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1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright(c) 2009-2012 Realtek Corporation.*/3 4#ifndef __RTL92D_REG_H__5#define __RTL92D_REG_H__6 7/* ----------------------------------------------------- */8/* 0x0000h ~ 0x00FFh System Configuration */9/* ----------------------------------------------------- */10#define REG_SYS_ISO_CTRL 0x000011#define REG_SYS_FUNC_EN 0x000212#define REG_APS_FSMCO 0x000413#define REG_SYS_CLKR 0x000814#define REG_9346CR 0x000A15#define REG_EE_VPD 0x000C16#define REG_AFE_MISC 0x001017#define REG_SPS0_CTRL 0x001118#define REG_POWER_OFF_IN_PROCESS 0x001719#define REG_SPS_OCP_CFG 0x001820#define REG_RSV_CTRL 0x001C21#define REG_RF_CTRL 0x001F22#define REG_LDOA15_CTRL 0x002023#define REG_LDOV12D_CTRL 0x002124#define REG_LDOHCI12_CTRL 0x002225#define REG_LPLDO_CTRL 0x002326#define REG_AFE_XTAL_CTRL 0x002427#define REG_AFE_PLL_CTRL 0x002828/* for 92d, DMDP,SMSP,DMSP contrl */29#define REG_MAC_PHY_CTRL 0x002c30#define REG_EFUSE_CTRL 0x003031#define REG_EFUSE_TEST 0x003432#define REG_PWR_DATA 0x003833#define REG_CAL_TIMER 0x003C34#define REG_ACLK_MON 0x003E35#define REG_GPIO_MUXCFG 0x004036#define REG_GPIO_IO_SEL 0x004237#define REG_MAC_PINMUX_CFG 0x004338#define REG_GPIO_PIN_CTRL 0x004439#define REG_GPIO_INTM 0x004840#define REG_LEDCFG0 0x004C41#define REG_LEDCFG1 0x004D42#define REG_LEDCFG2 0x004E43#define REG_LEDCFG3 0x004F44#define REG_FSIMR 0x005045#define REG_FSISR 0x005446 47#define REG_MCUFWDL 0x008048 49#define REG_HMEBOX_EXT_0 0x008850#define REG_HMEBOX_EXT_1 0x008A51#define REG_HMEBOX_EXT_2 0x008C52#define REG_HMEBOX_EXT_3 0x008E53#define SIZE_OF_REG_HMEBOX_EXT 254 55#define REG_EFUSE_ACCESS 0x00CF56 57#define REG_BIST_SCAN 0x00D058#define REG_BIST_RPT 0x00D459#define REG_BIST_ROM_RPT 0x00D860#define REG_USB_SIE_INTF 0x00E061#define REG_PCIE_MIO_INTF 0x00E462#define REG_PCIE_MIO_INTD 0x00E863#define REG_HPON_FSM 0x00EC64#define REG_SYS_CFG 0x00F065#define REG_MAC_PHY_CTRL_NORMAL 0x00f866 67#define REG_MAC0 0x008168#define REG_MAC1 0x005369#define FW_MAC0_READY 0x1870#define FW_MAC1_READY 0x1A71#define MAC0_ON BIT(7)72#define MAC1_ON BIT(0)73#define MAC0_READY BIT(0)74#define MAC1_READY BIT(0)75 76/* ----------------------------------------------------- */77/* 0x0100h ~ 0x01FFh MACTOP General Configuration */78/* ----------------------------------------------------- */79#define REG_CR 0x010080#define REG_PBP 0x010481#define REG_TRXDMA_CTRL 0x010C82#define REG_TRXFF_BNDY 0x011483#define REG_TRXFF_STATUS 0x011884#define REG_RXFF_PTR 0x011C85#define REG_HIMR 0x012086#define REG_HISR 0x012487#define REG_HIMRE 0x012888#define REG_HISRE 0x012C89#define REG_CPWM 0x012F90#define REG_FWIMR 0x013091#define REG_FWISR 0x013492#define REG_FTIMR 0x013893#define REG_PKTBUF_DBG_CTRL 0x014094#define REG_PKTBUF_DBG_DATA_L 0x014495#define REG_PKTBUF_DBG_DATA_H 0x014896 97#define REG_TC0_CTRL 0x015098#define REG_TC1_CTRL 0x015499#define REG_TC2_CTRL 0x0158100#define REG_TC3_CTRL 0x015C101#define REG_TC4_CTRL 0x0160102#define REG_TCUNIT_BASE 0x0164103#define REG_MBIST_START 0x0174104#define REG_MBIST_DONE 0x0178105#define REG_MBIST_FAIL 0x017C106#define REG_C2HEVT_MSG_NORMAL 0x01A0107#define REG_C2HEVT_MSG_TEST 0x01B8108#define REG_C2HEVT_CLEAR 0x01BF109#define REG_MCUTST_1 0x01c0110#define REG_FMETHR 0x01C8111#define REG_HMETFR 0x01CC112#define REG_HMEBOX_0 0x01D0113#define REG_HMEBOX_1 0x01D4114#define REG_HMEBOX_2 0x01D8115#define REG_HMEBOX_3 0x01DC116#define SIZE_OF_REG_HMEBOX 4117 118#define REG_LLT_INIT 0x01E0119#define REG_BB_ACCEESS_CTRL 0x01E8120#define REG_BB_ACCESS_DATA 0x01EC121 122 123/* ----------------------------------------------------- */124/* 0x0200h ~ 0x027Fh TXDMA Configuration */125/* ----------------------------------------------------- */126#define REG_RQPN 0x0200127#define REG_FIFOPAGE 0x0204128#define REG_TDECTRL 0x0208129#define REG_TXDMA_OFFSET_CHK 0x020C130#define REG_TXDMA_STATUS 0x0210131#define REG_RQPN_NPQ 0x0214132 133/* ----------------------------------------------------- */134/* 0x0280h ~ 0x02FFh RXDMA Configuration */135/* ----------------------------------------------------- */136#define REG_RXDMA_AGG_PG_TH 0x0280137#define REG_RXPKT_NUM 0x0284138#define REG_RXDMA_STATUS 0x0288139 140/* ----------------------------------------------------- */141/* 0x0300h ~ 0x03FFh PCIe */142/* ----------------------------------------------------- */143#define REG_PCIE_CTRL_REG 0x0300144#define REG_INT_MIG 0x0304145#define REG_BCNQ_DESA 0x0308146#define REG_HQ_DESA 0x0310147#define REG_MGQ_DESA 0x0318148#define REG_VOQ_DESA 0x0320149#define REG_VIQ_DESA 0x0328150#define REG_BEQ_DESA 0x0330151#define REG_BKQ_DESA 0x0338152#define REG_RX_DESA 0x0340153#define REG_DBI 0x0348154#define REG_DBI_WDATA 0x0348155#define REG_DBI_RDATA 0x034C156#define REG_DBI_CTRL 0x0350157#define REG_DBI_FLAG 0x0352158#define REG_MDIO 0x0354159#define REG_DBG_SEL 0x0360160#define REG_PCIE_HRPWM 0x0361161#define REG_PCIE_HCPWM 0x0363162#define REG_UART_CTRL 0x0364163#define REG_UART_TX_DESA 0x0370164#define REG_UART_RX_DESA 0x0378165 166/* ----------------------------------------------------- */167/* 0x0400h ~ 0x047Fh Protocol Configuration */168/* ----------------------------------------------------- */169#define REG_VOQ_INFORMATION 0x0400170#define REG_VIQ_INFORMATION 0x0404171#define REG_BEQ_INFORMATION 0x0408172#define REG_BKQ_INFORMATION 0x040C173#define REG_MGQ_INFORMATION 0x0410174#define REG_HGQ_INFORMATION 0x0414175#define REG_BCNQ_INFORMATION 0x0418176 177 178#define REG_CPU_MGQ_INFORMATION 0x041C179#define REG_FWHW_TXQ_CTRL 0x0420180#define REG_HWSEQ_CTRL 0x0423181#define REG_TXPKTBUF_BCNQ_BDNY 0x0424182#define REG_TXPKTBUF_MGQ_BDNY 0x0425183#define REG_MULTI_BCNQ_EN 0x0426184#define REG_MULTI_BCNQ_OFFSET 0x0427185#define REG_SPEC_SIFS 0x0428186#define REG_RL 0x042A187#define REG_DARFRC 0x0430188#define REG_RARFRC 0x0438189#define REG_RRSR 0x0440190#define REG_ARFR0 0x0444191#define REG_ARFR1 0x0448192#define REG_ARFR2 0x044C193#define REG_ARFR3 0x0450194#define REG_AGGLEN_LMT 0x0458195#define REG_AMPDU_MIN_SPACE 0x045C196#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D197#define REG_FAST_EDCA_CTRL 0x0460198#define REG_RD_RESP_PKT_TH 0x0463199#define REG_INIRTS_RATE_SEL 0x0480200#define REG_INIDATA_RATE_SEL 0x0484201#define REG_POWER_STATUS 0x04A4202#define REG_POWER_STAGE1 0x04B4203#define REG_POWER_STAGE2 0x04B8204#define REG_PKT_LIFE_TIME 0x04C0205#define REG_PKT_VO_VI_LIFE_TIME 0x04C0206#define REG_PKT_BE_BK_LIFE_TIME 0x04C2207#define REG_STBC_SETTING 0x04C4208#define REG_PROT_MODE_CTRL 0x04C8209#define REG_MAX_AGGR_NUM 0x04CA210#define REG_RTS_MAX_AGGR_NUM 0x04CB211#define REG_BAR_MODE_CTRL 0x04CC212#define REG_RA_TRY_RATE_AGG_LMT 0x04CF213#define REG_EARLY_MODE_CONTROL 0x4D0214#define REG_NQOS_SEQ 0x04DC215#define REG_QOS_SEQ 0x04DE216#define REG_NEED_CPU_HANDLE 0x04E0217#define REG_PKT_LOSE_RPT 0x04E1218#define REG_PTCL_ERR_STATUS 0x04E2219#define REG_DUMMY 0x04FC220 221/* ----------------------------------------------------- */222/* 0x0500h ~ 0x05FFh EDCA Configuration */223/* ----------------------------------------------------- */224#define REG_EDCA_VO_PARAM 0x0500225#define REG_EDCA_VI_PARAM 0x0504226#define REG_EDCA_BE_PARAM 0x0508227#define REG_EDCA_BK_PARAM 0x050C228#define REG_BCNTCFG 0x0510229#define REG_PIFS 0x0512230#define REG_RDG_PIFS 0x0513231#define REG_SIFS_CTX 0x0514232#define REG_SIFS_TRX 0x0516233#define REG_AGGR_BREAK_TIME 0x051A234#define REG_SLOT 0x051B235#define REG_TX_PTCL_CTRL 0x0520236#define REG_TXPAUSE 0x0522237#define REG_DIS_TXREQ_CLR 0x0523238#define REG_RD_CTRL 0x0524239#define REG_TBTT_PROHIBIT 0x0540240#define REG_RD_NAV_NXT 0x0544241#define REG_NAV_PROT_LEN 0x0546242#define REG_BCN_CTRL 0x0550243#define REG_BCN_CTRL_1 0x0551244#define REG_MBID_NUM 0x0552245#define REG_DUAL_TSF_RST 0x0553246#define REG_BCN_INTERVAL 0x0554247#define REG_MBSSID_BCN_SPACE 0x0554248#define REG_DRVERLYINT 0x0558249#define REG_BCNDMATIM 0x0559250#define REG_ATIMWND 0x055A251#define REG_USTIME_TSF 0x055C252#define REG_BCN_MAX_ERR 0x055D253#define REG_RXTSF_OFFSET_CCK 0x055E254#define REG_RXTSF_OFFSET_OFDM 0x055F255#define REG_TSFTR 0x0560256#define REG_INIT_TSFTR 0x0564257#define REG_PSTIMER 0x0580258#define REG_TIMER0 0x0584259#define REG_TIMER1 0x0588260#define REG_ACMHWCTRL 0x05C0261#define REG_ACMRSTCTRL 0x05C1262#define REG_ACMAVG 0x05C2263#define REG_VO_ADMTIME 0x05C4264#define REG_VI_ADMTIME 0x05C6265#define REG_BE_ADMTIME 0x05C8266#define REG_EDCA_RANDOM_GEN 0x05CC267#define REG_SCH_TXCMD 0x05D0268 269/* Dual MAC Co-Existence Register */270#define REG_DMC 0x05F0271 272/* ----------------------------------------------------- */273/* 0x0600h ~ 0x07FFh WMAC Configuration */274/* ----------------------------------------------------- */275#define REG_APSD_CTRL 0x0600276#define REG_BWOPMODE 0x0603277#define REG_TCR 0x0604278#define REG_RCR 0x0608279#define REG_RX_PKT_LIMIT 0x060C280#define REG_RX_DLK_TIME 0x060D281#define REG_RX_DRVINFO_SZ 0x060F282 283#define REG_MACID 0x0610284#define REG_BSSID 0x0618285#define REG_MAR 0x0620286#define REG_MBIDCAMCFG 0x0628287 288#define REG_USTIME_EDCA 0x0638289#define REG_MAC_SPEC_SIFS 0x063A290#define REG_RESP_SIFS_CCK 0x063C291#define REG_RESP_SIFS_OFDM 0x063E292#define REG_ACKTO 0x0640293#define REG_CTS2TO 0x0641294#define REG_EIFS 0x0642295 296 297/* WMA, BA, CCX */298#define REG_NAV_CTRL 0x0650299#define REG_BACAMCMD 0x0654300#define REG_BACAMCONTENT 0x0658301#define REG_LBDLY 0x0660302#define REG_FWDLY 0x0661303#define REG_RXERR_RPT 0x0664304#define REG_WMAC_TRXPTCL_CTL 0x0668305 306 307/* Security */308#define REG_CAMCMD 0x0670309#define REG_CAMWRITE 0x0674310#define REG_CAMREAD 0x0678311#define REG_CAMDBG 0x067C312#define REG_SECCFG 0x0680313 314/* Power */315#define REG_WOW_CTRL 0x0690316#define REG_PSSTATUS 0x0691317#define REG_PS_RX_INFO 0x0692318#define REG_LPNAV_CTRL 0x0694319#define REG_WKFMCAM_CMD 0x0698320#define REG_WKFMCAM_RWD 0x069C321#define REG_RXFLTMAP0 0x06A0322#define REG_RXFLTMAP1 0x06A2323#define REG_RXFLTMAP2 0x06A4324#define REG_BCN_PSR_RPT 0x06A8325#define REG_CALB32K_CTRL 0x06AC326#define REG_PKT_MON_CTRL 0x06B4327#define REG_BT_COEX_TABLE 0x06C0328#define REG_WMAC_RESP_TXINFO 0x06D8329 330#define REG_USB_Queue_Select_MAC0 0xFE44331#define REG_USB_Queue_Select_MAC1 0xFE47332 333/* ----------------------------------------------------- */334/* Redifine 8192C register definition for compatibility */335/* ----------------------------------------------------- */336#define CR9346 REG_9346CR337#define MSR (REG_CR + 2)338#define ISR REG_HISR339#define TSFR REG_TSFTR340 341#define MACIDR0 REG_MACID342#define MACIDR4 (REG_MACID + 4)343 344#define PBP REG_PBP345 346#define IDR0 MACIDR0347#define IDR4 MACIDR4348 349/* ----------------------------------------------------- */350/* 8192C (MSR) Media Status Register(Offset 0x4C, 8 bits)*/351/* ----------------------------------------------------- */352#define MSR_NOLINK 0x00353#define MSR_ADHOC 0x01354#define MSR_INFRA 0x02355#define MSR_AP 0x03356#define MSR_MASK 0x03357 358/* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */359/* ----------------------------------------------------- */360/* 8192C Response Rate Set Register(offset 0x181, 24bits)*/361/* ----------------------------------------------------- */362#define RRSR_RSC_OFFSET 21363#define RRSR_SHORT_OFFSET 23364#define RRSR_RSC_BW_40M 0x600000365#define RRSR_RSC_UPSUBCHNL 0x400000366#define RRSR_RSC_LOWSUBCHNL 0x200000367#define RRSR_SHORT 0x800000368#define RRSR_1M BIT(0)369#define RRSR_2M BIT(1)370#define RRSR_5_5M BIT(2)371#define RRSR_11M BIT(3)372#define RRSR_6M BIT(4)373#define RRSR_9M BIT(5)374#define RRSR_12M BIT(6)375#define RRSR_18M BIT(7)376#define RRSR_24M BIT(8)377#define RRSR_36M BIT(9)378#define RRSR_48M BIT(10)379#define RRSR_54M BIT(11)380#define RRSR_MCS0 BIT(12)381#define RRSR_MCS1 BIT(13)382#define RRSR_MCS2 BIT(14)383#define RRSR_MCS3 BIT(15)384#define RRSR_MCS4 BIT(16)385#define RRSR_MCS5 BIT(17)386#define RRSR_MCS6 BIT(18)387#define RRSR_MCS7 BIT(19)388#define BRSR_ACKSHORTPMB BIT(23)389 390/* ----------------------------------------------------- */391/* 8192C Rate Definition */392/* ----------------------------------------------------- */393/* CCK */394#define RATR_1M 0x00000001395#define RATR_2M 0x00000002396#define RATR_55M 0x00000004397#define RATR_11M 0x00000008398/* OFDM */399#define RATR_6M 0x00000010400#define RATR_9M 0x00000020401#define RATR_12M 0x00000040402#define RATR_18M 0x00000080403#define RATR_24M 0x00000100404#define RATR_36M 0x00000200405#define RATR_48M 0x00000400406#define RATR_54M 0x00000800407/* MCS 1 Spatial Stream */408#define RATR_MCS0 0x00001000409#define RATR_MCS1 0x00002000410#define RATR_MCS2 0x00004000411#define RATR_MCS3 0x00008000412#define RATR_MCS4 0x00010000413#define RATR_MCS5 0x00020000414#define RATR_MCS6 0x00040000415#define RATR_MCS7 0x00080000416/* MCS 2 Spatial Stream */417#define RATR_MCS8 0x00100000418#define RATR_MCS9 0x00200000419#define RATR_MCS10 0x00400000420#define RATR_MCS11 0x00800000421#define RATR_MCS12 0x01000000422#define RATR_MCS13 0x02000000423#define RATR_MCS14 0x04000000424#define RATR_MCS15 0x08000000425 426/* CCK */427#define RATE_1M BIT(0)428#define RATE_2M BIT(1)429#define RATE_5_5M BIT(2)430#define RATE_11M BIT(3)431/* OFDM */432#define RATE_6M BIT(4)433#define RATE_9M BIT(5)434#define RATE_12M BIT(6)435#define RATE_18M BIT(7)436#define RATE_24M BIT(8)437#define RATE_36M BIT(9)438#define RATE_48M BIT(10)439#define RATE_54M BIT(11)440/* MCS 1 Spatial Stream */441#define RATE_MCS0 BIT(12)442#define RATE_MCS1 BIT(13)443#define RATE_MCS2 BIT(14)444#define RATE_MCS3 BIT(15)445#define RATE_MCS4 BIT(16)446#define RATE_MCS5 BIT(17)447#define RATE_MCS6 BIT(18)448#define RATE_MCS7 BIT(19)449/* MCS 2 Spatial Stream */450#define RATE_MCS8 BIT(20)451#define RATE_MCS9 BIT(21)452#define RATE_MCS10 BIT(22)453#define RATE_MCS11 BIT(23)454#define RATE_MCS12 BIT(24)455#define RATE_MCS13 BIT(25)456#define RATE_MCS14 BIT(26)457#define RATE_MCS15 BIT(27)458 459/* ALL CCK Rate */460#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | \461 RATR_11M)462#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | \463 RATR_18M | RATR_24M | \464 RATR_36M | RATR_48M | RATR_54M)465#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \466 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \467 RATR_MCS6 | RATR_MCS7)468#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \469 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \470 RATR_MCS14 | RATR_MCS15)471 472/* ----------------------------------------------------- */473/* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */474/* ----------------------------------------------------- */475#define BW_OPMODE_20MHZ BIT(2)476#define BW_OPMODE_5G BIT(1)477#define BW_OPMODE_11J BIT(0)478 479 480/* ----------------------------------------------------- */481/* 8192C CAM Config Setting (offset 0x250, 1 byte) */482/* ----------------------------------------------------- */483#define CAM_VALID BIT(15)484#define CAM_NOTVALID 0x0000485#define CAM_USEDK BIT(5)486 487#define CAM_NONE 0x0488#define CAM_WEP40 0x01489#define CAM_TKIP 0x02490#define CAM_AES 0x04491#define CAM_WEP104 0x05492#define CAM_SMS4 0x6493 494 495#define TOTAL_CAM_ENTRY 32496#define HALF_CAM_ENTRY 16497 498#define CAM_WRITE BIT(16)499#define CAM_READ 0x00000000500#define CAM_POLLINIG BIT(31)501 502/* 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) */503#define WOW_PMEN BIT0 /* Power management Enable. */504#define WOW_WOMEN BIT1 /* WoW function on or off. */505#define WOW_MAGIC BIT2 /* Magic packet */506#define WOW_UWF BIT3 /* Unicast Wakeup frame. */507 508/* 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) */509/* ----------------------------------------------------- */510/* 8190 IMR/ISR bits (offset 0xfd, 8bits) */511/* ----------------------------------------------------- */512#define IMR8190_DISABLED 0x0513#define IMR_BCNDMAINT6 BIT(31)514#define IMR_BCNDMAINT5 BIT(30)515#define IMR_BCNDMAINT4 BIT(29)516#define IMR_BCNDMAINT3 BIT(28)517#define IMR_BCNDMAINT2 BIT(27)518#define IMR_BCNDMAINT1 BIT(26)519#define IMR_BCNDOK8 BIT(25)520#define IMR_BCNDOK7 BIT(24)521#define IMR_BCNDOK6 BIT(23)522#define IMR_BCNDOK5 BIT(22)523#define IMR_BCNDOK4 BIT(21)524#define IMR_BCNDOK3 BIT(20)525#define IMR_BCNDOK2 BIT(19)526#define IMR_BCNDOK1 BIT(18)527#define IMR_TIMEOUT2 BIT(17)528#define IMR_TIMEOUT1 BIT(16)529#define IMR_TXFOVW BIT(15)530#define IMR_PSTIMEOUT BIT(14)531#define IMR_BCNINT BIT(13)532#define IMR_RXFOVW BIT(12)533#define IMR_RDU BIT(11)534#define IMR_ATIMEND BIT(10)535#define IMR_BDOK BIT(9)536#define IMR_HIGHDOK BIT(8)537#define IMR_TBDOK BIT(7)538#define IMR_MGNTDOK BIT(6)539#define IMR_TBDER BIT(5)540#define IMR_BKDOK BIT(4)541#define IMR_BEDOK BIT(3)542#define IMR_VIDOK BIT(2)543#define IMR_VODOK BIT(1)544#define IMR_ROK BIT(0)545 546#define IMR_TXERR BIT(11)547#define IMR_RXERR BIT(10)548#define IMR_C2HCMD BIT(9)549#define IMR_CPWM BIT(8)550#define IMR_OCPINT BIT(1)551#define IMR_WLANOFF BIT(0)552 553/* ----------------------------------------------------- */554/* 8192C EFUSE */555/* ----------------------------------------------------- */556#define HWSET_MAX_SIZE 256557#define EFUSE_MAX_SECTION 32558#define EFUSE_REAL_CONTENT_LEN 512559 560/* ----------------------------------------------------- */561/* 8192C EEPROM/EFUSE share register definition. */562/* ----------------------------------------------------- */563#define EEPROM_DEFAULT_TSSI 0x0564#define EEPROM_DEFAULT_CRYSTALCAP 0x0565#define EEPROM_DEFAULT_THERMALMETER 0x12566 567#define EEPROM_DEFAULT_TXPOWERLEVEL_2G 0x2C568#define EEPROM_DEFAULT_TXPOWERLEVEL_5G 0x22569 570#define EEPROM_DEFAULT_HT40_2SDIFF 0x0571/* HT20<->40 default Tx Power Index Difference */572#define EEPROM_DEFAULT_HT20_DIFF 2573/* OFDM Tx Power index diff */574#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x4575#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0576#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0577 578#define EEPROM_CHANNEL_PLAN_FCC 0x0579#define EEPROM_CHANNEL_PLAN_IC 0x1580#define EEPROM_CHANNEL_PLAN_ETSI 0x2581#define EEPROM_CHANNEL_PLAN_SPAIN 0x3582#define EEPROM_CHANNEL_PLAN_FRANCE 0x4583#define EEPROM_CHANNEL_PLAN_MKK 0x5584#define EEPROM_CHANNEL_PLAN_MKK1 0x6585#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7586#define EEPROM_CHANNEL_PLAN_TELEC 0x8587#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9588#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA589#define EEPROM_CHANNEL_PLAN_NCC 0xB590#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80591 592#define EEPROM_CID_DEFAULT 0x0593#define EEPROM_CID_TOSHIBA 0x4594#define EEPROM_CID_CCX 0x10595#define EEPROM_CID_QMI 0x0D596#define EEPROM_CID_WHQL 0xFE597 598 599#define RTL8192_EEPROM_ID 0x8129600#define EEPROM_WAPI_SUPPORT 0x78601 602 603#define RTL8190_EEPROM_ID 0x8129 /* 0-1 */604#define EEPROM_HPON 0x02 /* LDO settings.2-5 */605#define EEPROM_CLK 0x06 /* Clock settings.6-7 */606#define EEPROM_MAC_FUNCTION 0x08 /* SE Test mode.8 */607 608#define EEPROM_VID 0x28 /* SE Vendor ID.A-B */609#define EEPROM_DID 0x2A /* SE Device ID. C-D */610#define EEPROM_SVID 0x2C /* SE Vendor ID.E-F */611#define EEPROM_SMID 0x2E /* SE PCI Subsystem ID. 10-11 */612 613#define EEPROM_VID_USB 0xC614#define EEPROM_PID_USB 0xE615#define EEPROM_ENDPOINT_SETTING 0x10616#define EEPROM_MAC_ADDR 0x16 /* SEMAC Address. 12-17 */617#define EEPROM_MAC_ADDR_MAC0_92DU 0x19618#define EEPROM_MAC_ADDR_MAC0_92D 0x55619#define EEPROM_MAC_ADDR_MAC1_92D 0x5B620 621/* 2.4G band Tx power index setting */622#define EEPROM_CCK_TX_PWR_INX_2G 0x61623#define EEPROM_HT40_1S_TX_PWR_INX_2G 0x67624#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G 0x6D625#define EEPROM_HT20_TX_PWR_INX_DIFF_2G 0x70626#define EEPROM_OFDM_TX_PWR_INX_DIFF_2G 0x73627#define EEPROM_HT40_MAX_PWR_OFFSET_2G 0x76628#define EEPROM_HT20_MAX_PWR_OFFSET_2G 0x79629 630/*5GL channel 32-64 */631#define EEPROM_HT40_1S_TX_PWR_INX_5GL 0x7C632#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GL 0x82633#define EEPROM_HT20_TX_PWR_INX_DIFF_5GL 0x85634#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GL 0x88635#define EEPROM_HT40_MAX_PWR_OFFSET_5GL 0x8B636#define EEPROM_HT20_MAX_PWR_OFFSET_5GL 0x8E637 638/* 5GM channel 100-140 */639#define EEPROM_HT40_1S_TX_PWR_INX_5GM 0x91640#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GM 0x97641#define EEPROM_HT20_TX_PWR_INX_DIFF_5GM 0x9A642#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GM 0x9D643#define EEPROM_HT40_MAX_PWR_OFFSET_5GM 0xA0644#define EEPROM_HT20_MAX_PWR_OFFSET_5GM 0xA3645 646/* 5GH channel 149-165 */647#define EEPROM_HT40_1S_TX_PWR_INX_5GH 0xA6648#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GH 0xAC649#define EEPROM_HT20_TX_PWR_INX_DIFF_5GH 0xAF650#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GH 0xB2651#define EEPROM_HT40_MAX_PWR_OFFSET_5GH 0xB5652#define EEPROM_HT20_MAX_PWR_OFFSET_5GH 0xB8653 654/* Map of supported channels. */655#define EEPROM_CHANNEL_PLAN 0xBB656#define EEPROM_IQK_DELTA 0xBC657#define EEPROM_LCK_DELTA 0xBC658#define EEPROM_XTAL_K 0xBD /* [7:5] */659#define EEPROM_TSSI_A_5G 0xBE660#define EEPROM_TSSI_B_5G 0xBF661#define EEPROM_TSSI_AB_5G 0xC0662#define EEPROM_THERMAL_METER 0xC3 /* [4:0] */663#define EEPROM_RF_OPT1 0xC4664#define EEPROM_RF_OPT2 0xC5665#define EEPROM_RF_OPT3 0xC6666#define EEPROM_RF_OPT4 0xC7667#define EEPROM_RF_OPT5 0xC8668#define EEPROM_RF_OPT6 0xC9669#define EEPROM_VERSION 0xCA670#define EEPROM_CUSTOMER_ID 0xCB671#define EEPROM_RF_OPT7 0xCC672 673#define EEPROM_DEF_PART_NO 0x3FD /* Byte */674#define EEPROME_CHIP_VERSION_L 0x3FF675#define EEPROME_CHIP_VERSION_H 0x3FE676 677/*678 * Current IOREG MAP679 * 0x0000h ~ 0x00FFh System Configuration (256 Bytes)680 * 0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes)681 * 0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes)682 * 0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes)683 * 0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes)684 * 0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes)685 * 0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes)686 * 0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes)687 * 0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes)688 */689 690/* ----------------------------------------------------- */691/* 8192C (RCR) (Offset 0x608, 32 bits) */692/* ----------------------------------------------------- */693#define RCR_APPFCS BIT(31)694#define RCR_APP_MIC BIT(30)695#define RCR_APP_ICV BIT(29)696#define RCR_APP_PHYST_RXFF BIT(28)697#define RCR_APP_BA_SSN BIT(27)698#define RCR_ENMBID BIT(24)699#define RCR_LSIGEN BIT(23)700#define RCR_MFBEN BIT(22)701#define RCR_HTC_LOC_CTRL BIT(14)702#define RCR_AMF BIT(13)703#define RCR_ACF BIT(12)704#define RCR_ADF BIT(11)705#define RCR_AICV BIT(9)706#define RCR_ACRC32 BIT(8)707#define RCR_CBSSID_BCN BIT(7)708#define RCR_CBSSID_DATA BIT(6)709#define RCR_APWRMGT BIT(5)710#define RCR_ADD3 BIT(4)711#define RCR_AB BIT(3)712#define RCR_AM BIT(2)713#define RCR_APM BIT(1)714#define RCR_AAP BIT(0)715#define RCR_MXDMA_OFFSET 8716#define RCR_FIFO_OFFSET 13717 718/* ----------------------------------------------------- */719/* 8192C Regsiter Bit and Content definition */720/* ----------------------------------------------------- */721/* ----------------------------------------------------- */722/* 0x0000h ~ 0x00FFh System Configuration */723/* ----------------------------------------------------- */724 725/* SPS0_CTRL */726#define SW18_FPWM BIT(3)727 728 729/* SYS_ISO_CTRL */730#define ISO_MD2PP BIT(0)731#define ISO_UA2USB BIT(1)732#define ISO_UD2CORE BIT(2)733#define ISO_PA2PCIE BIT(3)734#define ISO_PD2CORE BIT(4)735#define ISO_IP2MAC BIT(5)736#define ISO_DIOP BIT(6)737#define ISO_DIOE BIT(7)738#define ISO_EB2CORE BIT(8)739#define ISO_DIOR BIT(9)740 741#define PWC_EV25V BIT(14)742#define PWC_EV12V BIT(15)743 744 745/* SYS_FUNC_EN */746#define FEN_BBRSTB BIT(0)747#define FEN_BB_GLB_RSTN BIT(1)748#define FEN_USBA BIT(2)749#define FEN_UPLL BIT(3)750#define FEN_USBD BIT(4)751#define FEN_DIO_PCIE BIT(5)752#define FEN_PCIEA BIT(6)753#define FEN_PPLL BIT(7)754#define FEN_PCIED BIT(8)755#define FEN_DIOE BIT(9)756#define FEN_CPUEN BIT(10)757#define FEN_DCORE BIT(11)758#define FEN_ELDR BIT(12)759#define FEN_DIO_RF BIT(13)760#define FEN_HWPDN BIT(14)761#define FEN_MREGEN BIT(15)762 763/* APS_FSMCO */764#define PFM_LDALL BIT(0)765#define PFM_ALDN BIT(1)766#define PFM_LDKP BIT(2)767#define PFM_WOWL BIT(3)768#define ENPDN BIT(4)769#define PDN_PL BIT(5)770#define APFM_ONMAC BIT(8)771#define APFM_OFF BIT(9)772#define APFM_RSM BIT(10)773#define AFSM_HSUS BIT(11)774#define AFSM_PCIE BIT(12)775#define APDM_MAC BIT(13)776#define APDM_HOST BIT(14)777#define APDM_HPDN BIT(15)778#define RDY_MACON BIT(16)779#define SUS_HOST BIT(17)780#define ROP_ALD BIT(20)781#define ROP_PWR BIT(21)782#define ROP_SPS BIT(22)783#define SOP_MRST BIT(25)784#define SOP_FUSE BIT(26)785#define SOP_ABG BIT(27)786#define SOP_AMB BIT(28)787#define SOP_RCK BIT(29)788#define SOP_A8M BIT(30)789#define XOP_BTCK BIT(31)790 791/* SYS_CLKR */792#define ANAD16V_EN BIT(0)793#define ANA8M BIT(1)794#define MACSLP BIT(4)795#define LOADER_CLK_EN BIT(5)796#define _80M_SSC_DIS BIT(7)797#define _80M_SSC_EN_HO BIT(8)798#define PHY_SSC_RSTB BIT(9)799#define SEC_CLK_EN BIT(10)800#define MAC_CLK_EN BIT(11)801#define SYS_CLK_EN BIT(12)802#define RING_CLK_EN BIT(13)803 804 805/* 9346CR */806#define BOOT_FROM_EEPROM BIT(4)807#define EEPROM_EN BIT(5)808 809/* AFE_MISC */810#define AFE_BGEN BIT(0)811#define AFE_MBEN BIT(1)812#define MAC_ID_EN BIT(7)813 814/* RSV_CTRL */815#define WLOCK_ALL BIT(0)816#define WLOCK_00 BIT(1)817#define WLOCK_04 BIT(2)818#define WLOCK_08 BIT(3)819#define WLOCK_40 BIT(4)820#define R_DIS_PRST_0 BIT(5)821#define R_DIS_PRST_1 BIT(6)822#define LOCK_ALL_EN BIT(7)823 824/* RF_CTRL */825#define RF_EN BIT(0)826#define RF_RSTB BIT(1)827#define RF_SDMRSTB BIT(2)828 829 830 831/* LDOA15_CTRL */832#define LDA15_EN BIT(0)833#define LDA15_STBY BIT(1)834#define LDA15_OBUF BIT(2)835#define LDA15_REG_VOS BIT(3)836#define _LDA15_VOADJ(x) (((x) & 0x7) << 4)837 838 839 840/* LDOV12D_CTRL */841#define LDV12_EN BIT(0)842#define LDV12_SDBY BIT(1)843#define LPLDO_HSM BIT(2)844#define LPLDO_LSM_DIS BIT(3)845#define _LDV12_VADJ(x) (((x) & 0xF) << 4)846 847 848/* AFE_XTAL_CTRL */849#define XTAL_EN BIT(0)850#define XTAL_BSEL BIT(1)851#define _XTAL_BOSC(x) (((x) & 0x3) << 2)852#define _XTAL_CADJ(x) (((x) & 0xF) << 4)853#define XTAL_GATE_USB BIT(8)854#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9)855#define XTAL_GATE_AFE BIT(11)856#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12)857#define XTAL_RF_GATE BIT(14)858#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15)859#define XTAL_GATE_DIG BIT(17)860#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18)861#define XTAL_BT_GATE BIT(20)862#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21)863#define _XTAL_GPIO(x) (((x) & 0x7) << 23)864 865 866#define CKDLY_AFE BIT(26)867#define CKDLY_USB BIT(27)868#define CKDLY_DIG BIT(28)869#define CKDLY_BT BIT(29)870 871 872/* AFE_PLL_CTRL */873#define APLL_EN BIT(0)874#define APLL_320_EN BIT(1)875#define APLL_FREF_SEL BIT(2)876#define APLL_EDGE_SEL BIT(3)877#define APLL_WDOGB BIT(4)878#define APLL_LPFEN BIT(5)879 880#define APLL_REF_CLK_13MHZ 0x1881#define APLL_REF_CLK_19_2MHZ 0x2882#define APLL_REF_CLK_20MHZ 0x3883#define APLL_REF_CLK_25MHZ 0x4884#define APLL_REF_CLK_26MHZ 0x5885#define APLL_REF_CLK_38_4MHZ 0x6886#define APLL_REF_CLK_40MHZ 0x7887 888#define APLL_320EN BIT(14)889#define APLL_80EN BIT(15)890#define APLL_1MEN BIT(24)891 892 893/* EFUSE_CTRL */894#define ALD_EN BIT(18)895#define EF_PD BIT(19)896#define EF_FLAG BIT(31)897 898/* EFUSE_TEST */899#define EF_TRPT BIT(7)900#define LDOE25_EN BIT(31)901 902/* MCUFWDL */903#define MCUFWDL_EN BIT(0)904#define MCUFWDL_RDY BIT(1)905#define FWDL_CHKSUM_RPT BIT(2)906#define MACINI_RDY BIT(3)907#define BBINI_RDY BIT(4)908#define RFINI_RDY BIT(5)909#define WINTINI_RDY BIT(6)910#define MAC1_WINTINI_RDY BIT(11)911#define CPRST BIT(23)912 913/* REG_SYS_CFG */914#define XCLK_VLD BIT(0)915#define ACLK_VLD BIT(1)916#define UCLK_VLD BIT(2)917#define PCLK_VLD BIT(3)918#define PCIRSTB BIT(4)919#define V15_VLD BIT(5)920#define TRP_B15V_EN BIT(7)921#define SIC_IDLE BIT(8)922#define BD_MAC2 BIT(9)923#define BD_MAC1 BIT(10)924#define IC_MACPHY_MODE BIT(11)925#define PAD_HWPD_IDN BIT(22)926#define TRP_VAUX_EN BIT(23)927#define TRP_BT_EN BIT(24)928#define BD_PKG_SEL BIT(25)929#define BD_HCI_SEL BIT(26)930#define TYPE_ID BIT(27)931 932#define HCI_TXDMA_EN BIT(0)933#define HCI_RXDMA_EN BIT(1)934#define TXDMA_EN BIT(2)935#define RXDMA_EN BIT(3)936#define PROTOCOL_EN BIT(4)937#define SCHEDULE_EN BIT(5)938#define MACTXEN BIT(6)939#define MACRXEN BIT(7)940#define ENSWBCN BIT(8)941#define ENSEC BIT(9)942 943#define HQSEL_VOQ BIT(0)944#define HQSEL_VIQ BIT(1)945#define HQSEL_BEQ BIT(2)946#define HQSEL_BKQ BIT(3)947#define HQSEL_MGTQ BIT(4)948#define HQSEL_HIQ BIT(5)949 950#define TXDMA_HIQ_MAP GENMASK(15, 14)951#define TXDMA_MGQ_MAP GENMASK(13, 12)952#define TXDMA_BKQ_MAP GENMASK(11, 10)953#define TXDMA_BEQ_MAP GENMASK(9, 8)954#define TXDMA_VIQ_MAP GENMASK(7, 6)955#define TXDMA_VOQ_MAP GENMASK(5, 4)956 957#define QUEUE_LOW 1958#define QUEUE_NORMAL 2959#define QUEUE_HIGH 3960 961#define HPQ_MASK GENMASK(7, 0)962#define LPQ_MASK GENMASK(15, 8)963#define PUBQ_MASK GENMASK(23, 16)964#define LD_RQPN BIT(31)965 966#define DROP_DATA_EN BIT(9)967 968/* LLT_INIT */969#define _LLT_NO_ACTIVE 0x0970#define _LLT_WRITE_ACCESS 0x1971#define _LLT_READ_ACCESS 0x2972 973#define _LLT_INIT_DATA(x) ((x) & 0xFF)974#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)975#define _LLT_OP(x) (((x) & 0x3) << 30)976#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)977 978 979/* ----------------------------------------------------- */980/* 0x0400h ~ 0x047Fh Protocol Configuration */981/* ----------------------------------------------------- */982/* FWHW_TXQ_CTRL */983#define EN_AMPDU_RTY_NEW BIT(7)984#define EN_BCNQ_DL BIT(22)985 986#define RETRY_LIMIT_SHORT_SHIFT 8987#define RETRY_LIMIT_LONG_SHIFT 0988 989 990/* ----------------------------------------------------- */991/* 0x0500h ~ 0x05FFh EDCA Configuration */992/* ----------------------------------------------------- */993/* EDCA setting */994#define AC_PARAM_TXOP_LIMIT_OFFSET 16995#define AC_PARAM_ECW_MAX_OFFSET 12996#define AC_PARAM_ECW_MIN_OFFSET 8997#define AC_PARAM_AIFS_OFFSET 0998 999/* REG_RD_CTRL */1000#define DIS_EDCA_CNT_DWN BIT(11)1001 1002/* REG_BCN_CTRL */1003#define EN_BCN_FUNCTION BIT(3)1004#define DIS_TSF_UDT BIT(4)1005 1006/* ACMHWCTRL */1007#define ACMHW_HWEN BIT(0)1008#define ACMHW_BEQEN BIT(1)1009#define ACMHW_VIQEN BIT(2)1010#define ACMHW_VOQEN BIT(3)1011 1012/* ----------------------------------------------------- */1013/* 0x0600h ~ 0x07FFh WMAC Configuration */1014/* ----------------------------------------------------- */1015 1016/* TCR */1017#define TSFRST BIT(0)1018#define DIS_GCLK BIT(1)1019#define PAD_SEL BIT(2)1020#define PWR_ST BIT(6)1021#define PWRBIT_OW_EN BIT(7)1022#define ACRC BIT(8)1023#define CFENDFORM BIT(9)1024#define ICV BIT(10)1025 1026/* SECCFG */1027#define SCR_TXUSEDK BIT(0)1028#define SCR_RXUSEDK BIT(1)1029#define SCR_TXENCENABLE BIT(2)1030#define SCR_RXENCENABLE BIT(3)1031#define SCR_SKBYA2 BIT(4)1032#define SCR_NOSKMC BIT(5)1033#define SCR_TXBCUSEDK BIT(6)1034#define SCR_RXBCUSEDK BIT(7)1035 1036/* General definitions */1037#define LAST_ENTRY_OF_TX_PKT_BUFFER 2551038#define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC 1271039 1040#define POLLING_LLT_THRESHOLD 201041#define POLLING_READY_TIMEOUT_COUNT 10001042 1043/* Min Spacing related settings. */1044#define MAX_MSS_DENSITY_2T 0x131045#define MAX_MSS_DENSITY_1T 0x0A1046 1047 1048/* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */1049/* 1. PMAC duplicate register due to connection: */1050/* RF_Mode, TRxRN, NumOf L-STF */1051/* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */1052/* 3. RF register 0x00-2E */1053/* 4. Bit Mask for BB/RF register */1054/* 5. Other defintion for BB/RF R/W */1055 1056/* 3. Page8(0x800) */1057#define RFPGA0_RFMOD 0x8001058 1059#define RFPGA0_TXINFO 0x8041060#define RFPGA0_PSDFUNCTION 0x8081061 1062#define RFPGA0_TXGAINSTAGE 0x80c1063 1064#define RFPGA0_RFTIMING1 0x8101065#define RFPGA0_RFTIMING2 0x8141066 1067#define RFPGA0_XA_HSSIPARAMETER1 0x8201068#define RFPGA0_XA_HSSIPARAMETER2 0x8241069#define RFPGA0_XB_HSSIPARAMETER1 0x8281070#define RFPGA0_XB_HSSIPARAMETER2 0x82c1071 1072#define RFPGA0_XA_LSSIPARAMETER 0x8401073#define RFPGA0_XB_LSSIPARAMETER 0x8441074 1075#define RFPGA0_RFWAKEUPPARAMETER 0x8501076#define RFPGA0_RFSLEEPUPPARAMETER 0x8541077 1078#define RFPGA0_XAB_SWITCHCONTROL 0x8581079#define RFPGA0_XCD_SWITCHCONTROL 0x85c1080 1081#define RFPGA0_XA_RFINTERFACEOE 0x8601082#define RFPGA0_XB_RFINTERFACEOE 0x8641083 1084#define RFPGA0_XAB_RFINTERFACESW 0x8701085#define RFPGA0_XCD_RFINTERFACESW 0x8741086 1087#define RFPGA0_XAB_RFPARAMETER 0x8781088#define RFPGA0_XCD_RFPARAMETER 0x87c1089 1090#define RFPGA0_ANALOGPARAMETER1 0x8801091#define RFPGA0_ANALOGPARAMETER2 0x8841092#define RFPGA0_ANALOGPARAMETER3 0x8881093#define RFPGA0_ADDALLOCKEN 0x8881094#define RFPGA0_ANALOGPARAMETER4 0x88c1095 1096#define RFPGA0_XA_LSSIREADBACK 0x8a01097#define RFPGA0_XB_LSSIREADBACK 0x8a41098#define RFPGA0_XC_LSSIREADBACK 0x8a81099#define RFPGA0_XD_LSSIREADBACK 0x8ac1100 1101#define RFPGA0_PSDREPORT 0x8b41102#define TRANSCEIVERA_HSPI_READBACK 0x8b81103#define TRANSCEIVERB_HSPI_READBACK 0x8bc1104#define RFPGA0_XAB_RFINTERFACERB 0x8e01105#define RFPGA0_XCD_RFINTERFACERB 0x8e41106 1107/* 4. Page9(0x900) */1108#define RFPGA1_RFMOD 0x9001109 1110#define RFPGA1_TXBLOCK 0x9041111#define RFPGA1_DEBUGSELECT 0x9081112#define RFPGA1_TXINFO 0x90c1113 1114/* 5. PageA(0xA00) */1115#define RCCK0_SYSTEM 0xa001116 1117#define RCCK0_AFESSTTING 0xa041118#define RCCK0_CCA 0xa081119 1120#define RCCK0_RXAGC1 0xa0c1121#define RCCK0_RXAGC2 0xa101122 1123#define RCCK0_RXHP 0xa141124 1125#define RCCK0_DSPPARAMETER1 0xa181126#define RCCK0_DSPPARAMETER2 0xa1c1127 1128#define RCCK0_TXFILTER1 0xa201129#define RCCK0_TXFILTER2 0xa241130#define RCCK0_DEBUGPORT 0xa281131#define RCCK0_FALSEALARMREPORT 0xa2c1132#define RCCK0_TRSSIREPORT 0xa501133#define RCCK0_RXREPORT 0xa541134#define RCCK0_FACOUNTERLOWER 0xa5c1135#define RCCK0_FACOUNTERUPPER 0xa581136 1137#define RPDP_ANTA 0xb001138#define RCONFIG_ANTA 0xb681139#define RCONFIG_ANTB 0xb6c1140#define RPDP_ANTB 0xb701141 1142/* 6. PageC(0xC00) */1143#define ROFDM0_LSTF 0xc001144 1145#define ROFDM0_TRXPATHENABLE 0xc041146#define ROFDM0_TRMUXPAR 0xc081147#define ROFDM0_TRSWISOLATION 0xc0c1148 1149#define ROFDM0_XARXAFE 0xc101150#define ROFDM0_XARXIQIMBALANCE 0xc141151#define ROFDM0_XBRXAFE 0xc181152#define ROFDM0_XBRXIQIMBALANCE 0xc1c1153#define ROFDM0_XCRXAFE 0xc201154#define ROFDM0_XCRXIQIMBALANCE 0xc241155#define ROFDM0_XDRXAFE 0xc281156#define ROFDM0_XDRXIQIMBALANCE 0xc2c1157 1158#define ROFDM0_RXDETECTOR1 0xc301159#define ROFDM0_RXDETECTOR2 0xc341160#define ROFDM0_RXDETECTOR3 0xc381161#define ROFDM0_RXDETECTOR4 0xc3c1162 1163#define ROFDM0_RXDSP 0xc401164#define ROFDM0_CFOANDDAGC 0xc441165#define ROFDM0_CCADROPTHRESHOLD 0xc481166#define ROFDM0_ECCATHRESHOLD 0xc4c1167 1168#define ROFDM0_XAAGCCORE1 0xc501169#define ROFDM0_XAAGCCORE2 0xc541170#define ROFDM0_XBAGCCORE1 0xc581171#define ROFDM0_XBAGCCORE2 0xc5c1172#define ROFDM0_XCAGCCORE1 0xc601173#define ROFDM0_XCAGCCORE2 0xc641174#define ROFDM0_XDAGCCORE1 0xc681175#define ROFDM0_XDAGCCORE2 0xc6c1176 1177#define ROFDM0_AGCPARAMETER1 0xc701178#define ROFDM0_AGCPARAMETER2 0xc741179#define ROFDM0_AGCRSSITABLE 0xc781180#define ROFDM0_HTSTFAGC 0xc7c1181 1182#define ROFDM0_XATXIQIMBALANCE 0xc801183#define ROFDM0_XATXAFE 0xc841184#define ROFDM0_XBTXIQIMBALANCE 0xc881185#define ROFDM0_XBTXAFE 0xc8c1186#define ROFDM0_XCTXIQIMBALANCE 0xc901187#define ROFDM0_XCTXAFE 0xc941188#define ROFDM0_XDTXIQIMBALANCE 0xc981189#define ROFDM0_XDTXAFE 0xc9c1190 1191#define ROFDM0_RXHPPARAMETER 0xce01192#define ROFDM0_TXPSEUDONOISEWGT 0xce41193#define ROFDM0_FRAMESYNC 0xcf01194#define ROFDM0_DFSREPORT 0xcf41195#define ROFDM0_RXIQEXTANTA 0xca01196#define ROFDM0_TXCOEFF1 0xca41197#define ROFDM0_TXCOEFF2 0xca81198#define ROFDM0_TXCOEFF3 0xcac1199#define ROFDM0_TXCOEFF4 0xcb01200#define ROFDM0_TXCOEFF5 0xcb41201#define ROFDM0_TXCOEFF6 0xcb81202 1203/* 7. PageD(0xD00) */1204#define ROFDM1_LSTF 0xd001205#define ROFDM1_TRXPATHENABLE 0xd041206 1207#define ROFDM1_CFO 0xd081208#define ROFDM1_CSI1 0xd101209#define ROFDM1_SBD 0xd141210#define ROFDM1_CSI2 0xd181211#define ROFDM1_CFOTRACKING 0xd2c1212#define ROFDM1_TRXMESAURE1 0xd341213#define ROFDM1_INTFDET 0xd3c1214#define ROFDM1_PSEUDONOISESTATEAB 0xd501215#define ROFDM1_PSEUDONOISESTATECD 0xd541216#define ROFDM1_RXPSEUDONOISEWGT 0xd581217 1218#define ROFDM_PHYCOUNTER1 0xda01219#define ROFDM_PHYCOUNTER2 0xda41220#define ROFDM_PHYCOUNTER3 0xda81221 1222#define ROFDM_SHORTCFOAB 0xdac1223#define ROFDM_SHORTCFOCD 0xdb01224#define ROFDM_LONGCFOAB 0xdb41225#define ROFDM_LONGCFOCD 0xdb81226#define ROFDM_TAILCFOAB 0xdbc1227#define ROFDM_TAILCFOCD 0xdc01228#define ROFDM_PWMEASURE1 0xdc41229#define ROFDM_PWMEASURE2 0xdc81230#define ROFDM_BWREPORT 0xdcc1231#define ROFDM_AGCREPORT 0xdd01232#define ROFDM_RXSNR 0xdd41233#define ROFDM_RXEVMCSI 0xdd81234#define ROFDM_SIGREPORT 0xddc1235 1236/* 8. PageE(0xE00) */1237#define RTXAGC_A_RATE18_06 0xe001238#define RTXAGC_A_RATE54_24 0xe041239#define RTXAGC_A_CCK1_MCS32 0xe081240#define RTXAGC_A_MCS03_MCS00 0xe101241#define RTXAGC_A_MCS07_MCS04 0xe141242#define RTXAGC_A_MCS11_MCS08 0xe181243#define RTXAGC_A_MCS15_MCS12 0xe1c1244 1245#define RTXAGC_B_RATE18_06 0x8301246#define RTXAGC_B_RATE54_24 0x8341247#define RTXAGC_B_CCK1_55_MCS32 0x8381248#define RTXAGC_B_MCS03_MCS00 0x83c1249#define RTXAGC_B_MCS07_MCS04 0x8481250#define RTXAGC_B_MCS11_MCS08 0x84c1251#define RTXAGC_B_MCS15_MCS12 0x8681252#define RTXAGC_B_CCK11_A_CCK2_11 0x86c1253 1254#define RFPGA0_IQK 0xe281255#define RTX_IQK_TONE_A 0xe301256#define RRX_IQK_TONE_A 0xe341257#define RTX_IQK_PI_A 0xe381258#define RRX_IQK_PI_A 0xe3c1259 1260#define RTX_IQK 0xe401261#define RRX_IQK 0xe441262#define RIQK_AGC_PTS 0xe481263#define RIQK_AGC_RSP 0xe4c1264#define RTX_IQK_TONE_B 0xe501265#define RRX_IQK_TONE_B 0xe541266#define RTX_IQK_PI_B 0xe581267#define RRX_IQK_PI_B 0xe5c1268#define RIQK_AGC_CONT 0xe601269 1270#define RBLUE_TOOTH 0xe6c1271#define RRX_WAIT_CCA 0xe701272#define RTX_CCK_RFON 0xe741273#define RTX_CCK_BBON 0xe781274#define RTX_OFDM_RFON 0xe7c1275#define RTX_OFDM_BBON 0xe801276#define RTX_TO_RX 0xe841277#define RTX_TO_TX 0xe881278#define RRX_CCK 0xe8c1279 1280#define RTX_POWER_BEFORE_IQK_A 0xe941281#define RTX_POWER_AFTER_IQK_A 0xe9c1282 1283#define RRX_POWER_BEFORE_IQK_A 0xea01284#define RRX_POWER_BEFORE_IQK_A_2 0xea41285#define RRX_POWER_AFTER_IQK_A 0xea81286#define RRX_POWER_AFTER_IQK_A_2 0xeac1287 1288#define RTX_POWER_BEFORE_IQK_B 0xeb41289#define RTX_POWER_AFTER_IQK_B 0xebc1290 1291#define RRX_POWER_BEFORE_IQK_B 0xec01292#define RRX_POWER_BEFORE_IQK_B_2 0xec41293#define RRX_POWER_AFTER_IQK_B 0xec81294#define RRX_POWER_AFTER_IQK_B_2 0xecc1295 1296#define MASK_IQK_RESULT 0x03ff00001297 1298#define RRX_OFDM 0xed01299#define RRX_WAIT_RIFS 0xed41300#define RRX_TO_RX 0xed81301#define RSTANDBY 0xedc1302#define RSLEEP 0xee01303#define RPMPD_ANAEN 0xeec1304 1305/* RL6052 Register definition */1306#define RF_AC 0x001307 1308#define RF_IQADJ_G1 0x011309#define RF_IQADJ_G2 0x021310#define RF_BS_PA_APSET_G1_G4 0x031311#define RF_POW_TRSW 0x051312 1313#define RF_GAIN_RX 0x061314#define RF_GAIN_TX 0x071315 1316#define RF_TXM_IDAC 0x081317#define RF_TXPA_AG 0x0B1318#define RF_BS_IQGEN 0x0F1319 1320#define RF_MODE1 0x101321#define RF_MODE2 0x111322 1323#define RF_RX_AGC_HP 0x121324#define RF_TX_AGC 0x131325#define RF_BIAS 0x141326#define RF_IPA 0x151327#define RF_POW_ABILITY 0x171328#define RF_MODE_AG 0x181329#define rfchannel 0x181330#define RF_CHNLBW 0x181331#define RF_TOP 0x191332 1333#define RF_RX_G1 0x1A1334#define RF_RX_G2 0x1B1335 1336#define RF_RX_BB2 0x1C1337#define RF_RX_BB1 0x1D1338 1339#define RF_RCK1 0x1E1340#define RF_RCK2 0x1F1341 1342#define RF_TX_G1 0x201343#define RF_TX_G2 0x211344#define RF_TX_G3 0x221345 1346#define RF_TX_BB1 0x231347 1348#define RF_T_METER 0x421349 1350#define RF_SYN_G1 0x251351#define RF_SYN_G2 0x261352#define RF_SYN_G3 0x271353#define RF_SYN_G4 0x281354#define RF_SYN_G5 0x291355#define RF_SYN_G6 0x2A1356#define RF_SYN_G7 0x2B1357#define RF_SYN_G8 0x2C1358 1359#define RF_RCK_OS 0x301360 1361#define RF_TXPA_G1 0x311362#define RF_TXPA_G2 0x321363#define RF_TXPA_G3 0x331364 1365/* Bit Mask */1366 1367/* 2. Page8(0x800) */1368#define BRFMOD 0x11369#define BCCKTXSC 0x301370#define BCCKEN 0x10000001371#define BOFDMEN 0x20000001372 1373#define B3WIREDATALENGTH 0x8001374#define B3WIREADDRESSLENGTH 0x4001375 1376#define BRFSI_RFENV 0x101377 1378#define BLSSIREADADDRESS 0x7f8000001379#define BLSSIREADEDGE 0x800000001380#define BLSSIREADBACKDATA 0xfffff1381/* 4. PageA(0xA00) */1382#define BCCKSIDEBAND 0x101383 1384/* Other Definition */1385#define BBYTE0 0x11386#define BBYTE1 0x21387#define BBYTE2 0x41388#define BBYTE3 0x81389#define BWORD0 0x31390#define BWORD1 0xc1391#define BDWORD 0xf1392 1393#endif1394