1088 lines · c
1// SPDX-License-Identifier: GPL-2.02/* Copyright(c) 2009-2012 Realtek Corporation.*/3 4#include "../wifi.h"5#include "../efuse.h"6#include "../base.h"7#include "../regd.h"8#include "../cam.h"9#include "../ps.h"10#include "../pci.h"11#include "../rtl8192d/reg.h"12#include "../rtl8192d/def.h"13#include "../rtl8192d/dm_common.h"14#include "../rtl8192d/fw_common.h"15#include "../rtl8192d/hw_common.h"16#include "../rtl8192d/phy_common.h"17#include "phy.h"18#include "dm.h"19#include "fw.h"20#include "led.h"21#include "sw.h"22#include "hw.h"23 24u32 rtl92de_read_dword_dbi(struct ieee80211_hw *hw, u16 offset, u8 direct)25{26 struct rtl_priv *rtlpriv = rtl_priv(hw);27 u32 value;28 29 rtl_write_word(rtlpriv, REG_DBI_CTRL, (offset & 0xFFC));30 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(1) | direct);31 udelay(10);32 value = rtl_read_dword(rtlpriv, REG_DBI_RDATA);33 return value;34}35 36void rtl92de_write_dword_dbi(struct ieee80211_hw *hw,37 u16 offset, u32 value, u8 direct)38{39 struct rtl_priv *rtlpriv = rtl_priv(hw);40 41 rtl_write_word(rtlpriv, REG_DBI_CTRL, ((offset & 0xFFC) | 0xF000));42 rtl_write_dword(rtlpriv, REG_DBI_WDATA, value);43 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(0) | direct);44}45 46static void _rtl92de_set_bcn_ctrl_reg(struct ieee80211_hw *hw,47 u8 set_bits, u8 clear_bits)48{49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));50 struct rtl_priv *rtlpriv = rtl_priv(hw);51 52 rtlpci->reg_bcn_ctrl_val |= set_bits;53 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;54 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);55}56 57static void _rtl92de_enable_bcn_sub_func(struct ieee80211_hw *hw)58{59 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(1));60}61 62static void _rtl92de_disable_bcn_sub_func(struct ieee80211_hw *hw)63{64 _rtl92de_set_bcn_ctrl_reg(hw, BIT(1), 0);65}66 67void rtl92de_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)68{69 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));70 71 switch (variable) {72 case HW_VAR_RCR:73 *((u32 *) (val)) = rtlpci->receive_config;74 break;75 default:76 rtl92d_get_hw_reg(hw, variable, val);77 break;78 }79}80 81void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)82{83 struct rtl_priv *rtlpriv = rtl_priv(hw);84 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));85 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));86 87 switch (variable) {88 case HW_VAR_AC_PARAM: {89 u8 e_aci = *val;90 rtl92d_dm_init_edca_turbo(hw);91 if (rtlpci->acm_method != EACMWAY2_SW)92 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,93 &e_aci);94 break;95 }96 case HW_VAR_ACM_CTRL: {97 u8 e_aci = *val;98 union aci_aifsn *p_aci_aifsn =99 (union aci_aifsn *)(&(mac->ac[0].aifs));100 u8 acm = p_aci_aifsn->f.acm;101 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);102 103 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);104 if (acm) {105 switch (e_aci) {106 case AC0_BE:107 acm_ctrl |= ACMHW_BEQEN;108 break;109 case AC2_VI:110 acm_ctrl |= ACMHW_VIQEN;111 break;112 case AC3_VO:113 acm_ctrl |= ACMHW_VOQEN;114 break;115 default:116 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,117 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",118 acm);119 break;120 }121 } else {122 switch (e_aci) {123 case AC0_BE:124 acm_ctrl &= (~ACMHW_BEQEN);125 break;126 case AC2_VI:127 acm_ctrl &= (~ACMHW_VIQEN);128 break;129 case AC3_VO:130 acm_ctrl &= (~ACMHW_VOQEN);131 break;132 default:133 pr_err("switch case %#x not processed\n",134 e_aci);135 break;136 }137 }138 rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE,139 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",140 acm_ctrl);141 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);142 break;143 }144 case HW_VAR_RCR:145 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);146 rtlpci->receive_config = ((u32 *) (val))[0];147 break;148 case HW_VAR_H2C_FW_JOINBSSRPT: {149 u8 mstatus = (*val);150 u8 tmp_regcr, tmp_reg422;151 bool recover = false;152 153 if (mstatus == RT_MEDIA_CONNECT) {154 rtlpriv->cfg->ops->set_hw_reg(hw,155 HW_VAR_AID, NULL);156 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);157 rtl_write_byte(rtlpriv, REG_CR + 1,158 (tmp_regcr | BIT(0)));159 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3));160 _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0);161 tmp_reg422 = rtl_read_byte(rtlpriv,162 REG_FWHW_TXQ_CTRL + 2);163 if (tmp_reg422 & BIT(6))164 recover = true;165 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,166 tmp_reg422 & (~BIT(6)));167 rtl92d_set_fw_rsvdpagepkt(hw, 0);168 _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0);169 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4));170 if (recover)171 rtl_write_byte(rtlpriv,172 REG_FWHW_TXQ_CTRL + 2,173 tmp_reg422);174 rtl_write_byte(rtlpriv, REG_CR + 1,175 (tmp_regcr & ~(BIT(0))));176 }177 rtl92d_set_fw_joinbss_report_cmd(hw, (*val));178 break;179 }180 case HW_VAR_CORRECT_TSF: {181 u8 btype_ibss = val[0];182 183 if (btype_ibss)184 rtl92d_stop_tx_beacon(hw);185 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3));186 rtl_write_dword(rtlpriv, REG_TSFTR,187 (u32) (mac->tsf & 0xffffffff));188 rtl_write_dword(rtlpriv, REG_TSFTR + 4,189 (u32) ((mac->tsf >> 32) & 0xffffffff));190 _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0);191 if (btype_ibss)192 rtl92d_resume_tx_beacon(hw);193 194 break;195 }196 case HW_VAR_INT_MIGRATION: {197 bool int_migration = *(bool *) (val);198 199 if (int_migration) {200 /* Set interrupt migration timer and201 * corresponding Tx/Rx counter.202 * timer 25ns*0xfa0=100us for 0xf packets.203 * 0x306:Rx, 0x307:Tx */204 rtl_write_dword(rtlpriv, REG_INT_MIG, 0xfe000fa0);205 rtlpriv->dm.interrupt_migration = int_migration;206 } else {207 /* Reset all interrupt migration settings. */208 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);209 rtlpriv->dm.interrupt_migration = int_migration;210 }211 break;212 }213 case HW_VAR_INT_AC: {214 bool disable_ac_int = *((bool *) val);215 216 /* Disable four ACs interrupts. */217 if (disable_ac_int) {218 /* Disable VO, VI, BE and BK four AC interrupts219 * to gain more efficient CPU utilization.220 * When extremely highly Rx OK occurs,221 * we will disable Tx interrupts.222 */223 rtlpriv->cfg->ops->update_interrupt_mask(hw, 0,224 RT_AC_INT_MASKS);225 rtlpriv->dm.disable_tx_int = disable_ac_int;226 /* Enable four ACs interrupts. */227 } else {228 rtlpriv->cfg->ops->update_interrupt_mask(hw,229 RT_AC_INT_MASKS, 0);230 rtlpriv->dm.disable_tx_int = disable_ac_int;231 }232 break;233 }234 default:235 rtl92d_set_hw_reg(hw, variable, val);236 break;237 }238}239 240static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw)241{242 struct rtl_priv *rtlpriv = rtl_priv(hw);243 unsigned short i;244 u8 txpktbuf_bndy;245 u8 maxpage;246 bool status;247 u32 value32; /* High+low page number */248 u8 value8; /* normal page number */249 250 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {251 maxpage = 255;252 txpktbuf_bndy = 246;253 value8 = 0;254 value32 = 0x80bf0d29;255 } else {256 maxpage = 127;257 txpktbuf_bndy = 123;258 value8 = 0;259 value32 = 0x80750005;260 }261 262 /* Set reserved page for each queue */263 /* 11. RQPN 0x200[31:0] = 0x80BD1C1C */264 /* load RQPN */265 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);266 rtl_write_dword(rtlpriv, REG_RQPN, value32);267 268 /* 12. TXRKTBUG_PG_BNDY 0x114[31:0] = 0x27FF00F6 */269 /* TXRKTBUG_PG_BNDY */270 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,271 (rtl_read_word(rtlpriv, REG_TRXFF_BNDY + 2) << 16 |272 txpktbuf_bndy));273 274 /* 13. TDECTRL[15:8] 0x209[7:0] = 0xF6 */275 /* Beacon Head for TXDMA */276 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);277 278 /* 14. BCNQ_PGBNDY 0x424[7:0] = 0xF6 */279 /* BCNQ_PGBNDY */280 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);281 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);282 283 /* 15. WMAC_LBK_BF_HD 0x45D[7:0] = 0xF6 */284 /* WMAC_LBK_BF_HD */285 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);286 287 /* Set Tx/Rx page size (Tx must be 128 Bytes, */288 /* Rx can be 64,128,256,512,1024 bytes) */289 /* 16. PBP [7:0] = 0x11 */290 /* TRX page size */291 rtl_write_byte(rtlpriv, REG_PBP, 0x11);292 293 /* 17. DRV_INFO_SZ = 0x04 */294 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);295 296 /* 18. LLT_table_init(Adapter); */297 for (i = 0; i < (txpktbuf_bndy - 1); i++) {298 status = rtl92d_llt_write(hw, i, i + 1);299 if (!status)300 return status;301 }302 303 /* end of list */304 status = rtl92d_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);305 if (!status)306 return status;307 308 /* Make the other pages as ring buffer */309 /* This ring buffer is used as beacon buffer if we */310 /* config this MAC as two MAC transfer. */311 /* Otherwise used as local loopback buffer. */312 for (i = txpktbuf_bndy; i < maxpage; i++) {313 status = rtl92d_llt_write(hw, i, (i + 1));314 if (!status)315 return status;316 }317 318 /* Let last entry point to the start entry of ring buffer */319 status = rtl92d_llt_write(hw, maxpage, txpktbuf_bndy);320 if (!status)321 return status;322 323 return true;324}325 326static void _rtl92de_gen_refresh_led_state(struct ieee80211_hw *hw)327{328 struct rtl_priv *rtlpriv = rtl_priv(hw);329 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));330 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));331 enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;332 333 if (rtlpci->up_first_time)334 return;335 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)336 rtl92de_sw_led_on(hw, pin0);337 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)338 rtl92de_sw_led_on(hw, pin0);339 else340 rtl92de_sw_led_off(hw, pin0);341}342 343static bool _rtl92de_init_mac(struct ieee80211_hw *hw)344{345 struct rtl_priv *rtlpriv = rtl_priv(hw);346 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));347 unsigned char bytetmp;348 unsigned short wordtmp;349 u16 retry;350 351 rtl92d_phy_set_poweron(hw);352 /* Add for resume sequence of power domain according353 * to power document V11. Chapter V.11.... */354 /* 0. RSV_CTRL 0x1C[7:0] = 0x00 */355 /* unlock ISO/CLK/Power control register */356 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);357 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x05);358 359 /* 1. AFE_XTAL_CTRL [7:0] = 0x0F enable XTAL */360 /* 2. SPS0_CTRL 0x11[7:0] = 0x2b enable SPS into PWM mode */361 /* 3. delay (1ms) this is not necessary when initially power on */362 363 /* C. Resume Sequence */364 /* a. SPS0_CTRL 0x11[7:0] = 0x2b */365 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);366 367 /* b. AFE_XTAL_CTRL [7:0] = 0x0F */368 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);369 370 /* c. DRV runs power on init flow */371 372 /* auto enable WLAN */373 /* 4. APS_FSMCO 0x04[8] = 1; wait till 0x04[8] = 0 */374 /* Power On Reset for MAC Block */375 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);376 udelay(2);377 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);378 udelay(2);379 380 /* 5. Wait while 0x04[8] == 0 goto 2, otherwise goto 1 */381 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);382 udelay(50);383 retry = 0;384 while ((bytetmp & BIT(0)) && retry < 1000) {385 retry++;386 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);387 udelay(50);388 }389 390 /* Enable Radio off, GPIO, and LED function */391 /* 6. APS_FSMCO 0x04[15:0] = 0x0012 when enable HWPDN */392 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);393 394 /* release RF digital isolation */395 /* 7. SYS_ISO_CTRL 0x01[1] = 0x0; */396 /*Set REG_SYS_ISO_CTRL 0x1=0x82 to prevent wake# problem. */397 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);398 udelay(2);399 400 /* make sure that BB reset OK. */401 /* rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); */402 403 /* Disable REG_CR before enable it to assure reset */404 rtl_write_word(rtlpriv, REG_CR, 0x0);405 406 /* Release MAC IO register reset */407 rtl_write_word(rtlpriv, REG_CR, 0x2ff);408 409 /* clear stopping tx/rx dma */410 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x0);411 412 /* rtl_write_word(rtlpriv,REG_CR+2, 0x2); */413 414 /* System init */415 /* 18. LLT_table_init(Adapter); */416 if (!_rtl92de_llt_table_init(hw))417 return false;418 419 /* Clear interrupt and enable interrupt */420 /* 19. HISR 0x124[31:0] = 0xffffffff; */421 /* HISRE 0x12C[7:0] = 0xFF */422 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);423 rtl_write_byte(rtlpriv, REG_HISRE, 0xff);424 425 /* 20. HIMR 0x120[31:0] |= [enable INT mask bit map]; */426 /* 21. HIMRE 0x128[7:0] = [enable INT mask bit map] */427 /* The IMR should be enabled later after all init sequence428 * is finished. */429 430 /* 22. PCIE configuration space configuration */431 /* 23. Ensure PCIe Device 0x80[15:0] = 0x0143 (ASPM+CLKREQ), */432 /* and PCIe gated clock function is enabled. */433 /* PCIE configuration space will be written after434 * all init sequence.(Or by BIOS) */435 436 rtl92d_phy_config_maccoexist_rfpage(hw);437 438 /* THe below section is not related to power document Vxx . */439 /* This is only useful for driver and OS setting. */440 /* -------------------Software Relative Setting---------------------- */441 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);442 wordtmp &= 0xf;443 wordtmp |= 0xF771;444 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);445 446 /* Reported Tx status from HW for rate adaptive. */447 /* This should be realtive to power on step 14. But in document V11 */448 /* still not contain the description.!!! */449 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);450 451 /* Set Tx/Rx page size (Tx must be 128 Bytes,452 * Rx can be 64,128,256,512,1024 bytes) */453 /* rtl_write_byte(rtlpriv,REG_PBP, 0x11); */454 455 /* Set RCR register */456 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);457 /* rtl_write_byte(rtlpriv,REG_RX_DRVINFO_SZ, 4); */458 459 /* Set TCR register */460 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);461 462 /* disable earlymode */463 rtl_write_byte(rtlpriv, 0x4d0, 0x0);464 465 /* Set TX/RX descriptor physical address(from OS API). */466 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,467 rtlpci->tx_ring[BEACON_QUEUE].dma);468 rtl_write_dword(rtlpriv, REG_MGQ_DESA, rtlpci->tx_ring[MGNT_QUEUE].dma);469 rtl_write_dword(rtlpriv, REG_VOQ_DESA, rtlpci->tx_ring[VO_QUEUE].dma);470 rtl_write_dword(rtlpriv, REG_VIQ_DESA, rtlpci->tx_ring[VI_QUEUE].dma);471 rtl_write_dword(rtlpriv, REG_BEQ_DESA, rtlpci->tx_ring[BE_QUEUE].dma);472 rtl_write_dword(rtlpriv, REG_BKQ_DESA, rtlpci->tx_ring[BK_QUEUE].dma);473 rtl_write_dword(rtlpriv, REG_HQ_DESA, rtlpci->tx_ring[HIGH_QUEUE].dma);474 /* Set RX Desc Address */475 rtl_write_dword(rtlpriv, REG_RX_DESA,476 rtlpci->rx_ring[RX_MPDU_QUEUE].dma);477 478 /* if we want to support 64 bit DMA, we should set it here,479 * but now we do not support 64 bit DMA*/480 481 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x33);482 483 /* Reset interrupt migration setting when initialization */484 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);485 486 /* Reconsider when to do this operation after asking HWSD. */487 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);488 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));489 do {490 retry++;491 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);492 } while ((retry < 200) && !(bytetmp & BIT(7)));493 494 /* After MACIO reset,we must refresh LED state. */495 _rtl92de_gen_refresh_led_state(hw);496 497 /* Reset H2C protection register */498 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);499 500 return true;501}502 503static void _rtl92de_hw_configure(struct ieee80211_hw *hw)504{505 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));506 struct rtl_priv *rtlpriv = rtl_priv(hw);507 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));508 u8 reg_bw_opmode = BW_OPMODE_20MHZ;509 u32 reg_rrsr;510 511 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;512 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);513 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);514 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);515 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);516 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);517 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);518 rtl_write_word(rtlpriv, REG_RL, 0x0707);519 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);520 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);521 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);522 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);523 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);524 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);525 /* Aggregation threshold */526 if (rtlhal->macphymode == DUALMAC_DUALPHY)527 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb9726641);528 else if (rtlhal->macphymode == DUALMAC_SINGLEPHY)529 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x66626641);530 else531 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);532 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);533 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a);534 rtlpci->reg_bcn_ctrl_val = 0x1f;535 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);536 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);537 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);538 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);539 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);540 /* For throughput */541 rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0x6666);542 /* ACKTO for IOT issue. */543 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);544 /* Set Spec SIFS (used in NAV) */545 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);546 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);547 /* Set SIFS for CCK */548 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);549 /* Set SIFS for OFDM */550 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);551 /* Set Multicast Address. */552 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);553 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);554 switch (rtlpriv->phy.rf_type) {555 case RF_1T2R:556 case RF_1T1R:557 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);558 break;559 case RF_2T2R:560 case RF_2T2R_GREEN:561 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);562 break;563 }564}565 566static void _rtl92de_enable_aspm_back_door(struct ieee80211_hw *hw)567{568 struct rtl_priv *rtlpriv = rtl_priv(hw);569 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));570 571 rtl_write_byte(rtlpriv, 0x34b, 0x93);572 rtl_write_word(rtlpriv, 0x350, 0x870c);573 rtl_write_byte(rtlpriv, 0x352, 0x1);574 if (ppsc->support_backdoor)575 rtl_write_byte(rtlpriv, 0x349, 0x1b);576 else577 rtl_write_byte(rtlpriv, 0x349, 0x03);578 rtl_write_word(rtlpriv, 0x350, 0x2718);579 rtl_write_byte(rtlpriv, 0x352, 0x1);580}581 582int rtl92de_hw_init(struct ieee80211_hw *hw)583{584 struct rtl_priv *rtlpriv = rtl_priv(hw);585 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));586 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));587 struct rtl_phy *rtlphy = &(rtlpriv->phy);588 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));589 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));590 bool rtstatus = true;591 u8 tmp_u1b;592 int i;593 int err;594 unsigned long flags;595 596 rtlpci->being_init_adapter = true;597 rtlpci->init_ready = false;598 spin_lock_irqsave(&globalmutex_for_power_and_efuse, flags);599 /* we should do iqk after disable/enable */600 rtl92d_phy_reset_iqk_result(hw);601 /* rtlpriv->intf_ops->disable_aspm(hw); */602 rtstatus = _rtl92de_init_mac(hw);603 if (!rtstatus) {604 pr_err("Init MAC failed\n");605 err = 1;606 spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);607 return err;608 }609 err = rtl92d_download_fw(hw);610 spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);611 if (err) {612 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,613 "Failed to download FW. Init HW without FW..\n");614 return 1;615 }616 rtlhal->last_hmeboxnum = 0;617 rtlpriv->psc.fw_current_inpsmode = false;618 619 tmp_u1b = rtl_read_byte(rtlpriv, 0x605);620 tmp_u1b = tmp_u1b | 0x30;621 rtl_write_byte(rtlpriv, 0x605, tmp_u1b);622 623 if (rtlhal->earlymode_enable) {624 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,625 "EarlyMode Enabled!!!\n");626 627 tmp_u1b = rtl_read_byte(rtlpriv, 0x4d0);628 tmp_u1b = tmp_u1b | 0x1f;629 rtl_write_byte(rtlpriv, 0x4d0, tmp_u1b);630 631 rtl_write_byte(rtlpriv, 0x4d3, 0x80);632 633 tmp_u1b = rtl_read_byte(rtlpriv, 0x605);634 tmp_u1b = tmp_u1b | 0x40;635 rtl_write_byte(rtlpriv, 0x605, tmp_u1b);636 }637 638 if (mac->rdg_en) {639 rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xff);640 rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200);641 rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05);642 }643 644 rtl92d_phy_mac_config(hw);645 /* because last function modify RCR, so we update646 * rcr var here, or TP will unstable for receive_config647 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx648 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/649 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);650 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);651 652 rtl92d_phy_bb_config(hw);653 654 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;655 /* set before initialize RF */656 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);657 658 /* config RF */659 rtl92d_phy_rf_config(hw);660 661 /* After read predefined TXT, we must set BB/MAC/RF662 * register as our requirement */663 /* After load BB,RF params,we need do more for 92D. */664 rtl92d_update_bbrf_configuration(hw);665 /* set default value after initialize RF, */666 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);667 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,668 RF_CHNLBW, RFREG_OFFSET_MASK);669 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,670 RF_CHNLBW, RFREG_OFFSET_MASK);671 672 /*---- Set CCK and OFDM Block "ON"----*/673 if (rtlhal->current_bandtype == BAND_ON_2_4G)674 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);675 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);676 if (rtlhal->interfaceindex == 0) {677 /* RFPGA0_ANALOGPARAMETER2: cck clock select,678 * set to 20MHz by default */679 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |680 BIT(11), 3);681 } else {682 /* Mac1 */683 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(11) |684 BIT(10), 3);685 }686 687 _rtl92de_hw_configure(hw);688 689 /* reset hw sec */690 rtl_cam_reset_all_entry(hw);691 rtl92d_enable_hw_security_config(hw);692 693 /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */694 /* TX power index for different rate set. */695 rtl92d_phy_get_hw_reg_originalvalue(hw);696 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);697 698 ppsc->rfpwr_state = ERFON;699 700 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);701 702 _rtl92de_enable_aspm_back_door(hw);703 /* rtlpriv->intf_ops->enable_aspm(hw); */704 705 rtl92de_dm_init(hw);706 rtlpci->being_init_adapter = false;707 708 if (ppsc->rfpwr_state == ERFON) {709 rtl92d_phy_lc_calibrate(hw, IS_92D_SINGLEPHY(rtlhal->version));710 /* 5G and 2.4G must wait sometime to let RF LO ready */711 if (rtlhal->macphymode == DUALMAC_DUALPHY) {712 u32 tmp_rega;713 for (i = 0; i < 10000; i++) {714 udelay(MAX_STALL_TIME);715 716 tmp_rega = rtl_get_rfreg(hw,717 (enum radio_path)RF90_PATH_A,718 0x2a, MASKDWORD);719 720 if (((tmp_rega & BIT(11)) == BIT(11)))721 break;722 }723 /* check that loop was successful. If not, exit now */724 if (i == 10000) {725 rtlpci->init_ready = false;726 return 1;727 }728 }729 }730 rtlpci->init_ready = true;731 return err;732}733 734static int _rtl92de_set_media_status(struct ieee80211_hw *hw,735 enum nl80211_iftype type)736{737 struct rtl_priv *rtlpriv = rtl_priv(hw);738 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);739 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;740 741 bt_msr &= 0xfc;742 743 if (type == NL80211_IFTYPE_UNSPECIFIED ||744 type == NL80211_IFTYPE_STATION) {745 rtl92d_stop_tx_beacon(hw);746 _rtl92de_enable_bcn_sub_func(hw);747 } else if (type == NL80211_IFTYPE_ADHOC ||748 type == NL80211_IFTYPE_AP) {749 rtl92d_resume_tx_beacon(hw);750 _rtl92de_disable_bcn_sub_func(hw);751 } else {752 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,753 "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n",754 type);755 }756 switch (type) {757 case NL80211_IFTYPE_UNSPECIFIED:758 bt_msr |= MSR_NOLINK;759 ledaction = LED_CTL_LINK;760 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,761 "Set Network type to NO LINK!\n");762 break;763 case NL80211_IFTYPE_ADHOC:764 bt_msr |= MSR_ADHOC;765 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,766 "Set Network type to Ad Hoc!\n");767 break;768 case NL80211_IFTYPE_STATION:769 bt_msr |= MSR_INFRA;770 ledaction = LED_CTL_LINK;771 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,772 "Set Network type to STA!\n");773 break;774 case NL80211_IFTYPE_AP:775 bt_msr |= MSR_AP;776 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,777 "Set Network type to AP!\n");778 break;779 default:780 pr_err("Network type %d not supported!\n", type);781 return 1;782 }783 rtl_write_byte(rtlpriv, MSR, bt_msr);784 rtlpriv->cfg->ops->led_control(hw, ledaction);785 if ((bt_msr & MSR_MASK) == MSR_AP)786 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);787 else788 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);789 return 0;790}791 792void rtl92de_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)793{794 struct rtl_priv *rtlpriv = rtl_priv(hw);795 u32 reg_rcr;796 797 if (rtlpriv->psc.rfpwr_state != ERFON)798 return;799 800 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));801 802 if (check_bssid) {803 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);804 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));805 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4));806 } else if (!check_bssid) {807 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));808 _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0);809 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));810 }811}812 813int rtl92de_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)814{815 struct rtl_priv *rtlpriv = rtl_priv(hw);816 817 if (_rtl92de_set_media_status(hw, type))818 return -EOPNOTSUPP;819 820 /* check bssid */821 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {822 if (type != NL80211_IFTYPE_AP)823 rtl92de_set_check_bssid(hw, true);824 } else {825 rtl92de_set_check_bssid(hw, false);826 }827 return 0;828}829 830/* do iqk or reload iqk */831/* windows just rtl92d_phy_reload_iqk_setting in set channel,832 * but it's very strict for time sequence so we add833 * rtl92d_phy_reload_iqk_setting here */834void rtl92d_linked_set_reg(struct ieee80211_hw *hw)835{836 struct rtl_priv *rtlpriv = rtl_priv(hw);837 struct rtl_phy *rtlphy = &(rtlpriv->phy);838 u8 indexforchannel;839 u8 channel = rtlphy->current_channel;840 841 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);842 if (!rtlphy->iqk_matrix[indexforchannel].iqk_done) {843 rtl_dbg(rtlpriv, COMP_SCAN | COMP_INIT, DBG_DMESG,844 "Do IQK for channel:%d\n", channel);845 rtl92d_phy_iq_calibrate(hw);846 }847}848 849void rtl92de_enable_interrupt(struct ieee80211_hw *hw)850{851 struct rtl_priv *rtlpriv = rtl_priv(hw);852 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));853 854 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);855 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);856 rtlpci->irq_enabled = true;857}858 859void rtl92de_disable_interrupt(struct ieee80211_hw *hw)860{861 struct rtl_priv *rtlpriv = rtl_priv(hw);862 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));863 864 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);865 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);866 rtlpci->irq_enabled = false;867}868 869static void _rtl92de_poweroff_adapter(struct ieee80211_hw *hw)870{871 struct rtl_priv *rtlpriv = rtl_priv(hw);872 u8 u1b_tmp;873 unsigned long flags;874 875 rtlpriv->intf_ops->enable_aspm(hw);876 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);877 rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(3), 0);878 rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(15), 0);879 880 /* 0x20:value 05-->04 */881 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);882 883 /* ==== Reset digital sequence ====== */884 rtl92d_firmware_selfreset(hw);885 886 /* f. SYS_FUNC_EN 0x03[7:0]=0x51 reset MCU, MAC register, DCORE */887 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);888 889 /* g. MCUFWDL 0x80[1:0]=0 reset MCU ready status */890 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);891 892 /* ==== Pull GPIO PIN to balance level and LED control ====== */893 894 /* h. GPIO_PIN_CTRL 0x44[31:0]=0x000 */895 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);896 897 /* i. Value = GPIO_PIN_CTRL[7:0] */898 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);899 900 /* j. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); */901 /* write external PIN level */902 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL,903 0x00FF0000 | (u1b_tmp << 8));904 905 /* k. GPIO_MUXCFG 0x42 [15:0] = 0x0780 */906 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);907 908 /* l. LEDCFG 0x4C[15:0] = 0x8080 */909 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);910 911 /* ==== Disable analog sequence === */912 913 /* m. AFE_PLL_CTRL[7:0] = 0x80 disable PLL */914 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);915 916 /* n. SPS0_CTRL 0x11[7:0] = 0x22 enter PFM mode */917 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);918 919 /* o. AFE_XTAL_CTRL 0x24[7:0] = 0x0E disable XTAL, if No BT COEX */920 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);921 922 /* p. RSV_CTRL 0x1C[7:0] = 0x0E lock ISO/CLK/Power control register */923 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);924 925 /* ==== interface into suspend === */926 927 /* q. APS_FSMCO[15:8] = 0x58 PCIe suspend mode */928 /* According to power document V11, we need to set this */929 /* value as 0x18. Otherwise, we may not L0s sometimes. */930 /* This indluences power consumption. Bases on SD1's test, */931 /* set as 0x00 do not affect power current. And if it */932 /* is set as 0x18, they had ever met auto load fail problem. */933 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);934 935 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,936 "In PowerOff,reg0x%x=%X\n",937 REG_SPS0_CTRL, rtl_read_byte(rtlpriv, REG_SPS0_CTRL));938 /* r. Note: for PCIe interface, PON will not turn */939 /* off m-bias and BandGap in PCIe suspend mode. */940 941 /* 0x17[7] 1b': power off in process 0b' : power off over */942 if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {943 spin_lock_irqsave(&globalmutex_power, flags);944 u1b_tmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);945 u1b_tmp &= (~BIT(7));946 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1b_tmp);947 spin_unlock_irqrestore(&globalmutex_power, flags);948 }949 950 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<=======\n");951}952 953void rtl92de_card_disable(struct ieee80211_hw *hw)954{955 struct rtl_priv *rtlpriv = rtl_priv(hw);956 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));957 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));958 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));959 enum nl80211_iftype opmode;960 961 mac->link_state = MAC80211_NOLINK;962 opmode = NL80211_IFTYPE_UNSPECIFIED;963 _rtl92de_set_media_status(hw, opmode);964 965 if (rtlpci->driver_is_goingto_unload ||966 ppsc->rfoff_reason > RF_CHANGE_BY_PS)967 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);968 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);969 /* Power sequence for each MAC. */970 /* a. stop tx DMA */971 /* b. close RF */972 /* c. clear rx buf */973 /* d. stop rx DMA */974 /* e. reset MAC */975 976 /* a. stop tx DMA */977 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);978 udelay(50);979 980 /* b. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */981 982 /* c. ========RF OFF sequence========== */983 /* 0x88c[23:20] = 0xf. */984 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);985 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);986 987 /* APSD_CTRL 0x600[7:0] = 0x40 */988 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);989 990 /* Close antenna 0,0xc04,0xd04 */991 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0);992 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0);993 994 /* SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB state machine */995 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);996 997 /* Mac0 can not do Global reset. Mac1 can do. */998 /* SYS_FUNC_EN 0x02[7:0] = 0xE0 reset BB state machine */999 if (rtlpriv->rtlhal.interfaceindex == 1)1000 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);1001 udelay(50);1002 1003 /* d. stop tx/rx dma before disable REG_CR (0x100) to fix */1004 /* dma hang issue when disable/enable device. */1005 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);1006 udelay(50);1007 rtl_write_byte(rtlpriv, REG_CR, 0x0);1008 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==> Do power off.......\n");1009 if (rtl92d_phy_check_poweroff(hw))1010 _rtl92de_poweroff_adapter(hw);1011 return;1012}1013 1014void rtl92de_interrupt_recognized(struct ieee80211_hw *hw,1015 struct rtl_int *intvec)1016{1017 struct rtl_priv *rtlpriv = rtl_priv(hw);1018 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));1019 1020 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];1021 rtl_write_dword(rtlpriv, ISR, intvec->inta);1022}1023 1024void rtl92de_set_beacon_related_registers(struct ieee80211_hw *hw)1025{1026 struct rtl_priv *rtlpriv = rtl_priv(hw);1027 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));1028 u16 bcn_interval, atim_window;1029 1030 bcn_interval = mac->beacon_interval;1031 atim_window = 2;1032 rtl92de_disable_interrupt(hw);1033 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);1034 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);1035 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);1036 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x20);1037 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G)1038 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x30);1039 else1040 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x20);1041 rtl_write_byte(rtlpriv, 0x606, 0x30);1042}1043 1044void rtl92de_set_beacon_interval(struct ieee80211_hw *hw)1045{1046 struct rtl_priv *rtlpriv = rtl_priv(hw);1047 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));1048 u16 bcn_interval = mac->beacon_interval;1049 1050 rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG,1051 "beacon_interval:%d\n", bcn_interval);1052 rtl92de_disable_interrupt(hw);1053 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);1054 rtl92de_enable_interrupt(hw);1055}1056 1057void rtl92de_update_interrupt_mask(struct ieee80211_hw *hw,1058 u32 add_msr, u32 rm_msr)1059{1060 struct rtl_priv *rtlpriv = rtl_priv(hw);1061 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));1062 1063 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",1064 add_msr, rm_msr);1065 if (add_msr)1066 rtlpci->irq_mask[0] |= add_msr;1067 if (rm_msr)1068 rtlpci->irq_mask[0] &= (~rm_msr);1069 rtl92de_disable_interrupt(hw);1070 rtl92de_enable_interrupt(hw);1071}1072 1073void rtl92de_suspend(struct ieee80211_hw *hw)1074{1075 struct rtl_priv *rtlpriv = rtl_priv(hw);1076 1077 rtlpriv->rtlhal.macphyctl_reg = rtl_read_byte(rtlpriv,1078 REG_MAC_PHY_CTRL_NORMAL);1079}1080 1081void rtl92de_resume(struct ieee80211_hw *hw)1082{1083 struct rtl_priv *rtlpriv = rtl_priv(hw);1084 1085 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL,1086 rtlpriv->rtlhal.macphyctl_reg);1087}1088