398 lines · c
1// SPDX-License-Identifier: GPL-2.02/* Copyright(c) 2009-2012 Realtek Corporation.*/3 4#include "../wifi.h"5#include "../core.h"6#include "../pci.h"7#include "../base.h"8#include "../rtl8192d/reg.h"9#include "../rtl8192d/def.h"10#include "../rtl8192d/dm_common.h"11#include "../rtl8192d/hw_common.h"12#include "../rtl8192d/phy_common.h"13#include "../rtl8192d/trx_common.h"14#include "phy.h"15#include "dm.h"16#include "hw.h"17#include "sw.h"18#include "trx.h"19#include "led.h"20 21#include <linux/module.h>22 23static void rtl92d_init_aspm_vars(struct ieee80211_hw *hw)24{25 struct rtl_priv *rtlpriv = rtl_priv(hw);26 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));27 28 /*29 * ASPM PS mode.30 * 0 - Disable ASPM,31 * 1 - Enable ASPM without Clock Req,32 * 2 - Enable ASPM with Clock Req,33 * 3 - Alwyas Enable ASPM with Clock Req,34 * 4 - Always Enable ASPM without Clock Req.35 * set default to RTL8192CE:3 RTL8192E:236 * */37 rtlpci->const_pci_aspm = 3;38 39 /*Setting for PCI-E device */40 rtlpci->const_devicepci_aspm_setting = 0x03;41 42 /*Setting for PCI-E bridge */43 rtlpci->const_hostpci_aspm_setting = 0x02;44 45 /*46 * In Hw/Sw Radio Off situation.47 * 0 - Default,48 * 1 - From ASPM setting without low Mac Pwr,49 * 2 - From ASPM setting with low Mac Pwr,50 * 3 - Bus D351 * set default to RTL8192CE:0 RTL8192SE:252 */53 rtlpci->const_hwsw_rfoff_d3 = 0;54 55 /*56 * This setting works for those device with57 * backdoor ASPM setting such as EPHY setting.58 * 0 - Not support ASPM,59 * 1 - Support ASPM,60 * 2 - According to chipset.61 */62 rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;63}64 65static int rtl92d_init_sw_vars(struct ieee80211_hw *hw)66{67 int err;68 u8 tid;69 struct rtl_priv *rtlpriv = rtl_priv(hw);70 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));71 char *fw_name = "rtlwifi/rtl8192defw.bin";72 73 rtlpriv->dm.dm_initialgain_enable = true;74 rtlpriv->dm.dm_flag = 0;75 rtlpriv->dm.disable_framebursting = false;76 rtlpriv->dm.thermalvalue = 0;77 rtlpriv->dm.useramask = true;78 79 /* dual mac */80 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G)81 rtlpriv->phy.current_channel = 36;82 else83 rtlpriv->phy.current_channel = 1;84 85 if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {86 rtlpriv->rtlhal.disable_amsdu_8k = true;87 /* No long RX - reduce fragmentation */88 rtlpci->rxbuffersize = 4096;89 }90 91 rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);92 93 rtlpci->receive_config = (94 RCR_APPFCS95 | RCR_AMF96 | RCR_ADF97 | RCR_APP_MIC98 | RCR_APP_ICV99 | RCR_AICV100 | RCR_ACRC32101 | RCR_AB102 | RCR_AM103 | RCR_APM104 | RCR_APP_PHYST_RXFF105 | RCR_HTC_LOC_CTRL106 );107 108 rtlpci->irq_mask[0] = (u32) (109 IMR_ROK110 | IMR_VODOK111 | IMR_VIDOK112 | IMR_BEDOK113 | IMR_BKDOK114 | IMR_MGNTDOK115 | IMR_HIGHDOK116 | IMR_BDOK117 | IMR_RDU118 | IMR_RXFOVW119 );120 121 rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD);122 123 /* for LPS & IPS */124 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;125 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;126 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;127 if (!rtlpriv->psc.inactiveps)128 pr_info("Power Save off (module option)\n");129 if (!rtlpriv->psc.fwctrl_lps)130 pr_info("FW Power Save off (module option)\n");131 rtlpriv->psc.reg_fwctrl_lps = 3;132 rtlpriv->psc.reg_max_lps_awakeintvl = 5;133 /* for ASPM, you can close aspm through134 * set const_support_pciaspm = 0 */135 rtl92d_init_aspm_vars(hw);136 137 if (rtlpriv->psc.reg_fwctrl_lps == 1)138 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;139 else if (rtlpriv->psc.reg_fwctrl_lps == 2)140 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;141 else if (rtlpriv->psc.reg_fwctrl_lps == 3)142 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;143 144 /* for early mode */145 rtlpriv->rtlhal.earlymode_enable = false;146 for (tid = 0; tid < 8; tid++)147 skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]);148 149 /* for firmware buf */150 rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);151 if (!rtlpriv->rtlhal.pfirmware) {152 pr_err("Can't alloc buffer for fw\n");153 return 1;154 }155 156 rtlpriv->max_fw_size = 0x8000;157 pr_info("Driver for Realtek RTL8192DE WLAN interface\n");158 pr_info("Loading firmware file %s\n", fw_name);159 160 /* request fw */161 err = request_firmware_nowait(THIS_MODULE, 1, fw_name,162 rtlpriv->io.dev, GFP_KERNEL, hw,163 rtl_fw_cb);164 if (err) {165 pr_err("Failed to request firmware!\n");166 vfree(rtlpriv->rtlhal.pfirmware);167 rtlpriv->rtlhal.pfirmware = NULL;168 return 1;169 }170 171 return 0;172}173 174static void rtl92d_deinit_sw_vars(struct ieee80211_hw *hw)175{176 struct rtl_priv *rtlpriv = rtl_priv(hw);177 u8 tid;178 179 if (rtlpriv->rtlhal.pfirmware) {180 vfree(rtlpriv->rtlhal.pfirmware);181 rtlpriv->rtlhal.pfirmware = NULL;182 }183 for (tid = 0; tid < 8; tid++)184 skb_queue_purge(&rtlpriv->mac80211.skb_waitq[tid]);185}186 187static struct rtl_hal_ops rtl8192de_hal_ops = {188 .init_sw_vars = rtl92d_init_sw_vars,189 .deinit_sw_vars = rtl92d_deinit_sw_vars,190 .read_eeprom_info = rtl92d_read_eeprom_info,191 .interrupt_recognized = rtl92de_interrupt_recognized,192 .hw_init = rtl92de_hw_init,193 .hw_disable = rtl92de_card_disable,194 .hw_suspend = rtl92de_suspend,195 .hw_resume = rtl92de_resume,196 .enable_interrupt = rtl92de_enable_interrupt,197 .disable_interrupt = rtl92de_disable_interrupt,198 .set_network_type = rtl92de_set_network_type,199 .set_chk_bssid = rtl92de_set_check_bssid,200 .set_qos = rtl92d_set_qos,201 .set_bcn_reg = rtl92de_set_beacon_related_registers,202 .set_bcn_intv = rtl92de_set_beacon_interval,203 .update_interrupt_mask = rtl92de_update_interrupt_mask,204 .get_hw_reg = rtl92de_get_hw_reg,205 .set_hw_reg = rtl92de_set_hw_reg,206 .update_rate_tbl = rtl92d_update_hal_rate_tbl,207 .fill_tx_desc = rtl92de_tx_fill_desc,208 .fill_tx_cmddesc = rtl92de_tx_fill_cmddesc,209 .query_rx_desc = rtl92d_rx_query_desc,210 .set_channel_access = rtl92d_update_channel_access_setting,211 .radio_onoff_checking = rtl92d_gpio_radio_on_off_checking,212 .set_bw_mode = rtl92d_phy_set_bw_mode,213 .switch_channel = rtl92d_phy_sw_chnl,214 .dm_watchdog = rtl92de_dm_watchdog,215 .scan_operation_backup = rtl_phy_scan_operation_backup,216 .set_rf_power_state = rtl92d_phy_set_rf_power_state,217 .led_control = rtl92de_led_control,218 .set_desc = rtl92d_set_desc,219 .get_desc = rtl92d_get_desc,220 .is_tx_desc_closed = rtl92de_is_tx_desc_closed,221 .tx_polling = rtl92de_tx_polling,222 .enable_hw_sec = rtl92d_enable_hw_security_config,223 .set_key = rtl92d_set_key,224 .get_bbreg = rtl92d_phy_query_bb_reg,225 .set_bbreg = rtl92d_phy_set_bb_reg,226 .get_rfreg = rtl92d_phy_query_rf_reg,227 .set_rfreg = rtl92d_phy_set_rf_reg,228 .linked_set_reg = rtl92d_linked_set_reg,229 .get_btc_status = rtl_btc_status_false,230 .phy_iq_calibrate = rtl92d_phy_iq_calibrate,231 .phy_lc_calibrate = rtl92d_phy_lc_calibrate,232};233 234static struct rtl_mod_params rtl92de_mod_params = {235 .sw_crypto = false,236 .inactiveps = true,237 .swctrl_lps = true,238 .fwctrl_lps = false,239 .aspm_support = 1,240 .debug_level = 0,241 .debug_mask = 0,242};243 244static const struct rtl_hal_cfg rtl92de_hal_cfg = {245 .bar_id = 2,246 .write_readback = true,247 .name = "rtl8192de",248 .ops = &rtl8192de_hal_ops,249 .mod_params = &rtl92de_mod_params,250 251 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,252 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,253 .maps[SYS_CLK] = REG_SYS_CLKR,254 .maps[MAC_RCR_AM] = RCR_AM,255 .maps[MAC_RCR_AB] = RCR_AB,256 .maps[MAC_RCR_ACRC32] = RCR_ACRC32,257 .maps[MAC_RCR_ACF] = RCR_ACF,258 .maps[MAC_RCR_AAP] = RCR_AAP,259 260 .maps[EFUSE_TEST] = REG_EFUSE_TEST,261 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,262 .maps[EFUSE_CLK] = 0, /* just for 92se */263 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,264 .maps[EFUSE_PWC_EV12V] = PWC_EV12V,265 .maps[EFUSE_FEN_ELDR] = FEN_ELDR,266 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,267 .maps[EFUSE_ANA8M] = 0, /* just for 92se */268 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,269 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,270 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,271 272 .maps[RWCAM] = REG_CAMCMD,273 .maps[WCAMI] = REG_CAMWRITE,274 .maps[RCAMO] = REG_CAMREAD,275 .maps[CAMDBG] = REG_CAMDBG,276 .maps[SECR] = REG_SECCFG,277 .maps[SEC_CAM_NONE] = CAM_NONE,278 .maps[SEC_CAM_WEP40] = CAM_WEP40,279 .maps[SEC_CAM_TKIP] = CAM_TKIP,280 .maps[SEC_CAM_AES] = CAM_AES,281 .maps[SEC_CAM_WEP104] = CAM_WEP104,282 283 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,284 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,285 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,286 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,287 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,288 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,289 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,290 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,291 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,292 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,293 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,294 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,295 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,296 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,297 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,298 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,299 300 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,301 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,302 .maps[RTL_IMR_BCNINT] = IMR_BCNINT,303 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,304 .maps[RTL_IMR_RDU] = IMR_RDU,305 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,306 .maps[RTL_IMR_BDOK] = IMR_BDOK,307 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,308 .maps[RTL_IMR_TBDER] = IMR_TBDER,309 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,310 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,311 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,312 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,313 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,314 .maps[RTL_IMR_VODOK] = IMR_VODOK,315 .maps[RTL_IMR_ROK] = IMR_ROK,316 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),317 318 .maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M,319 .maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M,320 .maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M,321 .maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M,322 .maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M,323 .maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M,324 .maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M,325 .maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M,326 .maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M,327 .maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M,328 .maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M,329 .maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M,330 331 .maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7,332 .maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15,333};334 335static const struct pci_device_id rtl92de_pci_ids[] = {336 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8193, rtl92de_hal_cfg)},337 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x002B, rtl92de_hal_cfg)},338 {},339};340 341MODULE_DEVICE_TABLE(pci, rtl92de_pci_ids);342 343MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");344MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");345MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");346MODULE_LICENSE("GPL");347MODULE_DESCRIPTION("Realtek 8192DE 802.11n Dual Mac PCI wireless");348MODULE_FIRMWARE("rtlwifi/rtl8192defw.bin");349 350module_param_named(swenc, rtl92de_mod_params.sw_crypto, bool, 0444);351module_param_named(debug_level, rtl92de_mod_params.debug_level, int, 0644);352module_param_named(ips, rtl92de_mod_params.inactiveps, bool, 0444);353module_param_named(swlps, rtl92de_mod_params.swctrl_lps, bool, 0444);354module_param_named(fwlps, rtl92de_mod_params.fwctrl_lps, bool, 0444);355module_param_named(aspm, rtl92de_mod_params.aspm_support, int, 0444);356module_param_named(debug_mask, rtl92de_mod_params.debug_mask, ullong, 0644);357MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");358MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");359MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 1)\n");360MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 0)\n");361MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");362MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");363MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");364 365static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);366 367static struct pci_driver rtl92de_driver = {368 .name = KBUILD_MODNAME,369 .id_table = rtl92de_pci_ids,370 .probe = rtl_pci_probe,371 .remove = rtl_pci_disconnect,372 .driver.pm = &rtlwifi_pm_ops,373};374 375/* add global spin lock to solve the problem that376 * Dul mac register operation on the same time */377DEFINE_SPINLOCK(globalmutex_power);378DEFINE_SPINLOCK(globalmutex_for_fwdownload);379DEFINE_SPINLOCK(globalmutex_for_power_and_efuse);380 381static int __init rtl92de_module_init(void)382{383 int ret = 0;384 385 ret = pci_register_driver(&rtl92de_driver);386 if (ret)387 WARN_ONCE(true, "rtl8192de: No device found\n");388 return ret;389}390 391static void __exit rtl92de_module_exit(void)392{393 pci_unregister_driver(&rtl92de_driver);394}395 396module_init(rtl92de_module_init);397module_exit(rtl92de_module_exit);398