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1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright(c) 2009-2014 Realtek Corporation.*/3 4#ifndef __RTL92E_DM_H__5#define __RTL92E_DM_H__6 7#define OFDMCCA_TH 5008#define BW_IND_BIAS 5009#define MF_USC 210#define MF_LSC 111#define MF_USC_LSC 012#define MONITOR_TIME 3013 14#define MAIN_ANT 015#define AUX_ANT 116#define MAIN_ANT_CG_TRX 117#define AUX_ANT_CG_TRX 018#define MAIN_ANT_CGCS_RX 019#define AUX_ANT_CGCS_RX 120 21/*RF REG LIST*/22#define DM_REG_RF_MODE_11N 0x0023#define DM_REG_RF_0B_11N 0x0B24#define DM_REG_CHNBW_11N 0x1825#define DM_REG_T_METER_11N 0x2426#define DM_REG_RF_25_11N 0x2527#define DM_REG_RF_26_11N 0x2628#define DM_REG_RF_27_11N 0x2729#define DM_REG_RF_2B_11N 0x2B30#define DM_REG_RF_2C_11N 0x2C31#define DM_REG_RXRF_A3_11N 0x3C32#define DM_REG_T_METER_92D_11N 0x4233#define DM_REG_T_METER_92E_11N 0x4234 35/*BB REG LIST*/36/*PAGE 8 */37#define DM_REG_BB_CTRL_11N 0x80038#define DM_REG_RF_PIN_11N 0x80439#define DM_REG_PSD_CTRL_11N 0x80840#define DM_REG_TX_ANT_CTRL_11N 0x80C41#define DM_REG_BB_PWR_SAV5_11N 0x81842#define DM_REG_CCK_RPT_FORMAT_11N 0x82443#define DM_REG_RX_DEFUALT_A_11N 0x85844#define DM_REG_RX_DEFUALT_B_11N 0x85A45#define DM_REG_BB_PWR_SAV3_11N 0x85C46#define DM_REG_ANTSEL_CTRL_11N 0x86047#define DM_REG_RX_ANT_CTRL_11N 0x86448#define DM_REG_PIN_CTRL_11N 0x87049#define DM_REG_BB_PWR_SAV1_11N 0x87450#define DM_REG_ANTSEL_PATH_11N 0x87851#define DM_REG_BB_3WIRE_11N 0x88C52#define DM_REG_SC_CNT_11N 0x8C453#define DM_REG_PSD_DATA_11N 0x8B454/*PAGE 9*/55#define DM_REG_ANT_MAPPING1_11N 0x91456#define DM_REG_ANT_MAPPING2_11N 0x91857/*PAGE A*/58#define DM_REG_CCK_ANTDIV_PARA1_11N 0xA0059#define DM_REG_CCK_CCA_11N 0xA0A60#define DM_REG_CCK_ANTDIV_PARA2_11N 0xA0C61#define DM_REG_CCK_ANTDIV_PARA3_11N 0xA1062#define DM_REG_CCK_ANTDIV_PARA4_11N 0xA1463#define DM_REG_CCK_FILTER_PARA1_11N 0xA2264#define DM_REG_CCK_FILTER_PARA2_11N 0xA2365#define DM_REG_CCK_FILTER_PARA3_11N 0xA2466#define DM_REG_CCK_FILTER_PARA4_11N 0xA2567#define DM_REG_CCK_FILTER_PARA5_11N 0xA2668#define DM_REG_CCK_FILTER_PARA6_11N 0xA2769#define DM_REG_CCK_FILTER_PARA7_11N 0xA2870#define DM_REG_CCK_FILTER_PARA8_11N 0xA2971#define DM_REG_CCK_FA_RST_11N 0xA2C72#define DM_REG_CCK_FA_MSB_11N 0xA5873#define DM_REG_CCK_FA_LSB_11N 0xA5C74#define DM_REG_CCK_CCA_CNT_11N 0xA6075#define DM_REG_BB_PWR_SAV4_11N 0xA7476/*PAGE B */77#define DM_REG_LNA_SWITCH_11N 0xB2C78#define DM_REG_PATH_SWITCH_11N 0xB3079#define DM_REG_RSSI_CTRL_11N 0xB3880#define DM_REG_CONFIG_ANTA_11N 0xB6881#define DM_REG_RSSI_BT_11N 0xB9C82/*PAGE C */83#define DM_REG_OFDM_FA_HOLDC_11N 0xC0084#define DM_REG_RX_PATH_11N 0xC0485#define DM_REG_TRMUX_11N 0xC0886#define DM_REG_OFDM_FA_RSTC_11N 0xC0C87#define DM_REG_RXIQI_MATRIX_11N 0xC1488#define DM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C89#define DM_REG_IGI_A_11N 0xC5090#define DM_REG_ANTDIV_PARA2_11N 0xC5491#define DM_REG_IGI_B_11N 0xC5892#define DM_REG_ANTDIV_PARA3_11N 0xC5C93#define DM_REG_L1SBD_PD_CH_11N 0XC6C94#define DM_REG_BB_PWR_SAV2_11N 0xC7095#define DM_REG_RX_OFF_11N 0xC7C96#define DM_REG_TXIQK_MATRIXA_11N 0xC8097#define DM_REG_TXIQK_MATRIXB_11N 0xC8898#define DM_REG_TXIQK_MATRIXA_LSB2_11N 0xC9499#define DM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C100#define DM_REG_RXIQK_MATRIX_LSB_11N 0xCA0101#define DM_REG_ANTDIV_PARA1_11N 0xCA4102#define DM_REG_OFDM_FA_TYPE1_11N 0xCF0103/*PAGE D */104#define DM_REG_OFDM_FA_RSTD_11N 0xD00105#define DM_REG_OFDM_FA_TYPE2_11N 0xDA0106#define DM_REG_OFDM_FA_TYPE3_11N 0xDA4107#define DM_REG_OFDM_FA_TYPE4_11N 0xDA8108/*PAGE E */109#define DM_REG_TXAGC_A_6_18_11N 0xE00110#define DM_REG_TXAGC_A_24_54_11N 0xE04111#define DM_REG_TXAGC_A_1_MCS32_11N 0xE08112#define DM_REG_TXAGC_A_MCS0_3_11N 0xE10113#define DM_REG_TXAGC_A_MCS4_7_11N 0xE14114#define DM_REG_TXAGC_A_MCS8_11_11N 0xE18115#define DM_REG_TXAGC_A_MCS12_15_11N 0xE1C116#define DM_REG_FPGA0_IQK_11N 0xE28117#define DM_REG_TXIQK_TONE_A_11N 0xE30118#define DM_REG_RXIQK_TONE_A_11N 0xE34119#define DM_REG_TXIQK_PI_A_11N 0xE38120#define DM_REG_RXIQK_PI_A_11N 0xE3C121#define DM_REG_TXIQK_11N 0xE40122#define DM_REG_RXIQK_11N 0xE44123#define DM_REG_IQK_AGC_PTS_11N 0xE48124#define DM_REG_IQK_AGC_RSP_11N 0xE4C125#define DM_REG_BLUETOOTH_11N 0xE6C126#define DM_REG_RX_WAIT_CCA_11N 0xE70127#define DM_REG_TX_CCK_RFON_11N 0xE74128#define DM_REG_TX_CCK_BBON_11N 0xE78129#define DM_REG_OFDM_RFON_11N 0xE7C130#define DM_REG_OFDM_BBON_11N 0xE80131#define DM_REG_TX2RX_11N 0xE84132#define DM_REG_TX2TX_11N 0xE88133#define DM_REG_RX_CCK_11N 0xE8C134#define DM_REG_RX_OFDM_11N 0xED0135#define DM_REG_RX_WAIT_RIFS_11N 0xED4136#define DM_REG_RX2RX_11N 0xED8137#define DM_REG_STANDBY_11N 0xEDC138#define DM_REG_SLEEP_11N 0xEE0139#define DM_REG_PMPD_ANAEN_11N 0xEEC140 141/*MAC REG LIST*/142#define DM_REG_BB_RST_11N 0x02143#define DM_REG_ANTSEL_PIN_11N 0x4C144#define DM_REG_EARLY_MODE_11N 0x4D0145#define DM_REG_RSSI_MONITOR_11N 0x4FE146#define DM_REG_EDCA_VO_11N 0x500147#define DM_REG_EDCA_VI_11N 0x504148#define DM_REG_EDCA_BE_11N 0x508149#define DM_REG_EDCA_BK_11N 0x50C150#define DM_REG_TXPAUSE_11N 0x522151#define DM_REG_RESP_TX_11N 0x6D8152#define DM_REG_ANT_TRAIN_PARA1_11N 0x7b0153#define DM_REG_ANT_TRAIN_PARA2_11N 0x7b4154 155/*DIG Related*/156#define DM_BIT_IGI_11N 0x0000007F157 158#define HAL_DM_DIG_DISABLE BIT(0)159#define HAL_DM_HIPWR_DISABLE BIT(1)160 161#define OFDM_TABLE_LENGTH 43162#define CCK_TABLE_LENGTH 33163 164#define OFDM_TABLE_SIZE 43165#define CCK_TABLE_SIZE 33166 167#define BW_AUTO_SWITCH_HIGH_LOW 25168#define BW_AUTO_SWITCH_LOW_HIGH 30169 170#define DM_DIG_FA_UPPER 0x3e171#define DM_DIG_FA_LOWER 0x1e172#define DM_DIG_FA_TH0 0x200173#define DM_DIG_FA_TH1 0x300174#define DM_DIG_FA_TH2 0x400175 176#define RXPATHSELECTION_SS_TH_LOW 30177#define RXPATHSELECTION_DIFF_TH 18178 179#define DM_RATR_STA_INIT 0180#define DM_RATR_STA_HIGH 1181#define DM_RATR_STA_MIDDLE 2182#define DM_RATR_STA_LOW 3183 184#define CTS2SELF_THVAL 30185#define REGC38_TH 20186 187#define WAIOTTHVAL 25188 189#define TXHIGHPWRLEVEL_NORMAL 0190#define TXHIGHPWRLEVEL_LEVEL1 1191#define TXHIGHPWRLEVEL_LEVEL2 2192#define TXHIGHPWRLEVEL_BT1 3193#define TXHIGHPWRLEVEL_BT2 4194 195#define DM_TYPE_BYFW 0196#define DM_TYPE_BYDRIVER 1197 198#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74199#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67200#define TXPWRTRACK_MAX_IDX 6201 202/* Dynamic ATC switch */203#define ATC_STATUS_OFF 0x0 /* enable */204#define ATC_STATUS_ON 0x1 /* disable */205#define CFO_THRESHOLD_XTAL 10 /* kHz */206#define CFO_THRESHOLD_ATC 80 /* kHz */207 208/* RSSI Dump Message */209#define RA_RSSIDUMP 0xcb0210#define RB_RSSIDUMP 0xcb1211#define RS1_RXEVMDUMP 0xcb2212#define RS2_RXEVMDUMP 0xcb3213#define RA_RXSNRDUMP 0xcb4214#define RB_RXSNRDUMP 0xcb5215#define RA_CFOSHORTDUMP 0xcb6216#define RB_CFOSHORTDUMP 0xcb8217#define RA_CFOLONGDUMP 0xcba218#define RB_CFOLONGDUMP 0xcbc219 220void rtl92ee_dm_init(struct ieee80211_hw *hw);221void rtl92ee_dm_watchdog(struct ieee80211_hw *hw);222void rtl92ee_dm_write_cck_cca_thres(struct ieee80211_hw *hw,223 u8 cur_thres);224void rtl92ee_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi);225void rtl92ee_dm_init_edca_turbo(struct ieee80211_hw *hw);226void rtl92ee_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);227void rtl92ee_dm_dynamic_arfb_select(struct ieee80211_hw *hw,228 u8 rate, bool collision_state);229#endif230