2609 lines · c
1// SPDX-License-Identifier: GPL-2.02/* Copyright(c) 2009-2014 Realtek Corporation.*/3 4#include "../wifi.h"5#include "../efuse.h"6#include "../base.h"7#include "../regd.h"8#include "../cam.h"9#include "../ps.h"10#include "../pci.h"11#include "reg.h"12#include "def.h"13#include "phy.h"14#include "dm.h"15#include "fw.h"16#include "led.h"17#include "hw.h"18#include "../pwrseqcmd.h"19#include "pwrseq.h"20 21#define LLT_CONFIG 522 23static void _rtl92ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw,24 u8 set_bits, u8 clear_bits)25{26 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));27 struct rtl_priv *rtlpriv = rtl_priv(hw);28 29 rtlpci->reg_bcn_ctrl_val |= set_bits;30 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;31 32 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);33}34 35static void _rtl92ee_stop_tx_beacon(struct ieee80211_hw *hw)36{37 struct rtl_priv *rtlpriv = rtl_priv(hw);38 u8 tmp;39 40 tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);41 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp & (~BIT(6)));42 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);43 tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);44 tmp &= ~(BIT(0));45 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp);46}47 48static void _rtl92ee_resume_tx_beacon(struct ieee80211_hw *hw)49{50 struct rtl_priv *rtlpriv = rtl_priv(hw);51 u8 tmp;52 53 tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);54 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp | BIT(6));55 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);56 tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);57 tmp |= BIT(0);58 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp);59}60 61static void _rtl92ee_enable_bcn_sub_func(struct ieee80211_hw *hw)62{63 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(1));64}65 66static void _rtl92ee_disable_bcn_sub_func(struct ieee80211_hw *hw)67{68 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(1), 0);69}70 71static void _rtl92ee_set_fw_clock_on(struct ieee80211_hw *hw,72 u8 rpwm_val, bool b_need_turn_off_ckk)73{74 struct rtl_priv *rtlpriv = rtl_priv(hw);75 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));76 bool b_support_remote_wake_up;77 u32 count = 0, isr_regaddr, content;78 bool b_schedule_timer = b_need_turn_off_ckk;79 80 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,81 (u8 *)(&b_support_remote_wake_up));82 83 if (!rtlhal->fw_ready)84 return;85 if (!rtlpriv->psc.fw_current_inpsmode)86 return;87 88 while (1) {89 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);90 if (rtlhal->fw_clk_change_in_progress) {91 while (rtlhal->fw_clk_change_in_progress) {92 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);93 count++;94 udelay(100);95 if (count > 1000)96 return;97 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);98 }99 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);100 } else {101 rtlhal->fw_clk_change_in_progress = false;102 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);103 break;104 }105 }106 107 if (IS_IN_LOW_POWER_STATE_92E(rtlhal->fw_ps_state)) {108 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,109 (u8 *)(&rpwm_val));110 if (FW_PS_IS_ACK(rpwm_val)) {111 isr_regaddr = REG_HISR;112 content = rtl_read_dword(rtlpriv, isr_regaddr);113 while (!(content & IMR_CPWM) && (count < 500)) {114 udelay(50);115 count++;116 content = rtl_read_dword(rtlpriv, isr_regaddr);117 }118 119 if (content & IMR_CPWM) {120 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);121 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_92E;122 rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,123 "Receive CPWM INT!!! PSState = %X\n",124 rtlhal->fw_ps_state);125 }126 }127 128 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);129 rtlhal->fw_clk_change_in_progress = false;130 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);131 if (b_schedule_timer) {132 mod_timer(&rtlpriv->works.fw_clockoff_timer,133 jiffies + MSECS(10));134 }135 } else {136 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);137 rtlhal->fw_clk_change_in_progress = false;138 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);139 }140}141 142static void _rtl92ee_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val)143{144 struct rtl_priv *rtlpriv = rtl_priv(hw);145 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));146 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));147 struct rtl8192_tx_ring *ring;148 enum rf_pwrstate rtstate;149 bool b_schedule_timer = false;150 u8 queue;151 152 if (!rtlhal->fw_ready)153 return;154 if (!rtlpriv->psc.fw_current_inpsmode)155 return;156 if (!rtlhal->allow_sw_to_change_hwclc)157 return;158 159 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));160 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)161 return;162 163 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {164 ring = &rtlpci->tx_ring[queue];165 if (skb_queue_len(&ring->queue)) {166 b_schedule_timer = true;167 break;168 }169 }170 171 if (b_schedule_timer) {172 mod_timer(&rtlpriv->works.fw_clockoff_timer,173 jiffies + MSECS(10));174 return;175 }176 177 if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR) {178 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);179 if (!rtlhal->fw_clk_change_in_progress) {180 rtlhal->fw_clk_change_in_progress = true;181 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);182 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);183 rtl_write_word(rtlpriv, REG_HISR, 0x0100);184 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,185 (u8 *)(&rpwm_val));186 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);187 rtlhal->fw_clk_change_in_progress = false;188 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);189 } else {190 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);191 mod_timer(&rtlpriv->works.fw_clockoff_timer,192 jiffies + MSECS(10));193 }194 }195}196 197static void _rtl92ee_set_fw_ps_rf_on(struct ieee80211_hw *hw)198{199 u8 rpwm_val = 0;200 201 rpwm_val |= (FW_PS_STATE_RF_OFF_92E | FW_PS_ACK);202 _rtl92ee_set_fw_clock_on(hw, rpwm_val, true);203}204 205static void _rtl92ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw)206{207 u8 rpwm_val = 0;208 209 rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR;210 _rtl92ee_set_fw_clock_off(hw, rpwm_val);211}212 213void rtl92ee_fw_clk_off_timer_callback(unsigned long data)214{215 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;216 217 _rtl92ee_set_fw_ps_rf_off_low_power(hw);218}219 220static void _rtl92ee_fwlps_leave(struct ieee80211_hw *hw)221{222 struct rtl_priv *rtlpriv = rtl_priv(hw);223 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));224 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));225 bool fw_current_inps = false;226 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;227 228 if (ppsc->low_power_enable) {229 rpwm_val = (FW_PS_STATE_ALL_ON_92E | FW_PS_ACK);/* RF on */230 _rtl92ee_set_fw_clock_on(hw, rpwm_val, false);231 rtlhal->allow_sw_to_change_hwclc = false;232 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,233 (u8 *)(&fw_pwrmode));234 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,235 (u8 *)(&fw_current_inps));236 } else {237 rpwm_val = FW_PS_STATE_ALL_ON_92E; /* RF on */238 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,239 (u8 *)(&rpwm_val));240 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,241 (u8 *)(&fw_pwrmode));242 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,243 (u8 *)(&fw_current_inps));244 }245}246 247static void _rtl92ee_fwlps_enter(struct ieee80211_hw *hw)248{249 struct rtl_priv *rtlpriv = rtl_priv(hw);250 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));251 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));252 bool fw_current_inps = true;253 u8 rpwm_val;254 255 if (ppsc->low_power_enable) {256 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR; /* RF off */257 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,258 (u8 *)(&fw_current_inps));259 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,260 (u8 *)(&ppsc->fwctrl_psmode));261 rtlhal->allow_sw_to_change_hwclc = true;262 _rtl92ee_set_fw_clock_off(hw, rpwm_val);263 } else {264 rpwm_val = FW_PS_STATE_RF_OFF_92E; /* RF off */265 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,266 (u8 *)(&fw_current_inps));267 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,268 (u8 *)(&ppsc->fwctrl_psmode));269 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,270 (u8 *)(&rpwm_val));271 }272}273 274void rtl92ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)275{276 struct rtl_priv *rtlpriv = rtl_priv(hw);277 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));278 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));279 280 switch (variable) {281 case HW_VAR_RCR:282 *((u32 *)(val)) = rtlpci->receive_config;283 break;284 case HW_VAR_RF_STATE:285 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;286 break;287 case HW_VAR_FWLPS_RF_ON:{288 enum rf_pwrstate rfstate;289 u32 val_rcr;290 291 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,292 (u8 *)(&rfstate));293 if (rfstate == ERFOFF) {294 *((bool *)(val)) = true;295 } else {296 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);297 val_rcr &= 0x00070000;298 if (val_rcr)299 *((bool *)(val)) = false;300 else301 *((bool *)(val)) = true;302 }303 }304 break;305 case HW_VAR_FW_PSMODE_STATUS:306 *((bool *)(val)) = ppsc->fw_current_inpsmode;307 break;308 case HW_VAR_CORRECT_TSF:{309 u64 tsf;310 u32 *ptsf_low = (u32 *)&tsf;311 u32 *ptsf_high = ((u32 *)&tsf) + 1;312 313 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));314 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);315 316 *((u64 *)(val)) = tsf;317 }318 break;319 case HAL_DEF_WOWLAN:320 break;321 default:322 rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG,323 "switch case %#x not processed\n", variable);324 break;325 }326}327 328static void _rtl92ee_download_rsvd_page(struct ieee80211_hw *hw)329{330 struct rtl_priv *rtlpriv = rtl_priv(hw);331 u8 tmp_regcr, tmp_reg422;332 u8 bcnvalid_reg, txbc_reg;333 u8 count = 0, dlbcn_count = 0;334 bool b_recover = false;335 336 /*Set REG_CR bit 8. DMA beacon by SW.*/337 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);338 rtl_write_byte(rtlpriv, REG_CR + 1, tmp_regcr | BIT(0));339 340 /* Disable Hw protection for a time which revserd for Hw sending beacon.341 * Fix download reserved page packet fail342 * that access collision with the protection time.343 * 2010.05.11. Added by tynli.344 */345 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(3));346 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(4), 0);347 348 /* Set FWHW_TXQ_CTRL 0x422[6]=0 to349 * tell Hw the packet is not a real beacon frame.350 */351 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);352 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422 & (~BIT(6)));353 354 if (tmp_reg422 & BIT(6))355 b_recover = true;356 357 do {358 /* Clear beacon valid check bit */359 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_DWBCN0_CTRL + 2);360 rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 2,361 bcnvalid_reg | BIT(0));362 363 /* download rsvd page */364 rtl92ee_set_fw_rsvdpagepkt(hw, false);365 366 txbc_reg = rtl_read_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3);367 count = 0;368 while ((txbc_reg & BIT(4)) && count < 20) {369 count++;370 udelay(10);371 txbc_reg = rtl_read_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3);372 }373 rtl_write_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3,374 txbc_reg | BIT(4));375 376 /* check rsvd page download OK. */377 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_DWBCN0_CTRL + 2);378 count = 0;379 while (!(bcnvalid_reg & BIT(0)) && count < 20) {380 count++;381 udelay(50);382 bcnvalid_reg = rtl_read_byte(rtlpriv,383 REG_DWBCN0_CTRL + 2);384 }385 386 if (bcnvalid_reg & BIT(0))387 rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 2, BIT(0));388 389 dlbcn_count++;390 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);391 392 if (!(bcnvalid_reg & BIT(0)))393 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,394 "Download RSVD page failed!\n");395 396 /* Enable Bcn */397 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0);398 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(4));399 400 if (b_recover)401 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);402 403 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);404 rtl_write_byte(rtlpriv, REG_CR + 1, tmp_regcr & (~BIT(0)));405}406 407void rtl92ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)408{409 struct rtl_priv *rtlpriv = rtl_priv(hw);410 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));411 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));412 struct rtl_efuse *efuse = rtl_efuse(rtl_priv(hw));413 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));414 u8 idx;415 416 switch (variable) {417 case HW_VAR_ETHER_ADDR:418 for (idx = 0; idx < ETH_ALEN; idx++)419 rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]);420 break;421 case HW_VAR_BASIC_RATE:{422 u16 b_rate_cfg = ((u16 *)val)[0];423 424 b_rate_cfg = b_rate_cfg & 0x15f;425 b_rate_cfg |= 0x01;426 b_rate_cfg = (b_rate_cfg | 0xd) & (~BIT(1));427 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);428 rtl_write_byte(rtlpriv, REG_RRSR + 1, (b_rate_cfg >> 8) & 0xff);429 break; }430 case HW_VAR_BSSID:431 for (idx = 0; idx < ETH_ALEN; idx++)432 rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]);433 break;434 case HW_VAR_SIFS:435 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);436 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);437 438 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);439 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);440 441 if (!mac->ht_enable)442 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e);443 else444 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,445 *((u16 *)val));446 break;447 case HW_VAR_SLOT_TIME:{448 u8 e_aci;449 450 rtl_dbg(rtlpriv, COMP_MLME, DBG_TRACE,451 "HW_VAR_SLOT_TIME %x\n", val[0]);452 453 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);454 455 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {456 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,457 (u8 *)(&e_aci));458 }459 break; }460 case HW_VAR_ACK_PREAMBLE:{461 u8 reg_tmp;462 u8 short_preamble = (bool)(*(u8 *)val);463 464 reg_tmp = (rtlpriv->mac80211.cur_40_prime_sc) << 5;465 if (short_preamble)466 reg_tmp |= 0x80;467 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);468 rtlpriv->mac80211.short_preamble = short_preamble;469 }470 break;471 case HW_VAR_WPA_CONFIG:472 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));473 break;474 case HW_VAR_AMPDU_FACTOR:{475 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };476 u8 fac;477 u8 *reg = NULL;478 u8 i = 0;479 480 reg = regtoset_normal;481 482 fac = *((u8 *)val);483 if (fac <= 3) {484 fac = (1 << (fac + 2));485 if (fac > 0xf)486 fac = 0xf;487 for (i = 0; i < 4; i++) {488 if ((reg[i] & 0xf0) > (fac << 4))489 reg[i] = (reg[i] & 0x0f) |490 (fac << 4);491 if ((reg[i] & 0x0f) > fac)492 reg[i] = (reg[i] & 0xf0) | fac;493 rtl_write_byte(rtlpriv,494 (REG_AGGLEN_LMT + i),495 reg[i]);496 }497 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,498 "Set HW_VAR_AMPDU_FACTOR:%#x\n", fac);499 }500 }501 break;502 case HW_VAR_AC_PARAM:{503 u8 e_aci = *((u8 *)val);504 505 if (rtlpci->acm_method != EACMWAY2_SW)506 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,507 (u8 *)(&e_aci));508 }509 break;510 case HW_VAR_ACM_CTRL:{511 u8 e_aci = *((u8 *)val);512 union aci_aifsn *aifs = (union aci_aifsn *)(&mac->ac[0].aifs);513 514 u8 acm = aifs->f.acm;515 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);516 517 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);518 519 if (acm) {520 switch (e_aci) {521 case AC0_BE:522 acm_ctrl |= ACMHW_BEQEN;523 break;524 case AC2_VI:525 acm_ctrl |= ACMHW_VIQEN;526 break;527 case AC3_VO:528 acm_ctrl |= ACMHW_VOQEN;529 break;530 default:531 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,532 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",533 acm);534 break;535 }536 } else {537 switch (e_aci) {538 case AC0_BE:539 acm_ctrl &= (~ACMHW_BEQEN);540 break;541 case AC2_VI:542 acm_ctrl &= (~ACMHW_VIQEN);543 break;544 case AC3_VO:545 acm_ctrl &= (~ACMHW_VOQEN);546 break;547 default:548 rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG,549 "switch case %#x not processed\n",550 e_aci);551 break;552 }553 }554 555 rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE,556 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",557 acm_ctrl);558 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);559 }560 break;561 case HW_VAR_RCR:{562 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);563 rtlpci->receive_config = ((u32 *)(val))[0];564 }565 break;566 case HW_VAR_RETRY_LIMIT:{567 u8 retry_limit = ((u8 *)(val))[0];568 569 rtl_write_word(rtlpriv, REG_RETRY_LIMIT,570 retry_limit << RETRY_LIMIT_SHORT_SHIFT |571 retry_limit << RETRY_LIMIT_LONG_SHIFT);572 }573 break;574 case HW_VAR_DUAL_TSF_RST:575 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));576 break;577 case HW_VAR_EFUSE_BYTES:578 efuse->efuse_usedbytes = *((u16 *)val);579 break;580 case HW_VAR_EFUSE_USAGE:581 efuse->efuse_usedpercentage = *((u8 *)val);582 break;583 case HW_VAR_IO_CMD:584 rtl92ee_phy_set_io_cmd(hw, (*(enum io_type *)val));585 break;586 case HW_VAR_SET_RPWM:{587 u8 rpwm_val;588 589 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);590 udelay(1);591 592 if (rpwm_val & BIT(7)) {593 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, (*(u8 *)val));594 } else {595 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,596 ((*(u8 *)val) | BIT(7)));597 }598 }599 break;600 case HW_VAR_H2C_FW_PWRMODE:601 rtl92ee_set_fw_pwrmode_cmd(hw, (*(u8 *)val));602 break;603 case HW_VAR_FW_PSMODE_STATUS:604 ppsc->fw_current_inpsmode = *((bool *)val);605 break;606 case HW_VAR_RESUME_CLK_ON:607 _rtl92ee_set_fw_ps_rf_on(hw);608 break;609 case HW_VAR_FW_LPS_ACTION:{610 bool b_enter_fwlps = *((bool *)val);611 612 if (b_enter_fwlps)613 _rtl92ee_fwlps_enter(hw);614 else615 _rtl92ee_fwlps_leave(hw);616 }617 break;618 case HW_VAR_H2C_FW_JOINBSSRPT:{619 u8 mstatus = (*(u8 *)val);620 621 if (mstatus == RT_MEDIA_CONNECT) {622 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);623 _rtl92ee_download_rsvd_page(hw);624 }625 rtl92ee_set_fw_media_status_rpt_cmd(hw, mstatus);626 }627 break;628 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:629 rtl92ee_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));630 break;631 case HW_VAR_AID:{632 u16 u2btmp;633 634 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);635 u2btmp &= 0xC000;636 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,637 (u2btmp | mac->assoc_id));638 }639 break;640 case HW_VAR_CORRECT_TSF:{641 u8 btype_ibss = ((u8 *)(val))[0];642 643 if (btype_ibss)644 _rtl92ee_stop_tx_beacon(hw);645 646 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(3));647 648 rtl_write_dword(rtlpriv, REG_TSFTR,649 (u32)(mac->tsf & 0xffffffff));650 rtl_write_dword(rtlpriv, REG_TSFTR + 4,651 (u32)((mac->tsf >> 32) & 0xffffffff));652 653 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0);654 655 if (btype_ibss)656 _rtl92ee_resume_tx_beacon(hw);657 }658 break;659 case HW_VAR_KEEP_ALIVE: {660 u8 array[2];661 662 array[0] = 0xff;663 array[1] = *((u8 *)val);664 rtl92ee_fill_h2c_cmd(hw, H2C_92E_KEEP_ALIVE_CTRL, 2, array);665 }666 break;667 default:668 rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG,669 "switch case %#x not processed\n", variable);670 break;671 }672}673 674static bool _rtl92ee_llt_table_init(struct ieee80211_hw *hw)675{676 struct rtl_priv *rtlpriv = rtl_priv(hw);677 u8 txpktbuf_bndy;678 u8 u8tmp, testcnt = 0;679 680 txpktbuf_bndy = 0xF7;681 682 rtl_write_dword(rtlpriv, REG_RQPN, 0x80E60808);683 684 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);685 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x3d00 - 1);686 687 rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 1, txpktbuf_bndy);688 rtl_write_byte(rtlpriv, REG_DWBCN1_CTRL + 1, txpktbuf_bndy);689 690 rtl_write_byte(rtlpriv, REG_BCNQ_BDNY, txpktbuf_bndy);691 rtl_write_byte(rtlpriv, REG_BCNQ1_BDNY, txpktbuf_bndy);692 693 rtl_write_byte(rtlpriv, REG_MGQ_BDNY, txpktbuf_bndy);694 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);695 696 rtl_write_byte(rtlpriv, REG_PBP, 0x31);697 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);698 699 u8tmp = rtl_read_byte(rtlpriv, REG_AUTO_LLT + 2);700 rtl_write_byte(rtlpriv, REG_AUTO_LLT + 2, u8tmp | BIT(0));701 702 while (u8tmp & BIT(0)) {703 u8tmp = rtl_read_byte(rtlpriv, REG_AUTO_LLT + 2);704 udelay(10);705 testcnt++;706 if (testcnt > 10)707 break;708 }709 710 return true;711}712 713static void _rtl92ee_gen_refresh_led_state(struct ieee80211_hw *hw)714{715 struct rtl_priv *rtlpriv = rtl_priv(hw);716 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));717 enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;718 719 if (rtlpriv->rtlhal.up_first_time)720 return;721 722 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)723 rtl92ee_sw_led_on(hw, pin0);724 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)725 rtl92ee_sw_led_on(hw, pin0);726 else727 rtl92ee_sw_led_off(hw, pin0);728}729 730static bool _rtl92ee_init_mac(struct ieee80211_hw *hw)731{732 struct rtl_priv *rtlpriv = rtl_priv(hw);733 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));734 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));735 736 u8 bytetmp;737 u16 wordtmp;738 u32 dwordtmp;739 740 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);741 742 dwordtmp = rtl_read_dword(rtlpriv, REG_SYS_CFG1);743 if (dwordtmp & BIT(24)) {744 rtl_write_byte(rtlpriv, 0x7c, 0xc3);745 } else {746 bytetmp = rtl_read_byte(rtlpriv, 0x16);747 rtl_write_byte(rtlpriv, 0x16, bytetmp | BIT(4) | BIT(6));748 rtl_write_byte(rtlpriv, 0x7c, 0x83);749 }750 /* 1. 40Mhz crystal source*/751 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_CTRL2);752 bytetmp &= 0xfb;753 rtl_write_byte(rtlpriv, REG_AFE_CTRL2, bytetmp);754 755 dwordtmp = rtl_read_dword(rtlpriv, REG_AFE_CTRL4);756 dwordtmp &= 0xfffffc7f;757 rtl_write_dword(rtlpriv, REG_AFE_CTRL4, dwordtmp);758 759 /* 2. 92E AFE parameter760 * MP chip then check version761 */762 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_CTRL2);763 bytetmp &= 0xbf;764 rtl_write_byte(rtlpriv, REG_AFE_CTRL2, bytetmp);765 766 dwordtmp = rtl_read_dword(rtlpriv, REG_AFE_CTRL4);767 dwordtmp &= 0xffdfffff;768 rtl_write_dword(rtlpriv, REG_AFE_CTRL4, dwordtmp);769 770 /* HW Power on sequence */771 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,772 PWR_INTF_PCI_MSK,773 RTL8192E_NIC_ENABLE_FLOW)) {774 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,775 "init MAC Fail as rtl_hal_pwrseqcmdparsing\n");776 return false;777 }778 779 /* Release MAC IO register reset */780 bytetmp = rtl_read_byte(rtlpriv, REG_CR);781 bytetmp = 0xff;782 rtl_write_byte(rtlpriv, REG_CR, bytetmp);783 mdelay(2);784 bytetmp = 0x7f;785 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);786 mdelay(2);787 788 /* Add for wakeup online */789 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);790 rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp | BIT(3));791 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);792 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp & (~BIT(4)));793 /* Release MAC IO register reset */794 rtl_write_word(rtlpriv, REG_CR, 0x2ff);795 796 if (!rtlhal->mac_func_enable) {797 if (!_rtl92ee_llt_table_init(hw)) {798 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,799 "LLT table init fail\n");800 return false;801 }802 }803 804 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);805 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);806 807 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);808 wordtmp &= 0xf;809 wordtmp |= 0xF5B1;810 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);811 /* Reported Tx status from HW for rate adaptive.*/812 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);813 814 /* Set RCR register */815 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);816 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff);817 818 /* Set TCR register */819 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);820 821 /* Set TX/RX descriptor physical address -- HI part */822 if (!rtlpriv->cfg->mod_params->dma64)823 goto dma64_end;824 825 rtl_write_dword(rtlpriv, REG_BCNQ_DESA + 4,826 ((u64)rtlpci->tx_ring[BEACON_QUEUE].buffer_desc_dma) >>827 32);828 rtl_write_dword(rtlpriv, REG_MGQ_DESA + 4,829 (u64)rtlpci->tx_ring[MGNT_QUEUE].buffer_desc_dma >> 32);830 rtl_write_dword(rtlpriv, REG_VOQ_DESA + 4,831 (u64)rtlpci->tx_ring[VO_QUEUE].buffer_desc_dma >> 32);832 rtl_write_dword(rtlpriv, REG_VIQ_DESA + 4,833 (u64)rtlpci->tx_ring[VI_QUEUE].buffer_desc_dma >> 32);834 rtl_write_dword(rtlpriv, REG_BEQ_DESA + 4,835 (u64)rtlpci->tx_ring[BE_QUEUE].buffer_desc_dma >> 32);836 rtl_write_dword(rtlpriv, REG_BKQ_DESA + 4,837 (u64)rtlpci->tx_ring[BK_QUEUE].buffer_desc_dma >> 32);838 rtl_write_dword(rtlpriv, REG_HQ0_DESA + 4,839 (u64)rtlpci->tx_ring[HIGH_QUEUE].buffer_desc_dma >> 32);840 841 rtl_write_dword(rtlpriv, REG_RX_DESA + 4,842 (u64)rtlpci->rx_ring[RX_MPDU_QUEUE].dma >> 32);843 844dma64_end:845 846 /* Set TX/RX descriptor physical address(from OS API). */847 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,848 ((u64)rtlpci->tx_ring[BEACON_QUEUE].buffer_desc_dma) &849 DMA_BIT_MASK(32));850 rtl_write_dword(rtlpriv, REG_MGQ_DESA,851 (u64)rtlpci->tx_ring[MGNT_QUEUE].buffer_desc_dma &852 DMA_BIT_MASK(32));853 rtl_write_dword(rtlpriv, REG_VOQ_DESA,854 (u64)rtlpci->tx_ring[VO_QUEUE].buffer_desc_dma &855 DMA_BIT_MASK(32));856 rtl_write_dword(rtlpriv, REG_VIQ_DESA,857 (u64)rtlpci->tx_ring[VI_QUEUE].buffer_desc_dma &858 DMA_BIT_MASK(32));859 860 rtl_write_dword(rtlpriv, REG_BEQ_DESA,861 (u64)rtlpci->tx_ring[BE_QUEUE].buffer_desc_dma &862 DMA_BIT_MASK(32));863 864 dwordtmp = rtl_read_dword(rtlpriv, REG_BEQ_DESA);865 866 rtl_write_dword(rtlpriv, REG_BKQ_DESA,867 (u64)rtlpci->tx_ring[BK_QUEUE].buffer_desc_dma &868 DMA_BIT_MASK(32));869 rtl_write_dword(rtlpriv, REG_HQ0_DESA,870 (u64)rtlpci->tx_ring[HIGH_QUEUE].buffer_desc_dma &871 DMA_BIT_MASK(32));872 873 rtl_write_dword(rtlpriv, REG_RX_DESA,874 (u64)rtlpci->rx_ring[RX_MPDU_QUEUE].dma &875 DMA_BIT_MASK(32));876 877 /* if we want to support 64 bit DMA, we should set it here,878 * but now we do not support 64 bit DMA879 */880 881 rtl_write_dword(rtlpriv, REG_TSFTIMER_HCI, 0x3fffffff);882 883 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 3);884 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, bytetmp | 0xF7);885 886 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);887 888 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);889 890 rtl_write_word(rtlpriv, REG_MGQ_TXBD_NUM,891 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));892 rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM,893 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));894 rtl_write_word(rtlpriv, REG_VIQ_TXBD_NUM,895 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));896 rtl_write_word(rtlpriv, REG_BEQ_TXBD_NUM,897 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));898 rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM,899 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));900 rtl_write_word(rtlpriv, REG_BKQ_TXBD_NUM,901 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));902 rtl_write_word(rtlpriv, REG_HI0Q_TXBD_NUM,903 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));904 rtl_write_word(rtlpriv, REG_HI1Q_TXBD_NUM,905 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));906 rtl_write_word(rtlpriv, REG_HI2Q_TXBD_NUM,907 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));908 rtl_write_word(rtlpriv, REG_HI3Q_TXBD_NUM,909 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));910 rtl_write_word(rtlpriv, REG_HI4Q_TXBD_NUM,911 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));912 rtl_write_word(rtlpriv, REG_HI5Q_TXBD_NUM,913 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));914 rtl_write_word(rtlpriv, REG_HI6Q_TXBD_NUM,915 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));916 rtl_write_word(rtlpriv, REG_HI7Q_TXBD_NUM,917 TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));918 /*Rx*/919 rtl_write_word(rtlpriv, REG_RX_RXBD_NUM,920 RX_DESC_NUM_92E |921 ((RTL8192EE_SEG_NUM << 13) & 0x6000) | 0x8000);922 923 rtl_write_dword(rtlpriv, REG_TSFTIMER_HCI, 0XFFFFFFFF);924 925 _rtl92ee_gen_refresh_led_state(hw);926 return true;927}928 929static void _rtl92ee_hw_configure(struct ieee80211_hw *hw)930{931 struct rtl_priv *rtlpriv = rtl_priv(hw);932 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));933 u32 reg_rrsr;934 935 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;936 /* Init value for RRSR. */937 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);938 939 /* ARFB table 9 for 11ac 5G 2SS */940 rtl_write_dword(rtlpriv, REG_ARFR0, 0x00000010);941 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0x3e0ff000);942 943 /* ARFB table 10 for 11ac 5G 1SS */944 rtl_write_dword(rtlpriv, REG_ARFR1, 0x00000010);945 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x000ff000);946 947 /* Set SLOT time */948 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);949 950 /* CF-End setting. */951 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);952 953 /* Set retry limit */954 rtl_write_word(rtlpriv, REG_RETRY_LIMIT, 0x0707);955 956 /* BAR settings */957 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x0201ffff);958 959 /* Set Data / Response auto rate fallack retry count */960 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);961 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);962 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);963 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);964 965 /* Beacon related, for rate adaptive */966 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);967 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);968 969 rtlpci->reg_bcn_ctrl_val = 0x1d;970 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);971 972 /* Marked out by Bruce, 2010-09-09.973 * This register is configured for the 2nd Beacon (multiple BSSID).974 * We shall disable this register if we only support 1 BSSID.975 * vivi guess 92d also need this, also 92d now doesnot set this reg976 */977 rtl_write_byte(rtlpriv, REG_BCN_CTRL_1, 0);978 979 /* TBTT prohibit hold time. Suggested by designer TimChen. */980 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); /* 8 ms */981 982 rtl_write_byte(rtlpriv, REG_PIFS, 0);983 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);984 985 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);986 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x08ff);987 988 /* For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/989 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);990 991 /* ACKTO for IOT issue. */992 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);993 994 /* Set Spec SIFS (used in NAV) */995 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x100a);996 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x100a);997 998 /* Set SIFS for CCK */999 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x100a);1000 1001 /* Set SIFS for OFDM */1002 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x100a);1003 1004 /* Note Data sheet don't define */1005 rtl_write_byte(rtlpriv, 0x4C7, 0x80);1006 1007 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);1008 1009 rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1717);1010 1011 /* Set Multicast Address. 2009.01.07. by tynli. */1012 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);1013 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);1014}1015 1016static void _rtl92ee_enable_aspm_back_door(struct ieee80211_hw *hw)1017{1018 struct rtl_priv *rtlpriv = rtl_priv(hw);1019 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));1020 u32 tmp32 = 0, count = 0;1021 u8 tmp8 = 0;1022 1023 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x78);1024 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2);1025 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);1026 count = 0;1027 while (tmp8 && count < 20) {1028 udelay(10);1029 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);1030 count++;1031 }1032 1033 if (0 == tmp8) {1034 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA);1035 if ((tmp32 & 0xff00) != 0x2000) {1036 tmp32 &= 0xffff00ff;1037 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA,1038 tmp32 | BIT(13));1039 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf078);1040 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1);1041 1042 tmp8 = rtl_read_byte(rtlpriv,1043 REG_BACKDOOR_DBI_DATA + 2);1044 count = 0;1045 while (tmp8 && count < 20) {1046 udelay(10);1047 tmp8 = rtl_read_byte(rtlpriv,1048 REG_BACKDOOR_DBI_DATA + 2);1049 count++;1050 }1051 }1052 }1053 1054 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x70c);1055 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2);1056 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);1057 count = 0;1058 while (tmp8 && count < 20) {1059 udelay(10);1060 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);1061 count++;1062 }1063 if (0 == tmp8) {1064 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA);1065 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA,1066 tmp32 | BIT(31));1067 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf70c);1068 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1);1069 }1070 1071 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);1072 count = 0;1073 while (tmp8 && count < 20) {1074 udelay(10);1075 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);1076 count++;1077 }1078 1079 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x718);1080 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2);1081 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);1082 count = 0;1083 while (tmp8 && count < 20) {1084 udelay(10);1085 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);1086 count++;1087 }1088 if (ppsc->support_backdoor || (0 == tmp8)) {1089 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA);1090 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA,1091 tmp32 | BIT(11) | BIT(12));1092 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf718);1093 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1);1094 }1095 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);1096 count = 0;1097 while (tmp8 && count < 20) {1098 udelay(10);1099 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);1100 count++;1101 }1102}1103 1104void rtl92ee_enable_hw_security_config(struct ieee80211_hw *hw)1105{1106 struct rtl_priv *rtlpriv = rtl_priv(hw);1107 u8 sec_reg_value;1108 u8 tmp;1109 1110 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,1111 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",1112 rtlpriv->sec.pairwise_enc_algorithm,1113 rtlpriv->sec.group_enc_algorithm);1114 1115 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {1116 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,1117 "not open hw encryption\n");1118 return;1119 }1120 1121 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;1122 1123 if (rtlpriv->sec.use_defaultkey) {1124 sec_reg_value |= SCR_TXUSEDK;1125 sec_reg_value |= SCR_RXUSEDK;1126 }1127 1128 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);1129 1130 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);1131 rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));1132 1133 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,1134 "The SECR-value %x\n", sec_reg_value);1135 1136 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);1137}1138 1139static bool _rtl8192ee_check_pcie_dma_hang(struct rtl_priv *rtlpriv)1140{1141 u8 tmp;1142 1143 /* write reg 0x350 Bit[26]=1. Enable debug port. */1144 tmp = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 3);1145 if (!(tmp & BIT(2))) {1146 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 3,1147 tmp | BIT(2));1148 mdelay(100); /* Suggested by DD Justin_tsai. */1149 }1150 1151 /* read reg 0x350 Bit[25] if 1 : RX hang1152 * read reg 0x350 Bit[24] if 1 : TX hang1153 */1154 tmp = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 3);1155 if ((tmp & BIT(0)) || (tmp & BIT(1))) {1156 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,1157 "CheckPcieDMAHang8192EE(): true!!\n");1158 return true;1159 }1160 return false;1161}1162 1163static void _rtl8192ee_reset_pcie_interface_dma(struct rtl_priv *rtlpriv,1164 bool mac_power_on)1165{1166 u8 tmp;1167 bool release_mac_rx_pause;1168 u8 backup_pcie_dma_pause;1169 1170 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,1171 "ResetPcieInterfaceDMA8192EE()\n");1172 1173 /* Revise Note: Follow the document "PCIe RX DMA Hang Reset Flow_v03"1174 * released by SD1 Alan.1175 */1176 1177 /* 1. disable register write lock1178 * write 0x1C bit[1:0] = 2'h01179 * write 0xCC bit[2] = 1'b11180 */1181 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);1182 tmp &= ~(BIT(1) | BIT(0));1183 rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);1184 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);1185 tmp |= BIT(2);1186 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);1187 1188 /* 2. Check and pause TRX DMA1189 * write 0x284 bit[18] = 1'b11190 * write 0x301 = 0xFF1191 */1192 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);1193 if (tmp & BIT(2)) {1194 /* Already pause before the function for another reason. */1195 release_mac_rx_pause = false;1196 } else {1197 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));1198 release_mac_rx_pause = true;1199 }1200 1201 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);1202 if (backup_pcie_dma_pause != 0xFF)1203 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);1204 1205 if (mac_power_on) {1206 /* 3. reset TRX function1207 * write 0x100 = 0x001208 */1209 rtl_write_byte(rtlpriv, REG_CR, 0);1210 }1211 1212 /* 4. Reset PCIe DMA1213 * write 0x003 bit[0] = 01214 */1215 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);1216 tmp &= ~(BIT(0));1217 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);1218 1219 /* 5. Enable PCIe DMA1220 * write 0x003 bit[0] = 11221 */1222 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);1223 tmp |= BIT(0);1224 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);1225 1226 if (mac_power_on) {1227 /* 6. enable TRX function1228 * write 0x100 = 0xFF1229 */1230 rtl_write_byte(rtlpriv, REG_CR, 0xFF);1231 1232 /* We should init LLT & RQPN and1233 * prepare Tx/Rx descrptor address later1234 * because MAC function is reset.1235 */1236 }1237 1238 /* 7. Restore PCIe autoload down bit1239 * write 0xF8 bit[17] = 1'b11240 */1241 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);1242 tmp |= BIT(1);1243 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);1244 1245 /* In MAC power on state, BB and RF maybe in ON state,1246 * if we release TRx DMA here1247 * it will cause packets to be started to Tx/Rx,1248 * so we release Tx/Rx DMA later.1249 */1250 if (!mac_power_on) {1251 /* 8. release TRX DMA1252 * write 0x284 bit[18] = 1'b01253 * write 0x301 = 0x001254 */1255 if (release_mac_rx_pause) {1256 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);1257 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,1258 (tmp & (~BIT(2))));1259 }1260 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,1261 backup_pcie_dma_pause);1262 }1263 1264 /* 9. lock system register1265 * write 0xCC bit[2] = 1'b01266 */1267 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);1268 tmp &= ~(BIT(2));1269 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);1270}1271 1272int rtl92ee_hw_init(struct ieee80211_hw *hw)1273{1274 struct rtl_priv *rtlpriv = rtl_priv(hw);1275 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));1276 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));1277 struct rtl_phy *rtlphy = &rtlpriv->phy;1278 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));1279 bool rtstatus = true;1280 int err = 0;1281 u8 tmp_u1b, u1byte;1282 u32 tmp_u4b;1283 1284 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, " Rtl8192EE hw init\n");1285 rtlpriv->rtlhal.being_init_adapter = true;1286 rtlpriv->intf_ops->disable_aspm(hw);1287 1288 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1);1289 u1byte = rtl_read_byte(rtlpriv, REG_CR);1290 if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) {1291 rtlhal->mac_func_enable = true;1292 } else {1293 rtlhal->mac_func_enable = false;1294 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_92E;1295 }1296 1297 if (_rtl8192ee_check_pcie_dma_hang(rtlpriv)) {1298 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "92ee dma hang!\n");1299 _rtl8192ee_reset_pcie_interface_dma(rtlpriv,1300 rtlhal->mac_func_enable);1301 rtlhal->mac_func_enable = false;1302 }1303 1304 rtstatus = _rtl92ee_init_mac(hw);1305 1306 rtl_write_byte(rtlpriv, 0x577, 0x03);1307 1308 /*for Crystal 40 Mhz setting */1309 rtl_write_byte(rtlpriv, REG_AFE_CTRL4, 0x2A);1310 rtl_write_byte(rtlpriv, REG_AFE_CTRL4 + 1, 0x00);1311 rtl_write_byte(rtlpriv, REG_AFE_CTRL2, 0x83);1312 1313 /*Forced the antenna b to wifi */1314 if (rtlpriv->btcoexist.btc_info.btcoexist == 1) {1315 rtl_write_byte(rtlpriv, 0x64, 0);1316 rtl_write_byte(rtlpriv, 0x65, 1);1317 }1318 if (!rtstatus) {1319 pr_err("Init MAC failed\n");1320 err = 1;1321 return err;1322 }1323 rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, 0x8000);1324 err = rtl92ee_download_fw(hw, false);1325 if (err) {1326 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,1327 "Failed to download FW. Init HW without FW now..\n");1328 err = 1;1329 rtlhal->fw_ready = false;1330 return err;1331 }1332 rtlhal->fw_ready = true;1333 /*fw related variable initialize */1334 ppsc->fw_current_inpsmode = false;1335 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_92E;1336 rtlhal->fw_clk_change_in_progress = false;1337 rtlhal->allow_sw_to_change_hwclc = false;1338 rtlhal->last_hmeboxnum = 0;1339 1340 rtl92ee_phy_mac_config(hw);1341 1342 rtl92ee_phy_bb_config(hw);1343 1344 rtl92ee_phy_rf_config(hw);1345 1346 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, RF90_PATH_A,1347 RF_CHNLBW, RFREG_OFFSET_MASK);1348 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, RF90_PATH_B,1349 RF_CHNLBW, RFREG_OFFSET_MASK);1350 rtlphy->backup_rf_0x1a = (u32)rtl_get_rfreg(hw, RF90_PATH_A, RF_RX_G1,1351 RFREG_OFFSET_MASK);1352 rtlphy->rfreg_chnlval[0] = (rtlphy->rfreg_chnlval[0] & 0xfffff3ff) |1353 BIT(10) | BIT(11);1354 1355 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,1356 rtlphy->rfreg_chnlval[0]);1357 rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK,1358 rtlphy->rfreg_chnlval[0]);1359 1360 /*---- Set CCK and OFDM Block "ON"----*/1361 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);1362 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);1363 1364 /* Must set this,1365 * otherwise the rx sensitivity will be very pool. Maddest1366 */1367 rtl_set_rfreg(hw, RF90_PATH_A, 0xB1, RFREG_OFFSET_MASK, 0x54418);1368 1369 /*Set Hardware(MAC default setting.)*/1370 _rtl92ee_hw_configure(hw);1371 1372 rtlhal->mac_func_enable = true;1373 1374 rtl_cam_reset_all_entry(hw);1375 rtl92ee_enable_hw_security_config(hw);1376 1377 ppsc->rfpwr_state = ERFON;1378 1379 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);1380 _rtl92ee_enable_aspm_back_door(hw);1381 rtlpriv->intf_ops->enable_aspm(hw);1382 1383 rtl92ee_bt_hw_init(hw);1384 1385 rtlpriv->rtlhal.being_init_adapter = false;1386 1387 if (ppsc->rfpwr_state == ERFON) {1388 if (rtlphy->iqk_initialized) {1389 rtl92ee_phy_iq_calibrate(hw, true);1390 } else {1391 rtl92ee_phy_iq_calibrate(hw, false);1392 rtlphy->iqk_initialized = true;1393 }1394 }1395 1396 rtlphy->rfpath_rx_enable[0] = true;1397 if (rtlphy->rf_type == RF_2T2R)1398 rtlphy->rfpath_rx_enable[1] = true;1399 1400 efuse_one_byte_read(hw, 0x1FA, &tmp_u1b);1401 if (!(tmp_u1b & BIT(0))) {1402 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);1403 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n");1404 }1405 1406 if ((!(tmp_u1b & BIT(1))) && (rtlphy->rf_type == RF_2T2R)) {1407 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);1408 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path B\n");1409 }1410 1411 rtl_write_byte(rtlpriv, REG_NAV_UPPER, ((30000 + 127) / 128));1412 1413 /*Fixed LDPC rx hang issue. */1414 tmp_u4b = rtl_read_dword(rtlpriv, REG_SYS_SWR_CTRL1);1415 rtl_write_byte(rtlpriv, REG_SYS_SWR_CTRL2, 0x75);1416 tmp_u4b = (tmp_u4b & 0xfff00fff) | (0x7E << 12);1417 rtl_write_dword(rtlpriv, REG_SYS_SWR_CTRL1, tmp_u4b);1418 1419 rtl92ee_dm_init(hw);1420 1421 rtl_write_dword(rtlpriv, 0x4fc, 0);1422 1423 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,1424 "end of Rtl8192EE hw init %x\n", err);1425 return 0;1426}1427 1428static enum version_8192e _rtl92ee_read_chip_version(struct ieee80211_hw *hw)1429{1430 struct rtl_priv *rtlpriv = rtl_priv(hw);1431 struct rtl_phy *rtlphy = &rtlpriv->phy;1432 enum version_8192e version;1433 u32 value32;1434 1435 rtlphy->rf_type = RF_2T2R;1436 1437 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1);1438 if (value32 & TRP_VAUX_EN)1439 version = (enum version_8192e)VERSION_TEST_CHIP_2T2R_8192E;1440 else1441 version = (enum version_8192e)VERSION_NORMAL_CHIP_2T2R_8192E;1442 1443 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,1444 "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?1445 "RF_2T2R" : "RF_1T1R");1446 1447 return version;1448}1449 1450static int _rtl92ee_set_media_status(struct ieee80211_hw *hw,1451 enum nl80211_iftype type)1452{1453 struct rtl_priv *rtlpriv = rtl_priv(hw);1454 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;1455 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;1456 u8 mode = MSR_NOLINK;1457 1458 switch (type) {1459 case NL80211_IFTYPE_UNSPECIFIED:1460 mode = MSR_NOLINK;1461 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,1462 "Set Network type to NO LINK!\n");1463 break;1464 case NL80211_IFTYPE_ADHOC:1465 case NL80211_IFTYPE_MESH_POINT:1466 mode = MSR_ADHOC;1467 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,1468 "Set Network type to Ad Hoc!\n");1469 break;1470 case NL80211_IFTYPE_STATION:1471 mode = MSR_INFRA;1472 ledaction = LED_CTL_LINK;1473 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,1474 "Set Network type to STA!\n");1475 break;1476 case NL80211_IFTYPE_AP:1477 mode = MSR_AP;1478 ledaction = LED_CTL_LINK;1479 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,1480 "Set Network type to AP!\n");1481 break;1482 default:1483 pr_err("Network type %d not support!\n", type);1484 return 1;1485 }1486 1487 /* MSR_INFRA == Link in infrastructure network;1488 * MSR_ADHOC == Link in ad hoc network;1489 * Therefore, check link state is necessary.1490 *1491 * MSR_AP == AP mode; link state is not cared here.1492 */1493 if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {1494 mode = MSR_NOLINK;1495 ledaction = LED_CTL_NO_LINK;1496 }1497 1498 if (mode == MSR_NOLINK || mode == MSR_INFRA) {1499 _rtl92ee_stop_tx_beacon(hw);1500 _rtl92ee_enable_bcn_sub_func(hw);1501 } else if (mode == MSR_ADHOC || mode == MSR_AP) {1502 _rtl92ee_resume_tx_beacon(hw);1503 _rtl92ee_disable_bcn_sub_func(hw);1504 } else {1505 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,1506 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",1507 mode);1508 }1509 1510 rtl_write_byte(rtlpriv, MSR, bt_msr | mode);1511 rtlpriv->cfg->ops->led_control(hw, ledaction);1512 if (mode == MSR_AP)1513 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);1514 else1515 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);1516 return 0;1517}1518 1519void rtl92ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)1520{1521 struct rtl_priv *rtlpriv = rtl_priv(hw);1522 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));1523 u32 reg_rcr = rtlpci->receive_config;1524 1525 if (rtlpriv->psc.rfpwr_state != ERFON)1526 return;1527 1528 if (check_bssid) {1529 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);1530 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,1531 (u8 *)(®_rcr));1532 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(4));1533 } else {1534 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));1535 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(4), 0);1536 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,1537 (u8 *)(®_rcr));1538 }1539}1540 1541int rtl92ee_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)1542{1543 struct rtl_priv *rtlpriv = rtl_priv(hw);1544 1545 if (_rtl92ee_set_media_status(hw, type))1546 return -EOPNOTSUPP;1547 1548 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {1549 if (type != NL80211_IFTYPE_AP &&1550 type != NL80211_IFTYPE_MESH_POINT)1551 rtl92ee_set_check_bssid(hw, true);1552 } else {1553 rtl92ee_set_check_bssid(hw, false);1554 }1555 1556 return 0;1557}1558 1559/* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */1560void rtl92ee_set_qos(struct ieee80211_hw *hw, int aci)1561{1562 struct rtl_priv *rtlpriv = rtl_priv(hw);1563 1564 rtl92ee_dm_init_edca_turbo(hw);1565 switch (aci) {1566 case AC1_BK:1567 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);1568 break;1569 case AC0_BE:1570 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */1571 break;1572 case AC2_VI:1573 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);1574 break;1575 case AC3_VO:1576 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);1577 break;1578 default:1579 WARN_ONCE(true, "rtl8192ee: invalid aci: %d !\n", aci);1580 break;1581 }1582}1583 1584void rtl92ee_enable_interrupt(struct ieee80211_hw *hw)1585{1586 struct rtl_priv *rtlpriv = rtl_priv(hw);1587 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));1588 1589 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);1590 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);1591 rtlpci->irq_enabled = true;1592}1593 1594void rtl92ee_disable_interrupt(struct ieee80211_hw *hw)1595{1596 struct rtl_priv *rtlpriv = rtl_priv(hw);1597 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));1598 1599 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);1600 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);1601 rtlpci->irq_enabled = false;1602 /*synchronize_irq(rtlpci->pdev->irq);*/1603}1604 1605static void _rtl92ee_poweroff_adapter(struct ieee80211_hw *hw)1606{1607 struct rtl_priv *rtlpriv = rtl_priv(hw);1608 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));1609 u8 u1b_tmp;1610 1611 rtlhal->mac_func_enable = false;1612 1613 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n");1614 1615 /* Run LPS WL RFOFF flow */1616 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,1617 PWR_INTF_PCI_MSK, RTL8192E_NIC_LPS_ENTER_FLOW);1618 /* turn off RF */1619 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);1620 1621 /* ==== Reset digital sequence ====== */1622 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)1623 rtl92ee_firmware_selfreset(hw);1624 1625 /* Reset MCU */1626 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);1627 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));1628 1629 /* reset MCU ready status */1630 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);1631 1632 /* HW card disable configuration. */1633 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,1634 PWR_INTF_PCI_MSK, RTL8192E_NIC_DISABLE_FLOW);1635 1636 /* Reset MCU IO Wrapper */1637 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);1638 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));1639 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);1640 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp | BIT(0)));1641 1642 /* lock ISO/CLK/Power control register */1643 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);1644}1645 1646void rtl92ee_card_disable(struct ieee80211_hw *hw)1647{1648 struct rtl_priv *rtlpriv = rtl_priv(hw);1649 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));1650 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));1651 enum nl80211_iftype opmode;1652 1653 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8192ee card disable\n");1654 1655 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);1656 1657 mac->link_state = MAC80211_NOLINK;1658 opmode = NL80211_IFTYPE_UNSPECIFIED;1659 1660 _rtl92ee_set_media_status(hw, opmode);1661 1662 if (rtlpriv->rtlhal.driver_is_goingto_unload ||1663 ppsc->rfoff_reason > RF_CHANGE_BY_PS)1664 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);1665 1666 _rtl92ee_poweroff_adapter(hw);1667 1668 /* after power off we should do iqk again */1669 if (!rtlpriv->cfg->ops->get_btc_status())1670 rtlpriv->phy.iqk_initialized = false;1671}1672 1673void rtl92ee_interrupt_recognized(struct ieee80211_hw *hw,1674 struct rtl_int *intvec)1675{1676 struct rtl_priv *rtlpriv = rtl_priv(hw);1677 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));1678 1679 intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];1680 rtl_write_dword(rtlpriv, ISR, intvec->inta);1681 1682 intvec->intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];1683 rtl_write_dword(rtlpriv, REG_HISRE, intvec->intb);1684}1685 1686void rtl92ee_set_beacon_related_registers(struct ieee80211_hw *hw)1687{1688 struct rtl_priv *rtlpriv = rtl_priv(hw);1689 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));1690 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));1691 u16 bcn_interval, atim_window;1692 1693 bcn_interval = mac->beacon_interval;1694 atim_window = 2; /*FIX MERGE */1695 rtl92ee_disable_interrupt(hw);1696 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);1697 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);1698 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);1699 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);1700 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);1701 rtl_write_byte(rtlpriv, 0x606, 0x30);1702 rtlpci->reg_bcn_ctrl_val |= BIT(3);1703 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);1704}1705 1706void rtl92ee_set_beacon_interval(struct ieee80211_hw *hw)1707{1708 struct rtl_priv *rtlpriv = rtl_priv(hw);1709 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));1710 u16 bcn_interval = mac->beacon_interval;1711 1712 rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG,1713 "beacon_interval:%d\n", bcn_interval);1714 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);1715}1716 1717void rtl92ee_update_interrupt_mask(struct ieee80211_hw *hw,1718 u32 add_msr, u32 rm_msr)1719{1720 struct rtl_priv *rtlpriv = rtl_priv(hw);1721 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));1722 1723 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD,1724 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);1725 1726 if (add_msr)1727 rtlpci->irq_mask[0] |= add_msr;1728 if (rm_msr)1729 rtlpci->irq_mask[0] &= (~rm_msr);1730 rtl92ee_disable_interrupt(hw);1731 rtl92ee_enable_interrupt(hw);1732}1733 1734static u8 _rtl92ee_get_chnl_group(u8 chnl)1735{1736 u8 group = 0;1737 1738 if (chnl <= 14) {1739 if (1 <= chnl && chnl <= 2)1740 group = 0;1741 else if (3 <= chnl && chnl <= 5)1742 group = 1;1743 else if (6 <= chnl && chnl <= 8)1744 group = 2;1745 else if (9 <= chnl && chnl <= 11)1746 group = 3;1747 else if (12 <= chnl && chnl <= 14)1748 group = 4;1749 } else {1750 if (36 <= chnl && chnl <= 42)1751 group = 0;1752 else if (44 <= chnl && chnl <= 48)1753 group = 1;1754 else if (50 <= chnl && chnl <= 58)1755 group = 2;1756 else if (60 <= chnl && chnl <= 64)1757 group = 3;1758 else if (100 <= chnl && chnl <= 106)1759 group = 4;1760 else if (108 <= chnl && chnl <= 114)1761 group = 5;1762 else if (116 <= chnl && chnl <= 122)1763 group = 6;1764 else if (124 <= chnl && chnl <= 130)1765 group = 7;1766 else if (132 <= chnl && chnl <= 138)1767 group = 8;1768 else if (140 <= chnl && chnl <= 144)1769 group = 9;1770 else if (149 <= chnl && chnl <= 155)1771 group = 10;1772 else if (157 <= chnl && chnl <= 161)1773 group = 11;1774 else if (165 <= chnl && chnl <= 171)1775 group = 12;1776 else if (173 <= chnl && chnl <= 177)1777 group = 13;1778 }1779 return group;1780}1781 1782static void _rtl8192ee_read_power_value_fromprom(struct ieee80211_hw *hw,1783 struct txpower_info_2g *pwr2g,1784 struct txpower_info_5g *pwr5g,1785 bool autoload_fail, u8 *hwinfo)1786{1787 struct rtl_priv *rtlpriv = rtl_priv(hw);1788 u32 rf, addr = EEPROM_TX_PWR_INX, group, i = 0;1789 1790 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,1791 "hal_ReadPowerValueFromPROM92E(): PROMContent[0x%x]=0x%x\n",1792 (addr + 1), hwinfo[addr + 1]);1793 if (0xFF == hwinfo[addr+1]) /*YJ,add,120316*/1794 autoload_fail = true;1795 1796 if (autoload_fail) {1797 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,1798 "auto load fail : Use Default value!\n");1799 for (rf = 0 ; rf < MAX_RF_PATH ; rf++) {1800 /* 2.4G default value */1801 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {1802 pwr2g->index_cck_base[rf][group] = 0x2D;1803 pwr2g->index_bw40_base[rf][group] = 0x2D;1804 }1805 for (i = 0; i < MAX_TX_COUNT; i++) {1806 if (i == 0) {1807 pwr2g->bw20_diff[rf][0] = 0x02;1808 pwr2g->ofdm_diff[rf][0] = 0x04;1809 } else {1810 pwr2g->bw20_diff[rf][i] = 0xFE;1811 pwr2g->bw40_diff[rf][i] = 0xFE;1812 pwr2g->cck_diff[rf][i] = 0xFE;1813 pwr2g->ofdm_diff[rf][i] = 0xFE;1814 }1815 }1816 1817 /*5G default value*/1818 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)1819 pwr5g->index_bw40_base[rf][group] = 0x2A;1820 1821 for (i = 0; i < MAX_TX_COUNT; i++) {1822 if (i == 0) {1823 pwr5g->ofdm_diff[rf][0] = 0x04;1824 pwr5g->bw20_diff[rf][0] = 0x00;1825 pwr5g->bw80_diff[rf][0] = 0xFE;1826 pwr5g->bw160_diff[rf][0] = 0xFE;1827 } else {1828 pwr5g->ofdm_diff[rf][0] = 0xFE;1829 pwr5g->bw20_diff[rf][0] = 0xFE;1830 pwr5g->bw40_diff[rf][0] = 0xFE;1831 pwr5g->bw80_diff[rf][0] = 0xFE;1832 pwr5g->bw160_diff[rf][0] = 0xFE;1833 }1834 }1835 }1836 return;1837 }1838 1839 rtl_priv(hw)->efuse.txpwr_fromeprom = true;1840 1841 for (rf = 0 ; rf < MAX_RF_PATH ; rf++) {1842 /*2.4G default value*/1843 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {1844 pwr2g->index_cck_base[rf][group] = hwinfo[addr++];1845 if (pwr2g->index_cck_base[rf][group] == 0xFF)1846 pwr2g->index_cck_base[rf][group] = 0x2D;1847 }1848 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {1849 pwr2g->index_bw40_base[rf][group] = hwinfo[addr++];1850 if (pwr2g->index_bw40_base[rf][group] == 0xFF)1851 pwr2g->index_bw40_base[rf][group] = 0x2D;1852 }1853 for (i = 0; i < MAX_TX_COUNT; i++) {1854 if (i == 0) {1855 pwr2g->bw40_diff[rf][i] = 0;1856 if (hwinfo[addr] == 0xFF) {1857 pwr2g->bw20_diff[rf][i] = 0x02;1858 } else {1859 pwr2g->bw20_diff[rf][i] = (hwinfo[addr]1860 & 0xf0) >> 4;1861 if (pwr2g->bw20_diff[rf][i] & BIT(3))1862 pwr2g->bw20_diff[rf][i] |= 0xF0;1863 }1864 1865 if (hwinfo[addr] == 0xFF) {1866 pwr2g->ofdm_diff[rf][i] = 0x04;1867 } else {1868 pwr2g->ofdm_diff[rf][i] = (hwinfo[addr]1869 & 0x0f);1870 if (pwr2g->ofdm_diff[rf][i] & BIT(3))1871 pwr2g->ofdm_diff[rf][i] |= 0xF0;1872 }1873 pwr2g->cck_diff[rf][i] = 0;1874 addr++;1875 } else {1876 if (hwinfo[addr] == 0xFF) {1877 pwr2g->bw40_diff[rf][i] = 0xFE;1878 } else {1879 pwr2g->bw40_diff[rf][i] = (hwinfo[addr]1880 & 0xf0) >> 4;1881 if (pwr2g->bw40_diff[rf][i] & BIT(3))1882 pwr2g->bw40_diff[rf][i] |= 0xF0;1883 }1884 1885 if (hwinfo[addr] == 0xFF) {1886 pwr2g->bw20_diff[rf][i] = 0xFE;1887 } else {1888 pwr2g->bw20_diff[rf][i] = (hwinfo[addr]1889 & 0x0f);1890 if (pwr2g->bw20_diff[rf][i] & BIT(3))1891 pwr2g->bw20_diff[rf][i] |= 0xF0;1892 }1893 addr++;1894 1895 if (hwinfo[addr] == 0xFF) {1896 pwr2g->ofdm_diff[rf][i] = 0xFE;1897 } else {1898 pwr2g->ofdm_diff[rf][i] = (hwinfo[addr]1899 & 0xf0) >> 4;1900 if (pwr2g->ofdm_diff[rf][i] & BIT(3))1901 pwr2g->ofdm_diff[rf][i] |= 0xF0;1902 }1903 1904 if (hwinfo[addr] == 0xFF) {1905 pwr2g->cck_diff[rf][i] = 0xFE;1906 } else {1907 pwr2g->cck_diff[rf][i] = (hwinfo[addr]1908 & 0x0f);1909 if (pwr2g->cck_diff[rf][i] & BIT(3))1910 pwr2g->cck_diff[rf][i] |= 0xF0;1911 }1912 addr++;1913 }1914 }1915 1916 /*5G default value*/1917 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {1918 pwr5g->index_bw40_base[rf][group] = hwinfo[addr++];1919 if (pwr5g->index_bw40_base[rf][group] == 0xFF)1920 pwr5g->index_bw40_base[rf][group] = 0xFE;1921 }1922 1923 for (i = 0; i < MAX_TX_COUNT; i++) {1924 if (i == 0) {1925 pwr5g->bw40_diff[rf][i] = 0;1926 1927 if (hwinfo[addr] == 0xFF) {1928 pwr5g->bw20_diff[rf][i] = 0;1929 } else {1930 pwr5g->bw20_diff[rf][0] = (hwinfo[addr]1931 & 0xf0) >> 4;1932 if (pwr5g->bw20_diff[rf][i] & BIT(3))1933 pwr5g->bw20_diff[rf][i] |= 0xF0;1934 }1935 1936 if (hwinfo[addr] == 0xFF) {1937 pwr5g->ofdm_diff[rf][i] = 0x04;1938 } else {1939 pwr5g->ofdm_diff[rf][0] = (hwinfo[addr]1940 & 0x0f);1941 if (pwr5g->ofdm_diff[rf][i] & BIT(3))1942 pwr5g->ofdm_diff[rf][i] |= 0xF0;1943 }1944 addr++;1945 } else {1946 if (hwinfo[addr] == 0xFF) {1947 pwr5g->bw40_diff[rf][i] = 0xFE;1948 } else {1949 pwr5g->bw40_diff[rf][i] = (hwinfo[addr]1950 & 0xf0) >> 4;1951 if (pwr5g->bw40_diff[rf][i] & BIT(3))1952 pwr5g->bw40_diff[rf][i] |= 0xF0;1953 }1954 1955 if (hwinfo[addr] == 0xFF) {1956 pwr5g->bw20_diff[rf][i] = 0xFE;1957 } else {1958 pwr5g->bw20_diff[rf][i] = (hwinfo[addr]1959 & 0x0f);1960 if (pwr5g->bw20_diff[rf][i] & BIT(3))1961 pwr5g->bw20_diff[rf][i] |= 0xF0;1962 }1963 addr++;1964 }1965 }1966 1967 if (hwinfo[addr] == 0xFF) {1968 pwr5g->ofdm_diff[rf][1] = 0xFE;1969 pwr5g->ofdm_diff[rf][2] = 0xFE;1970 } else {1971 pwr5g->ofdm_diff[rf][1] = (hwinfo[addr] & 0xf0) >> 4;1972 pwr5g->ofdm_diff[rf][2] = (hwinfo[addr] & 0x0f);1973 }1974 addr++;1975 1976 if (hwinfo[addr] == 0xFF)1977 pwr5g->ofdm_diff[rf][3] = 0xFE;1978 else1979 pwr5g->ofdm_diff[rf][3] = (hwinfo[addr] & 0x0f);1980 addr++;1981 1982 for (i = 1; i < MAX_TX_COUNT; i++) {1983 if (pwr5g->ofdm_diff[rf][i] == 0xFF)1984 pwr5g->ofdm_diff[rf][i] = 0xFE;1985 else if (pwr5g->ofdm_diff[rf][i] & BIT(3))1986 pwr5g->ofdm_diff[rf][i] |= 0xF0;1987 }1988 1989 for (i = 0; i < MAX_TX_COUNT; i++) {1990 if (hwinfo[addr] == 0xFF) {1991 pwr5g->bw80_diff[rf][i] = 0xFE;1992 } else {1993 pwr5g->bw80_diff[rf][i] = (hwinfo[addr] & 0xf0)1994 >> 4;1995 if (pwr5g->bw80_diff[rf][i] & BIT(3))1996 pwr5g->bw80_diff[rf][i] |= 0xF0;1997 }1998 1999 if (hwinfo[addr] == 0xFF) {2000 pwr5g->bw160_diff[rf][i] = 0xFE;2001 } else {2002 pwr5g->bw160_diff[rf][i] =2003 (hwinfo[addr] & 0x0f);2004 if (pwr5g->bw160_diff[rf][i] & BIT(3))2005 pwr5g->bw160_diff[rf][i] |= 0xF0;2006 }2007 addr++;2008 }2009 }2010}2011 2012static void _rtl92ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,2013 bool autoload_fail, u8 *hwinfo)2014{2015 struct rtl_priv *rtlpriv = rtl_priv(hw);2016 struct rtl_efuse *efu = rtl_efuse(rtl_priv(hw));2017 struct txpower_info_2g pwr2g;2018 struct txpower_info_5g pwr5g;2019 u8 rf, idx;2020 u8 i;2021 2022 _rtl8192ee_read_power_value_fromprom(hw, &pwr2g, &pwr5g,2023 autoload_fail, hwinfo);2024 2025 for (rf = 0; rf < MAX_RF_PATH; rf++) {2026 for (i = 0; i < 14; i++) {2027 idx = _rtl92ee_get_chnl_group(i + 1);2028 2029 if (i == CHANNEL_MAX_NUMBER_2G - 1) {2030 efu->txpwrlevel_cck[rf][i] =2031 pwr2g.index_cck_base[rf][5];2032 efu->txpwrlevel_ht40_1s[rf][i] =2033 pwr2g.index_bw40_base[rf][idx];2034 } else {2035 efu->txpwrlevel_cck[rf][i] =2036 pwr2g.index_cck_base[rf][idx];2037 efu->txpwrlevel_ht40_1s[rf][i] =2038 pwr2g.index_bw40_base[rf][idx];2039 }2040 }2041 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {2042 idx = _rtl92ee_get_chnl_group(channel5g[i]);2043 efu->txpwr_5g_bw40base[rf][i] =2044 pwr5g.index_bw40_base[rf][idx];2045 }2046 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {2047 u8 upper, lower;2048 2049 idx = _rtl92ee_get_chnl_group(channel5g_80m[i]);2050 upper = pwr5g.index_bw40_base[rf][idx];2051 lower = pwr5g.index_bw40_base[rf][idx + 1];2052 2053 efu->txpwr_5g_bw80base[rf][i] = (upper + lower) / 2;2054 }2055 for (i = 0; i < MAX_TX_COUNT; i++) {2056 efu->txpwr_cckdiff[rf][i] = pwr2g.cck_diff[rf][i];2057 efu->txpwr_legacyhtdiff[rf][i] = pwr2g.ofdm_diff[rf][i];2058 efu->txpwr_ht20diff[rf][i] = pwr2g.bw20_diff[rf][i];2059 efu->txpwr_ht40diff[rf][i] = pwr2g.bw40_diff[rf][i];2060 2061 efu->txpwr_5g_ofdmdiff[rf][i] = pwr5g.ofdm_diff[rf][i];2062 efu->txpwr_5g_bw20diff[rf][i] = pwr5g.bw20_diff[rf][i];2063 efu->txpwr_5g_bw40diff[rf][i] = pwr5g.bw40_diff[rf][i];2064 efu->txpwr_5g_bw80diff[rf][i] = pwr5g.bw80_diff[rf][i];2065 }2066 }2067 2068 if (!autoload_fail)2069 efu->eeprom_thermalmeter = hwinfo[EEPROM_THERMAL_METER_92E];2070 else2071 efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;2072 2073 if (efu->eeprom_thermalmeter == 0xff || autoload_fail) {2074 efu->apk_thermalmeterignore = true;2075 efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;2076 }2077 2078 efu->thermalmeter[0] = efu->eeprom_thermalmeter;2079 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,2080 "thermalmeter = 0x%x\n", efu->eeprom_thermalmeter);2081 2082 if (!autoload_fail) {2083 efu->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION_92E]2084 & 0x07;2085 if (hwinfo[EEPROM_RF_BOARD_OPTION_92E] == 0xFF)2086 efu->eeprom_regulatory = 0;2087 } else {2088 efu->eeprom_regulatory = 0;2089 }2090 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,2091 "eeprom_regulatory = 0x%x\n", efu->eeprom_regulatory);2092}2093 2094static void _rtl92ee_read_adapter_info(struct ieee80211_hw *hw)2095{2096 struct rtl_priv *rtlpriv = rtl_priv(hw);2097 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));2098 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));2099 int params[] = {RTL8192E_EEPROM_ID, EEPROM_VID, EEPROM_DID,2100 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,2101 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,2102 COUNTRY_CODE_WORLD_WIDE_13};2103 u8 *hwinfo;2104 2105 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);2106 if (!hwinfo)2107 return;2108 2109 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))2110 goto exit;2111 2112 if (rtlefuse->eeprom_oemid == 0xFF)2113 rtlefuse->eeprom_oemid = 0;2114 2115 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,2116 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);2117 /* set channel plan from efuse */2118 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;2119 /*tx power*/2120 _rtl92ee_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,2121 hwinfo);2122 2123 rtl92ee_read_bt_coexist_info_from_hwpg(hw, rtlefuse->autoload_failflag,2124 hwinfo);2125 2126 /*board type*/2127 rtlefuse->board_type = (((*(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION_92E])2128 & 0xE0) >> 5);2129 if ((*(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION_92E]) == 0xFF)2130 rtlefuse->board_type = 0;2131 2132 if (rtlpriv->btcoexist.btc_info.btcoexist == 1)2133 rtlefuse->board_type |= BIT(2); /* ODM_BOARD_BT */2134 2135 rtlhal->board_type = rtlefuse->board_type;2136 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,2137 "board_type = 0x%x\n", rtlefuse->board_type);2138 /*parse xtal*/2139 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_92E];2140 if (hwinfo[EEPROM_XTAL_92E] == 0xFF)2141 rtlefuse->crystalcap = 0x20;2142 2143 /*antenna diversity*/2144 rtlefuse->antenna_div_type = NO_ANTDIV;2145 rtlefuse->antenna_div_cfg = 0;2146 2147 if (rtlhal->oem_id == RT_CID_DEFAULT) {2148 switch (rtlefuse->eeprom_oemid) {2149 case EEPROM_CID_DEFAULT:2150 if (rtlefuse->eeprom_did == 0x818B) {2151 if ((rtlefuse->eeprom_svid == 0x10EC) &&2152 (rtlefuse->eeprom_smid == 0x001B))2153 rtlhal->oem_id = RT_CID_819X_LENOVO;2154 } else {2155 rtlhal->oem_id = RT_CID_DEFAULT;2156 }2157 break;2158 default:2159 rtlhal->oem_id = RT_CID_DEFAULT;2160 break;2161 }2162 }2163exit:2164 kfree(hwinfo);2165}2166 2167static void _rtl92ee_hal_customized_behavior(struct ieee80211_hw *hw)2168{2169 struct rtl_priv *rtlpriv = rtl_priv(hw);2170 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));2171 2172 rtlpriv->ledctl.led_opendrain = true;2173 2174 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,2175 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);2176}2177 2178void rtl92ee_read_eeprom_info(struct ieee80211_hw *hw)2179{2180 struct rtl_priv *rtlpriv = rtl_priv(hw);2181 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));2182 struct rtl_phy *rtlphy = &rtlpriv->phy;2183 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));2184 u8 tmp_u1b;2185 2186 rtlhal->version = _rtl92ee_read_chip_version(hw);2187 if (get_rf_type(rtlphy) == RF_1T1R) {2188 rtlpriv->dm.rfpath_rxenable[0] = true;2189 } else {2190 rtlpriv->dm.rfpath_rxenable[0] = true;2191 rtlpriv->dm.rfpath_rxenable[1] = true;2192 }2193 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",2194 rtlhal->version);2195 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);2196 if (tmp_u1b & BIT(4)) {2197 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");2198 rtlefuse->epromtype = EEPROM_93C46;2199 } else {2200 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");2201 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;2202 }2203 if (tmp_u1b & BIT(5)) {2204 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");2205 rtlefuse->autoload_failflag = false;2206 _rtl92ee_read_adapter_info(hw);2207 } else {2208 pr_err("Autoload ERR!!\n");2209 }2210 _rtl92ee_hal_customized_behavior(hw);2211 2212 rtlphy->rfpath_rx_enable[0] = true;2213 if (rtlphy->rf_type == RF_2T2R)2214 rtlphy->rfpath_rx_enable[1] = true;2215}2216 2217static u8 _rtl92ee_mrate_idx_to_arfr_id(struct ieee80211_hw *hw, u8 rate_index)2218{2219 u8 ret = 0;2220 2221 switch (rate_index) {2222 case RATR_INX_WIRELESS_NGB:2223 ret = 0;2224 break;2225 case RATR_INX_WIRELESS_N:2226 case RATR_INX_WIRELESS_NG:2227 ret = 4;2228 break;2229 case RATR_INX_WIRELESS_NB:2230 ret = 2;2231 break;2232 case RATR_INX_WIRELESS_GB:2233 ret = 6;2234 break;2235 case RATR_INX_WIRELESS_G:2236 ret = 7;2237 break;2238 case RATR_INX_WIRELESS_B:2239 ret = 8;2240 break;2241 default:2242 ret = 0;2243 break;2244 }2245 return ret;2246}2247 2248static void rtl92ee_update_hal_rate_mask(struct ieee80211_hw *hw,2249 struct ieee80211_sta *sta,2250 u8 rssi_level, bool update_bw)2251{2252 struct rtl_priv *rtlpriv = rtl_priv(hw);2253 struct rtl_phy *rtlphy = &rtlpriv->phy;2254 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));2255 struct rtl_sta_info *sta_entry = NULL;2256 u32 ratr_bitmap;2257 u8 ratr_index;2258 u8 curtxbw_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)2259 ? 1 : 0;2260 u8 b_curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?2261 1 : 0;2262 u8 b_curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?2263 1 : 0;2264 enum wireless_mode wirelessmode = 0;2265 bool b_shortgi = false;2266 u8 rate_mask[7] = {0};2267 u8 macid = 0;2268 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/2269 sta_entry = (struct rtl_sta_info *)sta->drv_priv;2270 wirelessmode = sta_entry->wireless_mode;2271 if (mac->opmode == NL80211_IFTYPE_STATION ||2272 mac->opmode == NL80211_IFTYPE_MESH_POINT)2273 curtxbw_40mhz = mac->bw_40;2274 else if (mac->opmode == NL80211_IFTYPE_AP ||2275 mac->opmode == NL80211_IFTYPE_ADHOC)2276 macid = sta->aid + 1;2277 2278 ratr_bitmap = sta->deflink.supp_rates[0];2279 if (mac->opmode == NL80211_IFTYPE_ADHOC)2280 ratr_bitmap = 0xfff;2281 2282 ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |2283 sta->deflink.ht_cap.mcs.rx_mask[0] << 12);2284 2285 switch (wirelessmode) {2286 case WIRELESS_MODE_B:2287 ratr_index = RATR_INX_WIRELESS_B;2288 if (ratr_bitmap & 0x0000000c)2289 ratr_bitmap &= 0x0000000d;2290 else2291 ratr_bitmap &= 0x0000000f;2292 break;2293 case WIRELESS_MODE_G:2294 ratr_index = RATR_INX_WIRELESS_GB;2295 2296 if (rssi_level == 1)2297 ratr_bitmap &= 0x00000f00;2298 else if (rssi_level == 2)2299 ratr_bitmap &= 0x00000ff0;2300 else2301 ratr_bitmap &= 0x00000ff5;2302 break;2303 case WIRELESS_MODE_N_24G:2304 if (curtxbw_40mhz)2305 ratr_index = RATR_INX_WIRELESS_NGB;2306 else2307 ratr_index = RATR_INX_WIRELESS_NB;2308 2309 if (rtlphy->rf_type == RF_1T1R) {2310 if (curtxbw_40mhz) {2311 if (rssi_level == 1)2312 ratr_bitmap &= 0x000f0000;2313 else if (rssi_level == 2)2314 ratr_bitmap &= 0x000ff000;2315 else2316 ratr_bitmap &= 0x000ff015;2317 } else {2318 if (rssi_level == 1)2319 ratr_bitmap &= 0x000f0000;2320 else if (rssi_level == 2)2321 ratr_bitmap &= 0x000ff000;2322 else2323 ratr_bitmap &= 0x000ff005;2324 }2325 } else {2326 if (curtxbw_40mhz) {2327 if (rssi_level == 1)2328 ratr_bitmap &= 0x0f8f0000;2329 else if (rssi_level == 2)2330 ratr_bitmap &= 0x0ffff000;2331 else2332 ratr_bitmap &= 0x0ffff015;2333 } else {2334 if (rssi_level == 1)2335 ratr_bitmap &= 0x0f8f0000;2336 else if (rssi_level == 2)2337 ratr_bitmap &= 0x0ffff000;2338 else2339 ratr_bitmap &= 0x0ffff005;2340 }2341 }2342 2343 if ((curtxbw_40mhz && b_curshortgi_40mhz) ||2344 (!curtxbw_40mhz && b_curshortgi_20mhz)) {2345 if (macid == 0)2346 b_shortgi = true;2347 else if (macid == 1)2348 b_shortgi = false;2349 }2350 break;2351 default:2352 ratr_index = RATR_INX_WIRELESS_NGB;2353 2354 if (rtlphy->rf_type == RF_1T1R)2355 ratr_bitmap &= 0x000ff0ff;2356 else2357 ratr_bitmap &= 0x0f8ff0ff;2358 break;2359 }2360 ratr_index = _rtl92ee_mrate_idx_to_arfr_id(hw, ratr_index);2361 sta_entry->ratr_index = ratr_index;2362 2363 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,2364 "ratr_bitmap :%x\n", ratr_bitmap);2365 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |2366 (ratr_index << 28);2367 rate_mask[0] = macid;2368 rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00);2369 rate_mask[2] = curtxbw_40mhz | ((!update_bw) << 3);2370 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);2371 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);2372 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);2373 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);2374 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,2375 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",2376 ratr_index, ratr_bitmap, rate_mask[0], rate_mask[1],2377 rate_mask[2], rate_mask[3], rate_mask[4],2378 rate_mask[5], rate_mask[6]);2379 rtl92ee_fill_h2c_cmd(hw, H2C_92E_RA_MASK, 7, rate_mask);2380 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0);2381}2382 2383void rtl92ee_update_hal_rate_tbl(struct ieee80211_hw *hw,2384 struct ieee80211_sta *sta, u8 rssi_level,2385 bool update_bw)2386{2387 struct rtl_priv *rtlpriv = rtl_priv(hw);2388 2389 if (rtlpriv->dm.useramask)2390 rtl92ee_update_hal_rate_mask(hw, sta, rssi_level, update_bw);2391}2392 2393void rtl92ee_update_channel_access_setting(struct ieee80211_hw *hw)2394{2395 struct rtl_priv *rtlpriv = rtl_priv(hw);2396 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));2397 u16 sifs_timer;2398 2399 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,2400 (u8 *)&mac->slot_time);2401 if (!mac->ht_enable)2402 sifs_timer = 0x0a0a;2403 else2404 sifs_timer = 0x0e0e;2405 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);2406}2407 2408bool rtl92ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)2409{2410 *valid = 1;2411 return true;2412}2413 2414void rtl92ee_set_key(struct ieee80211_hw *hw, u32 key_index,2415 u8 *p_macaddr, bool is_group, u8 enc_algo,2416 bool is_wepkey, bool clear_all)2417{2418 struct rtl_priv *rtlpriv = rtl_priv(hw);2419 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));2420 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));2421 u8 *macaddr = p_macaddr;2422 u32 entry_id = 0;2423 bool is_pairwise = false;2424 2425 static u8 cam_const_addr[4][6] = {2426 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},2427 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},2428 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},2429 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}2430 };2431 static u8 cam_const_broad[] = {2432 0xff, 0xff, 0xff, 0xff, 0xff, 0xff2433 };2434 2435 if (clear_all) {2436 u8 idx = 0;2437 u8 cam_offset = 0;2438 u8 clear_number = 5;2439 2440 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");2441 2442 for (idx = 0; idx < clear_number; idx++) {2443 rtl_cam_mark_invalid(hw, cam_offset + idx);2444 rtl_cam_empty_entry(hw, cam_offset + idx);2445 2446 if (idx < 5) {2447 memset(rtlpriv->sec.key_buf[idx], 0,2448 MAX_KEY_LEN);2449 rtlpriv->sec.key_len[idx] = 0;2450 }2451 }2452 2453 } else {2454 switch (enc_algo) {2455 case WEP40_ENCRYPTION:2456 enc_algo = CAM_WEP40;2457 break;2458 case WEP104_ENCRYPTION:2459 enc_algo = CAM_WEP104;2460 break;2461 case TKIP_ENCRYPTION:2462 enc_algo = CAM_TKIP;2463 break;2464 case AESCCMP_ENCRYPTION:2465 enc_algo = CAM_AES;2466 break;2467 default:2468 rtl_dbg(rtlpriv, COMP_ERR, DBG_DMESG,2469 "switch case %#x not processed\n", enc_algo);2470 enc_algo = CAM_TKIP;2471 break;2472 }2473 2474 if (is_wepkey || rtlpriv->sec.use_defaultkey) {2475 macaddr = cam_const_addr[key_index];2476 entry_id = key_index;2477 } else {2478 if (is_group) {2479 macaddr = cam_const_broad;2480 entry_id = key_index;2481 } else {2482 if (mac->opmode == NL80211_IFTYPE_AP ||2483 mac->opmode == NL80211_IFTYPE_MESH_POINT) {2484 entry_id = rtl_cam_get_free_entry(hw,2485 p_macaddr);2486 if (entry_id >= TOTAL_CAM_ENTRY) {2487 pr_err("Can not find free hw security cam entry\n");2488 return;2489 }2490 } else {2491 entry_id = CAM_PAIRWISE_KEY_POSITION;2492 }2493 2494 key_index = PAIRWISE_KEYIDX;2495 is_pairwise = true;2496 }2497 }2498 2499 if (rtlpriv->sec.key_len[key_index] == 0) {2500 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,2501 "delete one entry, entry_id is %d\n",2502 entry_id);2503 if (mac->opmode == NL80211_IFTYPE_AP ||2504 mac->opmode == NL80211_IFTYPE_MESH_POINT)2505 rtl_cam_del_entry(hw, p_macaddr);2506 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);2507 } else {2508 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,2509 "add one entry\n");2510 if (is_pairwise) {2511 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,2512 "set Pairwise key\n");2513 2514 rtl_cam_add_one_entry(hw, macaddr, key_index,2515 entry_id, enc_algo,2516 CAM_CONFIG_NO_USEDK,2517 rtlpriv->sec.key_buf[key_index]);2518 } else {2519 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,2520 "set group key\n");2521 2522 if (mac->opmode == NL80211_IFTYPE_ADHOC) {2523 rtl_cam_add_one_entry(hw,2524 rtlefuse->dev_addr,2525 PAIRWISE_KEYIDX,2526 CAM_PAIRWISE_KEY_POSITION,2527 enc_algo, CAM_CONFIG_NO_USEDK,2528 rtlpriv->sec.key_buf[entry_id]);2529 }2530 2531 rtl_cam_add_one_entry(hw, macaddr, key_index,2532 entry_id, enc_algo,2533 CAM_CONFIG_NO_USEDK,2534 rtlpriv->sec.key_buf[entry_id]);2535 }2536 }2537 }2538}2539 2540void rtl92ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,2541 bool auto_load_fail, u8 *hwinfo)2542{2543 struct rtl_priv *rtlpriv = rtl_priv(hw);2544 u8 value;2545 2546 if (!auto_load_fail) {2547 value = hwinfo[EEPROM_RF_BOARD_OPTION_92E];2548 if (((value & 0xe0) >> 5) == 0x1)2549 rtlpriv->btcoexist.btc_info.btcoexist = 1;2550 else2551 rtlpriv->btcoexist.btc_info.btcoexist = 0;2552 2553 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8192E;2554 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;2555 } else {2556 rtlpriv->btcoexist.btc_info.btcoexist = 1;2557 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8192E;2558 rtlpriv->btcoexist.btc_info.ant_num = ANT_X1;2559 }2560}2561 2562void rtl92ee_bt_reg_init(struct ieee80211_hw *hw)2563{2564 struct rtl_priv *rtlpriv = rtl_priv(hw);2565 2566 /* 0:Low, 1:High, 2:From Efuse. */2567 rtlpriv->btcoexist.reg_bt_iso = 2;2568 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */2569 rtlpriv->btcoexist.reg_bt_sco = 3;2570 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */2571 rtlpriv->btcoexist.reg_bt_sco = 0;2572}2573 2574void rtl92ee_bt_hw_init(struct ieee80211_hw *hw)2575{2576 struct rtl_priv *rtlpriv = rtl_priv(hw);2577 2578 if (rtlpriv->cfg->ops->get_btc_status())2579 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);2580}2581 2582void rtl92ee_suspend(struct ieee80211_hw *hw)2583{2584}2585 2586void rtl92ee_resume(struct ieee80211_hw *hw)2587{2588}2589 2590/* Turn on AAP (RCR:bit 0) for promicuous mode. */2591void rtl92ee_allow_all_destaddr(struct ieee80211_hw *hw,2592 bool allow_all_da, bool write_into_reg)2593{2594 struct rtl_priv *rtlpriv = rtl_priv(hw);2595 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));2596 2597 if (allow_all_da) /* Set BIT0 */2598 rtlpci->receive_config |= RCR_AAP;2599 else /* Clear BIT0 */2600 rtlpci->receive_config &= ~RCR_AAP;2601 2602 if (write_into_reg)2603 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);2604 2605 rtl_dbg(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,2606 "receive_config=0x%08X, write_into_reg=%d\n",2607 rtlpci->receive_config, write_into_reg);2608}2609