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1// SPDX-License-Identifier: GPL-2.02/* Copyright(c) 2009-2014 Realtek Corporation.*/3 4#include "../wifi.h"5#include "../core.h"6#include "../pci.h"7#include "reg.h"8#include "def.h"9#include "phy.h"10#include "dm.h"11#include "hw.h"12#include "fw.h"13#include "trx.h"14#include "led.h"15#include "table.h"16 17#include "../btcoexist/rtl_btc.h"18 19#include <linux/vmalloc.h>20#include <linux/module.h>21 22static void rtl92ee_init_aspm_vars(struct ieee80211_hw *hw)23{24 struct rtl_priv *rtlpriv = rtl_priv(hw);25 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));26 27 /**28 * ASPM PS mode.29 * 0 - Disable ASPM,30 * 1 - Enable ASPM without Clock Req,31 * 2 - Enable ASPM with Clock Req,32 * 3 - Alwyas Enable ASPM with Clock Req,33 * 4 - Always Enable ASPM without Clock Req.34 * set default to RTL8192CE:3 RTL8192E:235 */36 rtlpci->const_pci_aspm = 3;37 38 /*Setting for PCI-E device */39 rtlpci->const_devicepci_aspm_setting = 0x03;40 41 /*Setting for PCI-E bridge */42 rtlpci->const_hostpci_aspm_setting = 0x02;43 44 /**45 * In Hw/Sw Radio Off situation.46 * 0 - Default,47 * 1 - From ASPM setting without low Mac Pwr,48 * 2 - From ASPM setting with low Mac Pwr,49 * 3 - Bus D350 * set default to RTL8192CE:0 RTL8192SE:251 */52 rtlpci->const_hwsw_rfoff_d3 = 0;53 54 /**55 * This setting works for those device with56 * backdoor ASPM setting such as EPHY setting.57 * 0 - Not support ASPM,58 * 1 - Support ASPM,59 * 2 - According to chipset.60 */61 rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;62}63 64static int rtl92ee_init_sw_vars(struct ieee80211_hw *hw)65{66 struct rtl_priv *rtlpriv = rtl_priv(hw);67 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));68 int err = 0;69 char *fw_name;70 71 rtl92ee_bt_reg_init(hw);72 rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;73 rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();74 75 rtlpriv->dm.dm_initialgain_enable = true;76 rtlpriv->dm.dm_flag = 0;77 rtlpriv->dm.disable_framebursting = false;78 rtlpci->transmit_config = CFENDFORM | BIT(15);79 80 /*just 2.4G band*/81 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;82 rtlpriv->rtlhal.bandset = BAND_ON_2_4G;83 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;84 85 rtlpci->receive_config = (RCR_APPFCS |86 RCR_APP_MIC |87 RCR_APP_ICV |88 RCR_APP_PHYST_RXFF |89 RCR_HTC_LOC_CTRL |90 RCR_AMF |91 RCR_ACF |92 RCR_ACRC32 |93 RCR_AB |94 RCR_AM |95 RCR_APM |96 0);97 98 rtlpci->irq_mask[0] = (u32)(IMR_PSTIMEOUT |99 IMR_C2HCMD |100 IMR_HIGHDOK |101 IMR_MGNTDOK |102 IMR_BKDOK |103 IMR_BEDOK |104 IMR_VIDOK |105 IMR_VODOK |106 IMR_RDU |107 IMR_ROK |108 0);109 rtlpci->irq_mask[1] = (u32)(IMR_RXFOVW | 0);110 111 /* for LPS & IPS */112 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;113 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;114 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;115 rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;116 if (rtlpriv->cfg->mod_params->disable_watchdog)117 pr_info("watchdog disabled\n");118 rtlpriv->psc.reg_fwctrl_lps = 3;119 rtlpriv->psc.reg_max_lps_awakeintvl = 5;120 /* for ASPM, you can close aspm through121 * set const_support_pciaspm = 0122 */123 rtl92ee_init_aspm_vars(hw);124 125 if (rtlpriv->psc.reg_fwctrl_lps == 1)126 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;127 else if (rtlpriv->psc.reg_fwctrl_lps == 2)128 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;129 else if (rtlpriv->psc.reg_fwctrl_lps == 3)130 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;131 132 /* for early mode */133 rtlpriv->rtlhal.earlymode_enable = false;134 135 /*low power */136 rtlpriv->psc.low_power_enable = false;137 138 /* for firmware buf */139 rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);140 if (!rtlpriv->rtlhal.pfirmware) {141 pr_err("Can't alloc buffer for fw\n");142 return 1;143 }144 145 /* request fw */146 fw_name = "rtlwifi/rtl8192eefw.bin";147 148 rtlpriv->max_fw_size = 0x8000;149 pr_info("Using firmware %s\n", fw_name);150 err = request_firmware_nowait(THIS_MODULE, 1, fw_name,151 rtlpriv->io.dev, GFP_KERNEL, hw,152 rtl_fw_cb);153 if (err) {154 pr_err("Failed to request firmware!\n");155 vfree(rtlpriv->rtlhal.pfirmware);156 rtlpriv->rtlhal.pfirmware = NULL;157 return 1;158 }159 160 return 0;161}162 163static void rtl92ee_deinit_sw_vars(struct ieee80211_hw *hw)164{165 struct rtl_priv *rtlpriv = rtl_priv(hw);166 167 if (rtlpriv->rtlhal.pfirmware) {168 vfree(rtlpriv->rtlhal.pfirmware);169 rtlpriv->rtlhal.pfirmware = NULL;170 }171}172 173/* get bt coexist status */174static bool rtl92ee_get_btc_status(void)175{176 return true;177}178 179static struct rtl_hal_ops rtl8192ee_hal_ops = {180 .init_sw_vars = rtl92ee_init_sw_vars,181 .deinit_sw_vars = rtl92ee_deinit_sw_vars,182 .read_eeprom_info = rtl92ee_read_eeprom_info,183 .interrupt_recognized = rtl92ee_interrupt_recognized,/*need check*/184 .hw_init = rtl92ee_hw_init,185 .hw_disable = rtl92ee_card_disable,186 .hw_suspend = rtl92ee_suspend,187 .hw_resume = rtl92ee_resume,188 .enable_interrupt = rtl92ee_enable_interrupt,189 .disable_interrupt = rtl92ee_disable_interrupt,190 .set_network_type = rtl92ee_set_network_type,191 .set_chk_bssid = rtl92ee_set_check_bssid,192 .set_qos = rtl92ee_set_qos,193 .set_bcn_reg = rtl92ee_set_beacon_related_registers,194 .set_bcn_intv = rtl92ee_set_beacon_interval,195 .update_interrupt_mask = rtl92ee_update_interrupt_mask,196 .get_hw_reg = rtl92ee_get_hw_reg,197 .set_hw_reg = rtl92ee_set_hw_reg,198 .update_rate_tbl = rtl92ee_update_hal_rate_tbl,199 .rx_desc_buff_remained_cnt = rtl92ee_rx_desc_buff_remained_cnt,200 .rx_check_dma_ok = rtl92ee_rx_check_dma_ok,201 .fill_tx_desc = rtl92ee_tx_fill_desc,202 .fill_tx_cmddesc = rtl92ee_tx_fill_cmddesc,203 .query_rx_desc = rtl92ee_rx_query_desc,204 .set_channel_access = rtl92ee_update_channel_access_setting,205 .radio_onoff_checking = rtl92ee_gpio_radio_on_off_checking,206 .set_bw_mode = rtl92ee_phy_set_bw_mode,207 .switch_channel = rtl92ee_phy_sw_chnl,208 .dm_watchdog = rtl92ee_dm_watchdog,209 .scan_operation_backup = rtl92ee_phy_scan_operation_backup,210 .set_rf_power_state = rtl92ee_phy_set_rf_power_state,211 .led_control = rtl92ee_led_control,212 .set_desc = rtl92ee_set_desc,213 .get_desc = rtl92ee_get_desc,214 .is_tx_desc_closed = rtl92ee_is_tx_desc_closed,215 .get_available_desc = rtl92ee_get_available_desc,216 .tx_polling = rtl92ee_tx_polling,217 .enable_hw_sec = rtl92ee_enable_hw_security_config,218 .set_key = rtl92ee_set_key,219 .get_bbreg = rtl92ee_phy_query_bb_reg,220 .set_bbreg = rtl92ee_phy_set_bb_reg,221 .get_rfreg = rtl92ee_phy_query_rf_reg,222 .set_rfreg = rtl92ee_phy_set_rf_reg,223 .fill_h2c_cmd = rtl92ee_fill_h2c_cmd,224 .get_btc_status = rtl92ee_get_btc_status,225 .c2h_ra_report_handler = rtl92ee_c2h_ra_report_handler,226};227 228static struct rtl_mod_params rtl92ee_mod_params = {229 .sw_crypto = false,230 .inactiveps = true,231 .swctrl_lps = false,232 .fwctrl_lps = true,233 .msi_support = true,234 .dma64 = false,235 .aspm_support = 1,236 .debug_level = 0,237 .debug_mask = 0,238};239 240static const struct rtl_hal_cfg rtl92ee_hal_cfg = {241 .bar_id = 2,242 .write_readback = true,243 .name = "rtl92ee_pci",244 .ops = &rtl8192ee_hal_ops,245 .mod_params = &rtl92ee_mod_params,246 247 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,248 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,249 .maps[SYS_CLK] = REG_SYS_CLKR,250 .maps[MAC_RCR_AM] = AM,251 .maps[MAC_RCR_AB] = AB,252 .maps[MAC_RCR_ACRC32] = ACRC32,253 .maps[MAC_RCR_ACF] = ACF,254 .maps[MAC_RCR_AAP] = AAP,255 .maps[MAC_HIMR] = REG_HIMR,256 .maps[MAC_HIMRE] = REG_HIMRE,257 258 .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,259 260 .maps[EFUSE_TEST] = REG_EFUSE_TEST,261 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,262 .maps[EFUSE_CLK] = 0,263 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,264 .maps[EFUSE_PWC_EV12V] = PWC_EV12V,265 .maps[EFUSE_FEN_ELDR] = FEN_ELDR,266 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,267 .maps[EFUSE_ANA8M] = ANA8M,268 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,269 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,270 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,271 .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,272 273 .maps[RWCAM] = REG_CAMCMD,274 .maps[WCAMI] = REG_CAMWRITE,275 .maps[RCAMO] = REG_CAMREAD,276 .maps[CAMDBG] = REG_CAMDBG,277 .maps[SECR] = REG_SECCFG,278 .maps[SEC_CAM_NONE] = CAM_NONE,279 .maps[SEC_CAM_WEP40] = CAM_WEP40,280 .maps[SEC_CAM_TKIP] = CAM_TKIP,281 .maps[SEC_CAM_AES] = CAM_AES,282 .maps[SEC_CAM_WEP104] = CAM_WEP104,283 284 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,285 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,286 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,287 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,288 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,289 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,290 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,291 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,292 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,293 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,294 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,295 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,296 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,297 298 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,299 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,300 .maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,301 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,302 .maps[RTL_IMR_RDU] = IMR_RDU,303 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,304 .maps[RTL_IMR_BDOK] = IMR_BCNDOK0,305 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,306 .maps[RTL_IMR_TBDER] = IMR_TBDER,307 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,308 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,309 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,310 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,311 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,312 .maps[RTL_IMR_VODOK] = IMR_VODOK,313 .maps[RTL_IMR_ROK] = IMR_ROK,314 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),315 316 .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,317 .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,318 .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,319 .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,320 .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,321 .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,322 .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,323 .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,324 .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,325 .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,326 .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,327 .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,328 329 .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,330 .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,331};332 333static const struct pci_device_id rtl92ee_pci_ids[] = {334 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x818B, rtl92ee_hal_cfg)},335 {},336};337 338MODULE_DEVICE_TABLE(pci, rtl92ee_pci_ids);339 340MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");341MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");342MODULE_LICENSE("GPL");343MODULE_DESCRIPTION("Realtek 8192EE 802.11n PCI wireless");344MODULE_FIRMWARE("rtlwifi/rtl8192eefw.bin");345 346module_param_named(swenc, rtl92ee_mod_params.sw_crypto, bool, 0444);347module_param_named(debug_level, rtl92ee_mod_params.debug_level, int, 0644);348module_param_named(debug_mask, rtl92ee_mod_params.debug_mask, ullong, 0644);349module_param_named(ips, rtl92ee_mod_params.inactiveps, bool, 0444);350module_param_named(swlps, rtl92ee_mod_params.swctrl_lps, bool, 0444);351module_param_named(fwlps, rtl92ee_mod_params.fwctrl_lps, bool, 0444);352module_param_named(msi, rtl92ee_mod_params.msi_support, bool, 0444);353module_param_named(dma64, rtl92ee_mod_params.dma64, bool, 0444);354module_param_named(aspm, rtl92ee_mod_params.aspm_support, int, 0444);355module_param_named(disable_watchdog, rtl92ee_mod_params.disable_watchdog,356 bool, 0444);357MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");358MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");359MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");360MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");361MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 1)\n");362MODULE_PARM_DESC(dma64, "Set to 1 to use DMA 64 (default 0)\n");363MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");364MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");365MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");366MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n");367 368static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);369 370static struct pci_driver rtl92ee_driver = {371 .name = KBUILD_MODNAME,372 .id_table = rtl92ee_pci_ids,373 .probe = rtl_pci_probe,374 .remove = rtl_pci_disconnect,375 .driver.pm = &rtlwifi_pm_ops,376};377 378module_pci_driver(rtl92ee_driver);379