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1// SPDX-License-Identifier: GPL-2.02/* Copyright(c) 2009-2014 Realtek Corporation.*/3 4#include "../wifi.h"5#include "../pci.h"6#include "../base.h"7#include "../stats.h"8#include "reg.h"9#include "def.h"10#include "phy.h"11#include "trx.h"12#include "led.h"13#include "dm.h"14#include "fw.h"15 16static u8 _rtl92ee_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)17{18 __le16 fc = rtl_get_fc(skb);19 20 if (unlikely(ieee80211_is_beacon(fc)))21 return QSLT_BEACON;22 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))23 return QSLT_MGNT;24 25 return skb->priority;26}27 28static void _rtl92ee_query_rxphystatus(struct ieee80211_hw *hw,29 struct rtl_stats *pstatus, u8 *pdesc,30 struct rx_fwinfo *p_drvinfo,31 bool bpacket_match_bssid,32 bool bpacket_toself,33 bool packet_beacon)34{35 struct rtl_priv *rtlpriv = rtl_priv(hw);36 struct phy_status_rpt *p_phystrpt = (struct phy_status_rpt *)p_drvinfo;37 s8 rx_pwr_all, rx_pwr[4];38 u8 rf_rx_num = 0, evm, pwdb_all;39 u8 i, max_spatial_stream;40 u32 rssi, total_rssi = 0;41 bool is_cck = pstatus->is_cck;42 u8 lan_idx, vga_idx;43 44 /* Record it for next packet processing */45 pstatus->packet_matchbssid = bpacket_match_bssid;46 pstatus->packet_toself = bpacket_toself;47 pstatus->packet_beacon = packet_beacon;48 pstatus->rx_mimo_signalquality[0] = -1;49 pstatus->rx_mimo_signalquality[1] = -1;50 51 if (is_cck) {52 u8 cck_highpwr;53 u8 cck_agc_rpt;54 /* CCK Driver info Structure is not the same as OFDM packet. */55 cck_agc_rpt = p_phystrpt->cck_agc_rpt_ofdm_cfosho_a;56 57 /* (1)Hardware does not provide RSSI for CCK58 * (2)PWDB, Average PWDB calculated by59 * hardware (for rate adaptive)60 */61 cck_highpwr = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2,62 BIT(9));63 64 lan_idx = ((cck_agc_rpt & 0xE0) >> 5);65 vga_idx = (cck_agc_rpt & 0x1f);66 switch (lan_idx) {67 case 7: /*VGA_idx = 27~2*/68 if (vga_idx <= 27)69 rx_pwr_all = -100 + 2 * (27 - vga_idx);70 else71 rx_pwr_all = -100;72 break;73 case 6: /*VGA_idx = 2~0*/74 rx_pwr_all = -48 + 2 * (2 - vga_idx);75 break;76 case 5: /*VGA_idx = 7~5*/77 rx_pwr_all = -42 + 2 * (7 - vga_idx);78 break;79 case 4: /*VGA_idx = 7~4*/80 rx_pwr_all = -36 + 2 * (7 - vga_idx);81 break;82 case 3: /*VGA_idx = 7~0*/83 rx_pwr_all = -24 + 2 * (7 - vga_idx);84 break;85 case 2: /*VGA_idx = 5~0*/86 if (cck_highpwr)87 rx_pwr_all = -12 + 2 * (5 - vga_idx);88 else89 rx_pwr_all = -6 + 2 * (5 - vga_idx);90 break;91 case 1:92 rx_pwr_all = 8 - 2 * vga_idx;93 break;94 case 0:95 rx_pwr_all = 14 - 2 * vga_idx;96 break;97 default:98 rx_pwr_all = 0;99 break;100 }101 rx_pwr_all += 16;102 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);103 104 if (!cck_highpwr) {105 if (pwdb_all >= 80)106 pwdb_all = ((pwdb_all - 80) << 1) +107 ((pwdb_all - 80) >> 1) + 80;108 else if ((pwdb_all <= 78) && (pwdb_all >= 20))109 pwdb_all += 3;110 if (pwdb_all > 100)111 pwdb_all = 100;112 }113 114 pstatus->rx_pwdb_all = pwdb_all;115 pstatus->bt_rx_rssi_percentage = pwdb_all;116 pstatus->recvsignalpower = rx_pwr_all;117 118 /* (3) Get Signal Quality (EVM) */119 if (bpacket_match_bssid) {120 u8 sq, sq_rpt;121 122 if (pstatus->rx_pwdb_all > 40) {123 sq = 100;124 } else {125 sq_rpt = p_phystrpt->cck_sig_qual_ofdm_pwdb_all;126 if (sq_rpt > 64)127 sq = 0;128 else if (sq_rpt < 20)129 sq = 100;130 else131 sq = ((64 - sq_rpt) * 100) / 44;132 }133 134 pstatus->signalquality = sq;135 pstatus->rx_mimo_signalquality[0] = sq;136 pstatus->rx_mimo_signalquality[1] = -1;137 }138 } else {139 /* (1)Get RSSI for HT rate */140 for (i = RF90_PATH_A; i < RF6052_MAX_PATH; i++) {141 /* we will judge RF RX path now. */142 if (rtlpriv->dm.rfpath_rxenable[i])143 rf_rx_num++;144 145 rx_pwr[i] = ((p_phystrpt->path_agc[i].gain & 0x3f) * 2)146 - 110;147 148 pstatus->rx_pwr[i] = rx_pwr[i];149 /* Translate DBM to percentage. */150 rssi = rtl_query_rxpwrpercentage(rx_pwr[i]);151 total_rssi += rssi;152 153 pstatus->rx_mimo_signalstrength[i] = (u8)rssi;154 }155 156 /* (2)PWDB, Average PWDB calculated by157 * hardware (for rate adaptive)158 */159 rx_pwr_all = ((p_phystrpt->cck_sig_qual_ofdm_pwdb_all >> 1)160 & 0x7f) - 110;161 162 pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);163 pstatus->rx_pwdb_all = pwdb_all;164 pstatus->bt_rx_rssi_percentage = pwdb_all;165 pstatus->rxpower = rx_pwr_all;166 pstatus->recvsignalpower = rx_pwr_all;167 168 /* (3)EVM of HT rate */169 if (pstatus->rate >= DESC_RATEMCS8 &&170 pstatus->rate <= DESC_RATEMCS15)171 max_spatial_stream = 2;172 else173 max_spatial_stream = 1;174 175 for (i = 0; i < max_spatial_stream; i++) {176 evm = rtl_evm_db_to_percentage(177 p_phystrpt->stream_rxevm[i]);178 179 if (bpacket_match_bssid) {180 /* Fill value in RFD, Get the first181 * spatial stream only182 */183 if (i == 0)184 pstatus->signalquality = (u8)(evm &185 0xff);186 pstatus->rx_mimo_signalquality[i] = (u8)(evm &187 0xff);188 }189 }190 191 if (bpacket_match_bssid) {192 for (i = RF90_PATH_A; i <= RF90_PATH_B; i++)193 rtl_priv(hw)->dm.cfo_tail[i] =194 (int)p_phystrpt->path_cfotail[i];195 196 if (rtl_priv(hw)->dm.packet_count == 0xffffffff)197 rtl_priv(hw)->dm.packet_count = 0;198 else199 rtl_priv(hw)->dm.packet_count++;200 }201 }202 203 /* UI BSS List signal strength(in percentage),204 * make it good looking, from 0~100.205 */206 if (is_cck)207 pstatus->signalstrength = (u8)(rtl_signal_scale_mapping(hw,208 pwdb_all));209 else if (rf_rx_num != 0)210 pstatus->signalstrength = (u8)(rtl_signal_scale_mapping(hw,211 total_rssi /= rf_rx_num));212}213 214static void _rtl92ee_translate_rx_signal_stuff(struct ieee80211_hw *hw,215 struct sk_buff *skb,216 struct rtl_stats *pstatus,217 u8 *pdesc,218 struct rx_fwinfo *p_drvinfo)219{220 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));221 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));222 struct ieee80211_hdr *hdr;223 u8 *tmp_buf;224 u8 *praddr;225 u8 *psaddr;226 __le16 fc;227 bool packet_matchbssid, packet_toself, packet_beacon;228 229 tmp_buf = skb->data + pstatus->rx_drvinfo_size +230 pstatus->rx_bufshift + 24;231 232 hdr = (struct ieee80211_hdr *)tmp_buf;233 fc = hdr->frame_control;234 praddr = hdr->addr1;235 psaddr = ieee80211_get_SA(hdr);236 ether_addr_copy(pstatus->psaddr, psaddr);237 238 packet_matchbssid = (!ieee80211_is_ctl(fc) &&239 (ether_addr_equal(mac->bssid,240 ieee80211_has_tods(fc) ?241 hdr->addr1 :242 ieee80211_has_fromds(fc) ?243 hdr->addr2 : hdr->addr3)) &&244 (!pstatus->hwerror) && (!pstatus->crc) &&245 (!pstatus->icv));246 247 packet_toself = packet_matchbssid &&248 (ether_addr_equal(praddr, rtlefuse->dev_addr));249 250 if (ieee80211_is_beacon(fc))251 packet_beacon = true;252 else253 packet_beacon = false;254 255 if (packet_beacon && packet_matchbssid)256 rtl_priv(hw)->dm.dbginfo.num_qry_beacon_pkt++;257 258 if (packet_matchbssid && ieee80211_is_data_qos(hdr->frame_control) &&259 !is_multicast_ether_addr(ieee80211_get_DA(hdr))) {260 struct ieee80211_qos_hdr *hdr_qos =261 (struct ieee80211_qos_hdr *)tmp_buf;262 u16 tid = le16_to_cpu(hdr_qos->qos_ctrl) & 0xf;263 264 if (tid != 0 && tid != 3)265 rtl_priv(hw)->dm.dbginfo.num_non_be_pkt++;266 }267 268 _rtl92ee_query_rxphystatus(hw, pstatus, pdesc, p_drvinfo,269 packet_matchbssid, packet_toself,270 packet_beacon);271 rtl_process_phyinfo(hw, tmp_buf, pstatus);272}273 274static void _rtl92ee_insert_emcontent(struct rtl_tcb_desc *ptcb_desc,275 u8 *virtualaddress8)276{277 u32 dwtmp;278 __le32 *virtualaddress = (__le32 *)virtualaddress8;279 280 memset(virtualaddress, 0, 8);281 282 set_earlymode_pktnum(virtualaddress, ptcb_desc->empkt_num);283 if (ptcb_desc->empkt_num == 1) {284 dwtmp = ptcb_desc->empkt_len[0];285 } else {286 dwtmp = ptcb_desc->empkt_len[0];287 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;288 dwtmp += ptcb_desc->empkt_len[1];289 }290 set_earlymode_len0(virtualaddress, dwtmp);291 292 if (ptcb_desc->empkt_num <= 3) {293 dwtmp = ptcb_desc->empkt_len[2];294 } else {295 dwtmp = ptcb_desc->empkt_len[2];296 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;297 dwtmp += ptcb_desc->empkt_len[3];298 }299 set_earlymode_len1(virtualaddress, dwtmp);300 if (ptcb_desc->empkt_num <= 5) {301 dwtmp = ptcb_desc->empkt_len[4];302 } else {303 dwtmp = ptcb_desc->empkt_len[4];304 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;305 dwtmp += ptcb_desc->empkt_len[5];306 }307 set_earlymode_len2_1(virtualaddress, dwtmp & 0xF);308 set_earlymode_len2_2(virtualaddress, dwtmp >> 4);309 if (ptcb_desc->empkt_num <= 7) {310 dwtmp = ptcb_desc->empkt_len[6];311 } else {312 dwtmp = ptcb_desc->empkt_len[6];313 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;314 dwtmp += ptcb_desc->empkt_len[7];315 }316 set_earlymode_len3(virtualaddress, dwtmp);317 if (ptcb_desc->empkt_num <= 9) {318 dwtmp = ptcb_desc->empkt_len[8];319 } else {320 dwtmp = ptcb_desc->empkt_len[8];321 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;322 dwtmp += ptcb_desc->empkt_len[9];323 }324 set_earlymode_len4(virtualaddress, dwtmp);325}326 327bool rtl92ee_rx_query_desc(struct ieee80211_hw *hw,328 struct rtl_stats *status,329 struct ieee80211_rx_status *rx_status,330 u8 *pdesc8, struct sk_buff *skb)331{332 struct rtl_priv *rtlpriv = rtl_priv(hw);333 struct rx_fwinfo *p_drvinfo;334 struct ieee80211_hdr *hdr;335 __le32 *pdesc = (__le32 *)pdesc8;336 u32 phystatus = get_rx_desc_physt(pdesc);337 u8 wake_match;338 339 if (get_rx_status_desc_rpt_sel(pdesc) == 0)340 status->packet_report_type = NORMAL_RX;341 else342 status->packet_report_type = C2H_PACKET;343 status->length = (u16)get_rx_desc_pkt_len(pdesc);344 status->rx_drvinfo_size = (u8)get_rx_desc_drv_info_size(pdesc) *345 RX_DRV_INFO_SIZE_UNIT;346 status->rx_bufshift = (u8)(get_rx_desc_shift(pdesc) & 0x03);347 status->icv = (u16)get_rx_desc_icv(pdesc);348 status->crc = (u16)get_rx_desc_crc32(pdesc);349 status->hwerror = (status->crc | status->icv);350 status->decrypted = !get_rx_desc_swdec(pdesc);351 status->rate = (u8)get_rx_desc_rxmcs(pdesc);352 status->isampdu = (bool)(get_rx_desc_paggr(pdesc) == 1);353 status->timestamp_low = get_rx_desc_tsfl(pdesc);354 status->is_cck = RTL92EE_RX_HAL_IS_CCK_RATE(status->rate);355 356 status->macid = get_rx_desc_macid(pdesc);357 if (get_rx_status_desc_pattern_match(pdesc))358 wake_match = BIT(2);359 else if (get_rx_status_desc_magic_match(pdesc))360 wake_match = BIT(1);361 else if (get_rx_status_desc_unicast_match(pdesc))362 wake_match = BIT(0);363 else364 wake_match = 0;365 if (wake_match)366 rtl_dbg(rtlpriv, COMP_RXDESC, DBG_LOUD,367 "GGGGGGGGGGGGGet Wakeup Packet!! WakeMatch=%d\n",368 wake_match);369 rx_status->freq = hw->conf.chandef.chan->center_freq;370 rx_status->band = hw->conf.chandef.chan->band;371 372 hdr = (struct ieee80211_hdr *)(skb->data + status->rx_drvinfo_size +373 status->rx_bufshift + 24);374 375 if (status->crc)376 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;377 378 if (status->rx_is40mhzpacket)379 rx_status->bw = RATE_INFO_BW_40;380 381 if (status->is_ht)382 rx_status->encoding = RX_ENC_HT;383 384 rx_status->flag |= RX_FLAG_MACTIME_START;385 386 /* hw will set status->decrypted true, if it finds the387 * frame is open data frame or mgmt frame.388 * So hw will not decryption robust managment frame389 * for IEEE80211w but still set status->decrypted390 * true, so here we should set it back to undecrypted391 * for IEEE80211w frame, and mac80211 sw will help392 * to decrypt it393 */394 if (status->decrypted) {395 if ((!_ieee80211_is_robust_mgmt_frame(hdr)) &&396 (ieee80211_has_protected(hdr->frame_control)))397 rx_status->flag |= RX_FLAG_DECRYPTED;398 else399 rx_status->flag &= ~RX_FLAG_DECRYPTED;400 }401 402 /* rate_idx: index of data rate into band's403 * supported rates or MCS index if HT rates404 * are use (RX_FLAG_HT)405 * Notice: this is diff with windows define406 */407 rx_status->rate_idx = rtlwifi_rate_mapping(hw, status->is_ht,408 false, status->rate);409 410 rx_status->mactime = status->timestamp_low;411 if (phystatus) {412 p_drvinfo = (struct rx_fwinfo *)(skb->data +413 status->rx_bufshift + 24);414 415 _rtl92ee_translate_rx_signal_stuff(hw, skb, status, pdesc8,416 p_drvinfo);417 }418 rx_status->signal = status->recvsignalpower + 10;419 if (status->packet_report_type == TX_REPORT2) {420 status->macid_valid_entry[0] =421 get_rx_rpt2_desc_macid_valid_1(pdesc);422 status->macid_valid_entry[1] =423 get_rx_rpt2_desc_macid_valid_2(pdesc);424 }425 return true;426}427 428/*in Windows, this == Rx_92EE_Interrupt*/429void rtl92ee_rx_check_dma_ok(struct ieee80211_hw *hw, u8 *header_desc8,430 u8 queue_index)431{432 u8 first_seg = 0;433 u8 last_seg = 0;434 u16 total_len = 0;435 u16 read_cnt = 0;436 __le32 *header_desc = (__le32 *)header_desc8;437 438 if (header_desc == NULL)439 return;440 441 total_len = (u16)get_rx_buffer_desc_total_length(header_desc);442 443 first_seg = (u8)get_rx_buffer_desc_fs(header_desc);444 445 last_seg = (u8)get_rx_buffer_desc_ls(header_desc);446 447 while (total_len == 0 && first_seg == 0 && last_seg == 0) {448 read_cnt++;449 total_len = (u16)get_rx_buffer_desc_total_length(header_desc);450 first_seg = (u8)get_rx_buffer_desc_fs(header_desc);451 last_seg = (u8)get_rx_buffer_desc_ls(header_desc);452 453 if (read_cnt > 20)454 break;455 }456}457 458u16 rtl92ee_rx_desc_buff_remained_cnt(struct ieee80211_hw *hw, u8 queue_index)459{460 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));461 struct rtl_priv *rtlpriv = rtl_priv(hw);462 u16 read_point, write_point, remind_cnt;463 u32 tmp_4byte;464 static bool start_rx;465 466 tmp_4byte = rtl_read_dword(rtlpriv, REG_RXQ_TXBD_IDX);467 read_point = (u16)((tmp_4byte>>16) & 0x7ff);468 write_point = (u16)(tmp_4byte & 0x7ff);469 470 if (write_point != rtlpci->rx_ring[queue_index].next_rx_rp) {471 rtl_dbg(rtlpriv, COMP_RXDESC, DBG_DMESG,472 "!!!write point is 0x%x, reg 0x3B4 value is 0x%x\n",473 write_point, tmp_4byte);474 tmp_4byte = rtl_read_dword(rtlpriv, REG_RXQ_TXBD_IDX);475 read_point = (u16)((tmp_4byte>>16) & 0x7ff);476 write_point = (u16)(tmp_4byte & 0x7ff);477 }478 479 if (read_point > 0)480 start_rx = true;481 if (!start_rx)482 return 0;483 484 remind_cnt = calc_fifo_space(read_point, write_point,485 RTL_PCI_MAX_RX_COUNT);486 487 if (remind_cnt == 0)488 return 0;489 490 rtlpci->rx_ring[queue_index].next_rx_rp = write_point;491 492 return remind_cnt;493}494 495static u16 get_desc_addr_fr_q_idx(u16 queue_index)496{497 u16 desc_address;498 499 switch (queue_index) {500 case BK_QUEUE:501 desc_address = REG_BKQ_TXBD_IDX;502 break;503 case BE_QUEUE:504 desc_address = REG_BEQ_TXBD_IDX;505 break;506 case VI_QUEUE:507 desc_address = REG_VIQ_TXBD_IDX;508 break;509 case VO_QUEUE:510 desc_address = REG_VOQ_TXBD_IDX;511 break;512 case BEACON_QUEUE:513 desc_address = REG_BEQ_TXBD_IDX;514 break;515 case TXCMD_QUEUE:516 desc_address = REG_BEQ_TXBD_IDX;517 break;518 case MGNT_QUEUE:519 desc_address = REG_MGQ_TXBD_IDX;520 break;521 case HIGH_QUEUE:522 desc_address = REG_HI0Q_TXBD_IDX;523 break;524 case HCCA_QUEUE:525 desc_address = REG_BEQ_TXBD_IDX;526 break;527 default:528 desc_address = REG_BEQ_TXBD_IDX;529 break;530 }531 return desc_address;532}533 534u16 rtl92ee_get_available_desc(struct ieee80211_hw *hw, u8 q_idx)535{536 struct rtl_priv *rtlpriv = rtl_priv(hw);537 u16 point_diff = 0;538 u16 current_tx_read_point, current_tx_write_point;539 u32 tmp_4byte;540 541 tmp_4byte = rtl_read_dword(rtlpriv,542 get_desc_addr_fr_q_idx(q_idx));543 current_tx_read_point = (u16)((tmp_4byte >> 16) & 0x0fff);544 current_tx_write_point = (u16)((tmp_4byte) & 0x0fff);545 546 point_diff = calc_fifo_space(current_tx_read_point,547 current_tx_write_point,548 TX_DESC_NUM_92E);549 550 return point_diff;551}552 553static void rtl92ee_pre_fill_tx_bd_desc(struct ieee80211_hw *hw,554 u8 *tx_bd_desc8, u8 *desc8,555 u8 queue_index,556 struct sk_buff *skb,557 dma_addr_t addr)558{559 struct rtl_priv *rtlpriv = rtl_priv(hw);560 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));561 u32 pkt_len = skb->len;562 u16 desc_size = 40; /*tx desc size*/563 u32 psblen = 0;564 u16 tx_page_size;565 u32 total_packet_size;566 u16 current_bd_desc;567 u8 i;568 u16 real_desc_size = 0x28;569 u16 append_early_mode_size = 0;570 u8 segmentnum = 1 << (RTL8192EE_SEG_NUM + 1);571 dma_addr_t desc_dma_addr;572 bool dma64 = rtlpriv->cfg->mod_params->dma64;573 __le32 *desc = (__le32 *)desc8;574 __le32 *tx_bd_desc = (__le32 *)tx_bd_desc8;575 576 tx_page_size = 2;577 current_bd_desc = rtlpci->tx_ring[queue_index].cur_tx_wp;578 579 total_packet_size = desc_size+pkt_len;580 581 if (rtlpriv->rtlhal.earlymode_enable) {582 if (queue_index < BEACON_QUEUE) {583 append_early_mode_size = 8;584 total_packet_size += append_early_mode_size;585 }586 }587 588 if (tx_page_size > 0) {589 psblen = (pkt_len + real_desc_size + append_early_mode_size) /590 (tx_page_size * 128);591 592 if (psblen * (tx_page_size * 128) < total_packet_size)593 psblen += 1;594 }595 596 /* tx desc addr */597 desc_dma_addr = rtlpci->tx_ring[queue_index].dma +598 (current_bd_desc * TX_DESC_SIZE);599 600 /* Reset */601 set_tx_buff_desc_len_0(tx_bd_desc, 0);602 set_tx_buff_desc_psb(tx_bd_desc, 0);603 set_tx_buff_desc_own(tx_bd_desc, 0);604 605 for (i = 1; i < segmentnum; i++) {606 set_txbuffer_desc_len_with_offset(tx_bd_desc, i, 0);607 set_txbuffer_desc_amsdu_with_offset(tx_bd_desc, i, 0);608 set_txbuffer_desc_add_low_with_offset(tx_bd_desc, i, 0);609 set_txbuffer_desc_add_high_with_offset(tx_bd_desc, i, 0, dma64);610 }611 612 /* Clear all status */613 clear_pci_tx_desc_content(desc, TX_DESC_SIZE);614 615 if (rtlpriv->rtlhal.earlymode_enable) {616 if (queue_index < BEACON_QUEUE) {617 /* This if needs braces */618 set_tx_buff_desc_len_0(tx_bd_desc, desc_size + 8);619 } else {620 set_tx_buff_desc_len_0(tx_bd_desc, desc_size);621 }622 } else {623 set_tx_buff_desc_len_0(tx_bd_desc, desc_size);624 }625 set_tx_buff_desc_psb(tx_bd_desc, psblen);626 set_tx_buff_desc_addr_low_0(tx_bd_desc, desc_dma_addr);627 set_tx_buff_desc_addr_high_0(tx_bd_desc, ((u64)desc_dma_addr >> 32),628 dma64);629 630 set_txbuffer_desc_len_with_offset(tx_bd_desc, 1, pkt_len);631 /* don't using extendsion mode. */632 set_txbuffer_desc_amsdu_with_offset(tx_bd_desc, 1, 0);633 set_txbuffer_desc_add_low_with_offset(tx_bd_desc, 1, addr);634 set_txbuffer_desc_add_high_with_offset(tx_bd_desc, 1,635 ((u64)addr >> 32), dma64);636 637 set_tx_desc_pkt_size(desc, (u16)(pkt_len));638 set_tx_desc_tx_buffer_size(desc, (u16)(pkt_len));639}640 641void rtl92ee_tx_fill_desc(struct ieee80211_hw *hw,642 struct ieee80211_hdr *hdr, u8 *pdesc8,643 u8 *pbd_desc_tx,644 struct ieee80211_tx_info *info,645 struct ieee80211_sta *sta,646 struct sk_buff *skb,647 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc)648{649 struct rtl_priv *rtlpriv = rtl_priv(hw);650 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));651 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));652 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);653 struct rtlwifi_tx_info *tx_info = rtl_tx_skb_cb_info(skb);654 u16 seq_number;655 __le16 fc = hdr->frame_control;656 u8 fw_qsel = _rtl92ee_map_hwqueue_to_fwqueue(skb, hw_queue);657 bool firstseg = ((hdr->seq_ctrl &658 cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0);659 bool lastseg = ((hdr->frame_control &660 cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0);661 dma_addr_t mapping;662 u8 bw_40 = 0;663 __le32 *pdesc = (__le32 *)pdesc8;664 665 if (mac->opmode == NL80211_IFTYPE_STATION) {666 bw_40 = mac->bw_40;667 } else if (mac->opmode == NL80211_IFTYPE_AP ||668 mac->opmode == NL80211_IFTYPE_ADHOC) {669 if (sta)670 bw_40 = sta->deflink.ht_cap.cap &671 IEEE80211_HT_CAP_SUP_WIDTH_20_40;672 }673 seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;674 rtl_get_tcb_desc(hw, info, sta, skb, ptcb_desc);675 /* reserve 8 byte for AMPDU early mode */676 if (rtlhal->earlymode_enable) {677 skb_push(skb, EM_HDR_LEN);678 memset(skb->data, 0, EM_HDR_LEN);679 }680 mapping = dma_map_single(&rtlpci->pdev->dev, skb->data, skb->len,681 DMA_TO_DEVICE);682 if (dma_mapping_error(&rtlpci->pdev->dev, mapping)) {683 rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE,684 "DMA mapping error\n");685 return;686 }687 688 if (pbd_desc_tx != NULL)689 rtl92ee_pre_fill_tx_bd_desc(hw, pbd_desc_tx, pdesc8, hw_queue,690 skb, mapping);691 692 if (ieee80211_is_nullfunc(fc) || ieee80211_is_ctl(fc)) {693 firstseg = true;694 lastseg = true;695 }696 if (firstseg) {697 if (rtlhal->earlymode_enable) {698 set_tx_desc_pkt_offset(pdesc, 1);699 set_tx_desc_offset(pdesc,700 USB_HWDESC_HEADER_LEN + EM_HDR_LEN);701 if (ptcb_desc->empkt_num) {702 rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE,703 "Insert 8 byte.pTcb->EMPktNum:%d\n",704 ptcb_desc->empkt_num);705 _rtl92ee_insert_emcontent(ptcb_desc,706 (u8 *)(skb->data));707 }708 } else {709 set_tx_desc_offset(pdesc, USB_HWDESC_HEADER_LEN);710 }711 712 713 set_tx_desc_tx_rate(pdesc, ptcb_desc->hw_rate);714 715 if (ieee80211_is_mgmt(fc)) {716 ptcb_desc->use_driver_rate = true;717 } else {718 if (rtlpriv->ra.is_special_data) {719 ptcb_desc->use_driver_rate = true;720 set_tx_desc_tx_rate(pdesc, DESC_RATE11M);721 } else {722 ptcb_desc->use_driver_rate = false;723 }724 }725 726 if (info->flags & IEEE80211_TX_CTL_AMPDU) {727 set_tx_desc_agg_enable(pdesc, 1);728 set_tx_desc_max_agg_num(pdesc, 0x14);729 }730 set_tx_desc_seq(pdesc, seq_number);731 set_tx_desc_rts_enable(pdesc,732 ((ptcb_desc->rts_enable &&733 !ptcb_desc->cts_enable) ? 1 : 0));734 set_tx_desc_hw_rts_enable(pdesc, 0);735 set_tx_desc_cts2self(pdesc,736 ((ptcb_desc->cts_enable) ? 1 : 0));737 738 set_tx_desc_rts_rate(pdesc, ptcb_desc->rts_rate);739 set_tx_desc_rts_sc(pdesc, ptcb_desc->rts_sc);740 set_tx_desc_rts_short(pdesc,741 ((ptcb_desc->rts_rate <= DESC_RATE54M) ?742 (ptcb_desc->rts_use_shortpreamble ? 1 : 0) :743 (ptcb_desc->rts_use_shortgi ? 1 : 0)));744 745 if (ptcb_desc->tx_enable_sw_calc_duration)746 set_tx_desc_nav_use_hdr(pdesc, 1);747 748 if (bw_40) {749 if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_20_40) {750 set_tx_desc_data_bw(pdesc, 1);751 set_tx_desc_tx_sub_carrier(pdesc, 3);752 } else {753 set_tx_desc_data_bw(pdesc, 0);754 set_tx_desc_tx_sub_carrier(pdesc,755 mac->cur_40_prime_sc);756 }757 } else {758 set_tx_desc_data_bw(pdesc, 0);759 set_tx_desc_tx_sub_carrier(pdesc, 0);760 }761 762 set_tx_desc_linip(pdesc, 0);763 if (sta) {764 u8 ampdu_density = sta->deflink.ht_cap.ampdu_density;765 766 set_tx_desc_ampdu_density(pdesc, ampdu_density);767 }768 if (info->control.hw_key) {769 struct ieee80211_key_conf *key = info->control.hw_key;770 771 switch (key->cipher) {772 case WLAN_CIPHER_SUITE_WEP40:773 case WLAN_CIPHER_SUITE_WEP104:774 case WLAN_CIPHER_SUITE_TKIP:775 set_tx_desc_sec_type(pdesc, 0x1);776 break;777 case WLAN_CIPHER_SUITE_CCMP:778 set_tx_desc_sec_type(pdesc, 0x3);779 break;780 default:781 set_tx_desc_sec_type(pdesc, 0x0);782 break;783 }784 }785 786 set_tx_desc_queue_sel(pdesc, fw_qsel);787 set_tx_desc_data_rate_fb_limit(pdesc, 0x1F);788 set_tx_desc_rts_rate_fb_limit(pdesc, 0xF);789 set_tx_desc_disable_fb(pdesc,790 ptcb_desc->disable_ratefallback ? 1 : 0);791 set_tx_desc_use_rate(pdesc, ptcb_desc->use_driver_rate ? 1 : 0);792 793 /*set_tx_desc_pwr_status(pdesc, pwr_status);*/794 /* Set TxRate and RTSRate in TxDesc */795 /* This prevent Tx initial rate of new-coming packets */796 /* from being overwritten by retried packet rate.*/797 if (!ptcb_desc->use_driver_rate) {798 /*set_tx_desc_rts_rate(pdesc, 0x08); */799 /* set_tx_desc_tx_rate(pdesc, 0x0b); */800 }801 if (ieee80211_is_data_qos(fc)) {802 if (mac->rdg_en) {803 rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE,804 "Enable RDG function.\n");805 set_tx_desc_rdg_enable(pdesc, 1);806 set_tx_desc_htc(pdesc, 1);807 }808 }809 /* tx report */810 rtl_set_tx_report(ptcb_desc, pdesc8, hw, tx_info);811 }812 813 set_tx_desc_first_seg(pdesc, (firstseg ? 1 : 0));814 set_tx_desc_last_seg(pdesc, (lastseg ? 1 : 0));815 set_tx_desc_tx_buffer_address(pdesc, mapping);816 if (rtlpriv->dm.useramask) {817 set_tx_desc_rate_id(pdesc, ptcb_desc->ratr_index);818 set_tx_desc_macid(pdesc, ptcb_desc->mac_id);819 } else {820 set_tx_desc_rate_id(pdesc, 0xC + ptcb_desc->ratr_index);821 set_tx_desc_macid(pdesc, ptcb_desc->ratr_index);822 }823 824 set_tx_desc_more_frag(pdesc, (lastseg ? 0 : 1));825 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||826 is_broadcast_ether_addr(ieee80211_get_DA(hdr))) {827 set_tx_desc_bmc(pdesc, 1);828 }829 rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE, "\n");830}831 832void rtl92ee_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc8,833 struct sk_buff *skb)834{835 struct rtl_priv *rtlpriv = rtl_priv(hw);836 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));837 u8 fw_queue = QSLT_BEACON;838 dma_addr_t mapping = dma_map_single(&rtlpci->pdev->dev, skb->data,839 skb->len, DMA_TO_DEVICE);840 u8 txdesc_len = 40;841 __le32 *pdesc = (__le32 *)pdesc8;842 843 if (dma_mapping_error(&rtlpci->pdev->dev, mapping)) {844 rtl_dbg(rtlpriv, COMP_SEND, DBG_TRACE,845 "DMA mapping error\n");846 return;847 }848 clear_pci_tx_desc_content(pdesc, txdesc_len);849 850 set_tx_desc_offset(pdesc, txdesc_len);851 852 set_tx_desc_tx_rate(pdesc, DESC_RATE1M);853 854 set_tx_desc_seq(pdesc, 0);855 856 set_tx_desc_linip(pdesc, 0);857 858 set_tx_desc_queue_sel(pdesc, fw_queue);859 860 set_tx_desc_first_seg(pdesc, 1);861 set_tx_desc_last_seg(pdesc, 1);862 863 set_tx_desc_tx_buffer_size(pdesc, (u16)(skb->len));864 865 set_tx_desc_tx_buffer_address(pdesc, mapping);866 867 set_tx_desc_rate_id(pdesc, 7);868 set_tx_desc_macid(pdesc, 0);869 870 set_tx_desc_own(pdesc, 1);871 872 set_tx_desc_pkt_size(pdesc, (u16)(skb->len));873 874 set_tx_desc_first_seg(pdesc, 1);875 set_tx_desc_last_seg(pdesc, 1);876 877 set_tx_desc_offset(pdesc, 40);878 879 set_tx_desc_use_rate(pdesc, 1);880 881 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,882 "H2C Tx Cmd Content\n", pdesc, txdesc_len);883}884 885void rtl92ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc8, bool istx,886 u8 desc_name, u8 *val)887{888 struct rtl_priv *rtlpriv = rtl_priv(hw);889 u8 q_idx = *val;890 bool dma64 = rtlpriv->cfg->mod_params->dma64;891 __le32 *pdesc = (__le32 *)pdesc8;892 893 if (istx) {894 switch (desc_name) {895 case HW_DESC_TX_NEXTDESC_ADDR:896 set_tx_desc_next_desc_address(pdesc, *(u32 *)val);897 break;898 case HW_DESC_OWN:{899 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));900 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[q_idx];901 u16 max_tx_desc = ring->entries;902 903 if (q_idx == BEACON_QUEUE) {904 ring->cur_tx_wp = 0;905 ring->cur_tx_rp = 0;906 set_tx_buff_desc_own(pdesc, 1);907 return;908 }909 910 /* make sure tx desc is available by caller */911 ring->cur_tx_wp = ((ring->cur_tx_wp + 1) % max_tx_desc);912 913 rtl_write_word(rtlpriv,914 get_desc_addr_fr_q_idx(q_idx),915 ring->cur_tx_wp);916 }917 break;918 }919 } else {920 switch (desc_name) {921 case HW_DESC_RX_PREPARE:922 set_rx_buffer_desc_ls(pdesc, 0);923 set_rx_buffer_desc_fs(pdesc, 0);924 set_rx_buffer_desc_total_length(pdesc, 0);925 926 set_rx_buffer_desc_data_length(pdesc,927 MAX_RECEIVE_BUFFER_SIZE +928 RX_DESC_SIZE);929 930 set_rx_buffer_physical_low(pdesc, (*(dma_addr_t *)val) &931 DMA_BIT_MASK(32));932 set_rx_buffer_physical_high(pdesc,933 ((u64)(*(dma_addr_t *)val)934 >> 32),935 dma64);936 break;937 case HW_DESC_RXERO:938 set_rx_desc_eor(pdesc, 1);939 break;940 default:941 WARN_ONCE(true,942 "rtl8192ee: ERR rxdesc :%d not processed\n",943 desc_name);944 break;945 }946 }947}948 949u64 rtl92ee_get_desc(struct ieee80211_hw *hw,950 u8 *pdesc8, bool istx, u8 desc_name)951{952 struct rtl_priv *rtlpriv = rtl_priv(hw);953 u64 ret = 0;954 bool dma64 = rtlpriv->cfg->mod_params->dma64;955 __le32 *pdesc = (__le32 *)pdesc8;956 957 if (istx) {958 switch (desc_name) {959 case HW_DESC_OWN:960 ret = get_tx_desc_own(pdesc);961 break;962 case HW_DESC_TXBUFF_ADDR:963 ret = get_txbuffer_desc_addr_low(pdesc, 1);964 ret |= (u64)get_txbuffer_desc_addr_high(pdesc, 1,965 dma64) << 32;966 break;967 default:968 WARN_ONCE(true,969 "rtl8192ee: ERR txdesc :%d not processed\n",970 desc_name);971 break;972 }973 } else {974 switch (desc_name) {975 case HW_DESC_OWN:976 ret = get_rx_desc_own(pdesc);977 break;978 case HW_DESC_RXPKT_LEN:979 ret = get_rx_desc_pkt_len(pdesc);980 break;981 case HW_DESC_RXBUFF_ADDR:982 ret = get_rx_desc_buff_addr(pdesc);983 break;984 default:985 WARN_ONCE(true,986 "rtl8192ee: ERR rxdesc :%d not processed\n",987 desc_name);988 break;989 }990 }991 return ret;992}993 994bool rtl92ee_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue, u16 index)995{996 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));997 struct rtl_priv *rtlpriv = rtl_priv(hw);998 u16 read_point, write_point;999 bool ret = false;1000 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];1001 1002 {1003 u16 cur_tx_rp;1004 u32 tmpu32;1005 1006 tmpu32 =1007 rtl_read_dword(rtlpriv,1008 get_desc_addr_fr_q_idx(hw_queue));1009 cur_tx_rp = (u16)((tmpu32 >> 16) & 0x0fff);1010 1011 /* don't need to update ring->cur_tx_wp */1012 ring->cur_tx_rp = cur_tx_rp;1013 }1014 1015 read_point = ring->cur_tx_rp;1016 write_point = ring->cur_tx_wp;1017 1018 if (write_point > read_point) {1019 if (index < write_point && index >= read_point)1020 ret = false;1021 else1022 ret = true;1023 } else if (write_point < read_point) {1024 if (index > write_point && index < read_point)1025 ret = true;1026 else1027 ret = false;1028 } else {1029 if (index != read_point)1030 ret = true;1031 }1032 1033 if (hw_queue == BEACON_QUEUE)1034 ret = true;1035 1036 if (rtlpriv->rtlhal.driver_is_goingto_unload ||1037 rtlpriv->psc.rfoff_reason > RF_CHANGE_BY_PS)1038 ret = true;1039 1040 return ret;1041}1042 1043void rtl92ee_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)1044{1045}1046