418 lines · c
1// SPDX-License-Identifier: GPL-2.02/* Copyright(c) 2009-2012 Realtek Corporation.*/3 4#include "../wifi.h"5#include "../core.h"6#include "../base.h"7#include "../pci.h"8#include "reg.h"9#include "def.h"10#include "phy.h"11#include "dm.h"12#include "fw.h"13#include "hw.h"14#include "trx.h"15#include "led.h"16 17#include <linux/module.h>18 19static void rtl92s_init_aspm_vars(struct ieee80211_hw *hw)20{21 struct rtl_priv *rtlpriv = rtl_priv(hw);22 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));23 24 /* ASPM PS mode.25 * 0 - Disable ASPM,26 * 1 - Enable ASPM without Clock Req,27 * 2 - Enable ASPM with Clock Req,28 * 3 - Alwyas Enable ASPM with Clock Req,29 * 4 - Always Enable ASPM without Clock Req.30 * set default to RTL8192CE:3 RTL8192E:231 * */32 rtlpci->const_pci_aspm = 2;33 34 /*Setting for PCI-E device */35 rtlpci->const_devicepci_aspm_setting = 0x03;36 37 /*Setting for PCI-E bridge */38 rtlpci->const_hostpci_aspm_setting = 0x02;39 40 /* In Hw/Sw Radio Off situation.41 * 0 - Default,42 * 1 - From ASPM setting without low Mac Pwr,43 * 2 - From ASPM setting with low Mac Pwr,44 * 3 - Bus D345 * set default to RTL8192CE:0 RTL8192SE:246 */47 rtlpci->const_hwsw_rfoff_d3 = 2;48 49 /* This setting works for those device with50 * backdoor ASPM setting such as EPHY setting.51 * 0 - Not support ASPM,52 * 1 - Support ASPM,53 * 2 - According to chipset.54 */55 rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;56}57 58static void rtl92se_fw_cb(const struct firmware *firmware, void *context)59{60 struct ieee80211_hw *hw = context;61 struct rtl_priv *rtlpriv = rtl_priv(hw);62 struct rt_firmware *pfirmware = NULL;63 char *fw_name = "rtlwifi/rtl8192sefw.bin";64 65 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,66 "Firmware callback routine entered!\n");67 complete(&rtlpriv->firmware_loading_complete);68 if (!firmware) {69 pr_err("Firmware %s not available\n", fw_name);70 rtlpriv->max_fw_size = 0;71 return;72 }73 if (firmware->size > rtlpriv->max_fw_size) {74 pr_err("Firmware is too big!\n");75 rtlpriv->max_fw_size = 0;76 release_firmware(firmware);77 return;78 }79 pfirmware = (struct rt_firmware *)rtlpriv->rtlhal.pfirmware;80 memcpy(pfirmware->sz_fw_tmpbuffer, firmware->data, firmware->size);81 pfirmware->sz_fw_tmpbufferlen = firmware->size;82 release_firmware(firmware);83}84 85static int rtl92s_init_sw_vars(struct ieee80211_hw *hw)86{87 struct rtl_priv *rtlpriv = rtl_priv(hw);88 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));89 int err = 0;90 u16 earlyrxthreshold = 7;91 char *fw_name = "rtlwifi/rtl8192sefw.bin";92 93 rtlpriv->dm.dm_initialgain_enable = true;94 rtlpriv->dm.dm_flag = 0;95 rtlpriv->dm.disable_framebursting = false;96 rtlpriv->dm.thermalvalue = 0;97 rtlpriv->dm.useramask = true;98 99 /* compatible 5G band 91se just 2.4G band & smsp */100 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;101 rtlpriv->rtlhal.bandset = BAND_ON_2_4G;102 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;103 104 rtlpci->transmit_config = 0;105 106 rtlpci->receive_config =107 RCR_APPFCS |108 RCR_APWRMGT |109 /*RCR_ADD3 |*/110 RCR_AMF |111 RCR_ADF |112 RCR_APP_MIC |113 RCR_APP_ICV |114 RCR_AICV |115 /* Accept ICV error, CRC32 Error */116 RCR_ACRC32 |117 RCR_AB |118 /* Accept Broadcast, Multicast */119 RCR_AM |120 /* Accept Physical match */121 RCR_APM |122 /* Accept Destination Address packets */123 /*RCR_AAP |*/124 RCR_APP_PHYST_STAFF |125 /* Accept PHY status */126 RCR_APP_PHYST_RXFF |127 (earlyrxthreshold << RCR_FIFO_OFFSET);128 129 rtlpci->irq_mask[0] = (u32)130 (IMR_ROK |131 IMR_VODOK |132 IMR_VIDOK |133 IMR_BEDOK |134 IMR_BKDOK |135 IMR_HCCADOK |136 IMR_MGNTDOK |137 IMR_COMDOK |138 IMR_HIGHDOK |139 IMR_BDOK |140 IMR_RXCMDOK |141 /*IMR_TIMEOUT0 |*/142 IMR_RDU |143 IMR_RXFOVW |144 IMR_BCNINT145 /*| IMR_TXFOVW*/146 /*| IMR_TBDOK |147 IMR_TBDER*/);148 149 rtlpci->irq_mask[1] = (u32) 0;150 151 rtlpci->shortretry_limit = 0x30;152 rtlpci->longretry_limit = 0x30;153 154 rtlpci->first_init = true;155 156 /* for LPS & IPS */157 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;158 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;159 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;160 if (!rtlpriv->psc.inactiveps)161 pr_info("Power Save off (module option)\n");162 if (!rtlpriv->psc.fwctrl_lps)163 pr_info("FW Power Save off (module option)\n");164 rtlpriv->psc.reg_fwctrl_lps = 3;165 rtlpriv->psc.reg_max_lps_awakeintvl = 5;166 /* for ASPM, you can close aspm through167 * set const_support_pciaspm = 0 */168 rtl92s_init_aspm_vars(hw);169 170 if (rtlpriv->psc.reg_fwctrl_lps == 1)171 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;172 else if (rtlpriv->psc.reg_fwctrl_lps == 2)173 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;174 else if (rtlpriv->psc.reg_fwctrl_lps == 3)175 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;176 177 /* for firmware buf */178 rtlpriv->rtlhal.pfirmware = vzalloc(sizeof(struct rt_firmware));179 if (!rtlpriv->rtlhal.pfirmware)180 return 1;181 182 rtlpriv->max_fw_size = RTL8190_MAX_FIRMWARE_CODE_SIZE*2 +183 sizeof(struct fw_hdr);184 pr_info("Driver for Realtek RTL8192SE/RTL8191SE\n"185 "Loading firmware %s\n", fw_name);186 /* request fw */187 err = request_firmware_nowait(THIS_MODULE, 1, fw_name,188 rtlpriv->io.dev, GFP_KERNEL, hw,189 rtl92se_fw_cb);190 if (err) {191 pr_err("Failed to request firmware!\n");192 vfree(rtlpriv->rtlhal.pfirmware);193 rtlpriv->rtlhal.pfirmware = NULL;194 return 1;195 }196 197 return err;198}199 200static void rtl92s_deinit_sw_vars(struct ieee80211_hw *hw)201{202 struct rtl_priv *rtlpriv = rtl_priv(hw);203 204 if (rtlpriv->rtlhal.pfirmware) {205 vfree(rtlpriv->rtlhal.pfirmware);206 rtlpriv->rtlhal.pfirmware = NULL;207 }208}209 210static bool rtl92se_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue,211 u16 index)212{213 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));214 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];215 u8 *entry = (u8 *)(&ring->desc[ring->idx]);216 u8 own = (u8)rtl92se_get_desc(hw, entry, true, HW_DESC_OWN);217 218 if (own)219 return false;220 return true;221}222 223static struct rtl_hal_ops rtl8192se_hal_ops = {224 .init_sw_vars = rtl92s_init_sw_vars,225 .deinit_sw_vars = rtl92s_deinit_sw_vars,226 .read_eeprom_info = rtl92se_read_eeprom_info,227 .interrupt_recognized = rtl92se_interrupt_recognized,228 .hw_init = rtl92se_hw_init,229 .hw_disable = rtl92se_card_disable,230 .hw_suspend = rtl92se_suspend,231 .hw_resume = rtl92se_resume,232 .enable_interrupt = rtl92se_enable_interrupt,233 .disable_interrupt = rtl92se_disable_interrupt,234 .set_network_type = rtl92se_set_network_type,235 .set_chk_bssid = rtl92se_set_check_bssid,236 .set_qos = rtl92se_set_qos,237 .set_bcn_reg = rtl92se_set_beacon_related_registers,238 .set_bcn_intv = rtl92se_set_beacon_interval,239 .update_interrupt_mask = rtl92se_update_interrupt_mask,240 .get_hw_reg = rtl92se_get_hw_reg,241 .set_hw_reg = rtl92se_set_hw_reg,242 .update_rate_tbl = rtl92se_update_hal_rate_tbl,243 .fill_tx_desc = rtl92se_tx_fill_desc,244 .fill_tx_cmddesc = rtl92se_tx_fill_cmddesc,245 .query_rx_desc = rtl92se_rx_query_desc,246 .set_channel_access = rtl92se_update_channel_access_setting,247 .radio_onoff_checking = rtl92se_gpio_radio_on_off_checking,248 .set_bw_mode = rtl92s_phy_set_bw_mode,249 .switch_channel = rtl92s_phy_sw_chnl,250 .dm_watchdog = rtl92s_dm_watchdog,251 .scan_operation_backup = rtl92s_phy_scan_operation_backup,252 .set_rf_power_state = rtl92s_phy_set_rf_power_state,253 .led_control = rtl92se_led_control,254 .set_desc = rtl92se_set_desc,255 .get_desc = rtl92se_get_desc,256 .is_tx_desc_closed = rtl92se_is_tx_desc_closed,257 .tx_polling = rtl92se_tx_polling,258 .enable_hw_sec = rtl92se_enable_hw_security_config,259 .set_key = rtl92se_set_key,260 .get_bbreg = rtl92s_phy_query_bb_reg,261 .set_bbreg = rtl92s_phy_set_bb_reg,262 .get_rfreg = rtl92s_phy_query_rf_reg,263 .set_rfreg = rtl92s_phy_set_rf_reg,264 .get_btc_status = rtl_btc_status_false,265};266 267static struct rtl_mod_params rtl92se_mod_params = {268 .sw_crypto = false,269 .inactiveps = true,270 .swctrl_lps = true,271 .fwctrl_lps = false,272 .aspm_support = 2,273 .debug_level = 0,274 .debug_mask = 0,275};276 277/* Because memory R/W bursting will cause system hang/crash278 * for 92se, so we don't read back after every write action */279static const struct rtl_hal_cfg rtl92se_hal_cfg = {280 .bar_id = 1,281 .write_readback = false,282 .name = "rtl92s_pci",283 .ops = &rtl8192se_hal_ops,284 .mod_params = &rtl92se_mod_params,285 286 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,287 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,288 .maps[SYS_CLK] = SYS_CLKR,289 .maps[MAC_RCR_AM] = RCR_AM,290 .maps[MAC_RCR_AB] = RCR_AB,291 .maps[MAC_RCR_ACRC32] = RCR_ACRC32,292 .maps[MAC_RCR_ACF] = RCR_ACF,293 .maps[MAC_RCR_AAP] = RCR_AAP,294 .maps[MAC_HIMR] = INTA_MASK,295 .maps[MAC_HIMRE] = INTA_MASK + 4,296 297 .maps[EFUSE_TEST] = REG_EFUSE_TEST,298 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,299 .maps[EFUSE_CLK] = REG_EFUSE_CLK,300 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,301 .maps[EFUSE_PWC_EV12V] = 0, /* nouse for 8192se */302 .maps[EFUSE_FEN_ELDR] = 0, /* nouse for 8192se */303 .maps[EFUSE_LOADER_CLK_EN] = 0,/* nouse for 8192se */304 .maps[EFUSE_ANA8M] = EFUSE_ANA8M,305 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE_92S,306 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,307 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,308 .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,309 310 .maps[RWCAM] = REG_RWCAM,311 .maps[WCAMI] = REG_WCAMI,312 .maps[RCAMO] = REG_RCAMO,313 .maps[CAMDBG] = REG_CAMDBG,314 .maps[SECR] = REG_SECR,315 .maps[SEC_CAM_NONE] = CAM_NONE,316 .maps[SEC_CAM_WEP40] = CAM_WEP40,317 .maps[SEC_CAM_TKIP] = CAM_TKIP,318 .maps[SEC_CAM_AES] = CAM_AES,319 .maps[SEC_CAM_WEP104] = CAM_WEP104,320 321 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,322 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,323 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,324 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,325 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,326 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,327 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,328 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,329 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,330 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,331 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,332 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,333 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,334 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,335 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,336 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,337 338 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,339 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,340 .maps[RTL_IMR_BCNINT] = IMR_BCNINT,341 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,342 .maps[RTL_IMR_RDU] = IMR_RDU,343 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,344 .maps[RTL_IMR_BDOK] = IMR_BDOK,345 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,346 .maps[RTL_IMR_TBDER] = IMR_TBDER,347 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,348 .maps[RTL_IMR_COMDOK] = IMR_COMDOK,349 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,350 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,351 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,352 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,353 .maps[RTL_IMR_VODOK] = IMR_VODOK,354 .maps[RTL_IMR_ROK] = IMR_ROK,355 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),356 357 .maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M,358 .maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M,359 .maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M,360 .maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M,361 .maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M,362 .maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M,363 .maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M,364 .maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M,365 .maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M,366 .maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M,367 .maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M,368 .maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M,369 370 .maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7,371 .maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15,372};373 374static const struct pci_device_id rtl92se_pci_ids[] = {375 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8192, rtl92se_hal_cfg)},376 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8171, rtl92se_hal_cfg)},377 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8172, rtl92se_hal_cfg)},378 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8173, rtl92se_hal_cfg)},379 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8174, rtl92se_hal_cfg)},380 {},381};382 383MODULE_DEVICE_TABLE(pci, rtl92se_pci_ids);384 385MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");386MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");387MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");388MODULE_LICENSE("GPL");389MODULE_DESCRIPTION("Realtek 8192S/8191S 802.11n PCI wireless");390MODULE_FIRMWARE("rtlwifi/rtl8192sefw.bin");391 392module_param_named(swenc, rtl92se_mod_params.sw_crypto, bool, 0444);393module_param_named(debug_level, rtl92se_mod_params.debug_level, int, 0644);394module_param_named(debug_mask, rtl92se_mod_params.debug_mask, ullong, 0644);395module_param_named(ips, rtl92se_mod_params.inactiveps, bool, 0444);396module_param_named(swlps, rtl92se_mod_params.swctrl_lps, bool, 0444);397module_param_named(fwlps, rtl92se_mod_params.fwctrl_lps, bool, 0444);398module_param_named(aspm, rtl92se_mod_params.aspm_support, int, 0444);399MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");400MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");401MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 1)\n");402MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 0)\n");403MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");404MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");405MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");406 407static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);408 409static struct pci_driver rtl92se_driver = {410 .name = KBUILD_MODNAME,411 .id_table = rtl92se_pci_ids,412 .probe = rtl_pci_probe,413 .remove = rtl_pci_disconnect,414 .driver.pm = &rtlwifi_pm_ops,415};416 417module_pci_driver(rtl92se_driver);418