2099 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright(c) 2009-2012 Realtek Corporation.*/3 4#ifndef __RTL8723E_REG_H__5#define __RTL8723E_REG_H__6 7#define REG_SYS_ISO_CTRL 0x00008#define REG_SYS_FUNC_EN 0x00029#define REG_APS_FSMCO 0x000410#define REG_SYS_CLKR 0x000811#define REG_9346CR 0x000A12#define REG_EE_VPD 0x000C13#define REG_AFE_MISC 0x001014#define REG_SPS0_CTRL 0x001115#define REG_SPS_OCP_CFG 0x001816#define REG_RSV_CTRL 0x001C17#define REG_RF_CTRL 0x001F18#define REG_LDOA15_CTRL 0x002019#define REG_LDOV12D_CTRL 0x002120#define REG_LDOHCI12_CTRL 0x002221#define REG_LPLDO_CTRL 0x002322#define REG_AFE_XTAL_CTRL 0x002423#define REG_AFE_PLL_CTRL 0x002824#define REG_EFUSE_CTRL 0x003025#define REG_EFUSE_TEST 0x003426#define REG_PWR_DATA 0x003827#define REG_CAL_TIMER 0x003C28#define REG_ACLK_MON 0x003E29#define REG_GPIO_MUXCFG 0x004030#define REG_GPIO_IO_SEL 0x004231#define REG_MAC_PINMUX_CFG 0x004332#define REG_GPIO_PIN_CTRL 0x004433#define REG_GPIO_INTM 0x004834#define REG_LEDCFG0 0x004C35#define REG_LEDCFG1 0x004D36#define REG_LEDCFG2 0x004E37#define REG_LEDCFG3 0x004F38#define REG_FSIMR 0x005039#define REG_FSISR 0x005440#define REG_GPIO_PIN_CTRL_2 0x006041#define REG_GPIO_IO_SEL_2 0x006242#define REG_MULTI_FUNC_CTRL 0x006843 44#define REG_MCUFWDL 0x008045 46#define REG_HMEBOX_EXT_0 0x008847#define REG_HMEBOX_EXT_1 0x008A48#define REG_HMEBOX_EXT_2 0x008C49#define REG_HMEBOX_EXT_3 0x008E50 51#define REG_BIST_SCAN 0x00D052#define REG_BIST_RPT 0x00D453#define REG_BIST_ROM_RPT 0x00D854#define REG_USB_SIE_INTF 0x00E055#define REG_PCIE_MIO_INTF 0x00E456#define REG_PCIE_MIO_INTD 0x00E857#define REG_SYS_CFG 0x00F058#define REG_GPIO_OUTSTS 0x00F459 60#define REG_CR 0x010061#define REG_PBP 0x010462#define REG_TRXDMA_CTRL 0x010C63#define REG_TRXFF_BNDY 0x011464#define REG_TRXFF_STATUS 0x011865#define REG_RXFF_PTR 0x011C66#define REG_HIMR 0x012067#define REG_HISR 0x012468#define REG_HIMRE 0x012869#define REG_HISRE 0x012C70#define REG_CPWM 0x012F71#define REG_FWIMR 0x013072#define REG_FWISR 0x013473#define REG_PKTBUF_DBG_CTRL 0x014074#define REG_PKTBUF_DBG_DATA_L 0x014475#define REG_PKTBUF_DBG_DATA_H 0x014876 77#define REG_TC0_CTRL 0x015078#define REG_TC1_CTRL 0x015479#define REG_TC2_CTRL 0x015880#define REG_TC3_CTRL 0x015C81#define REG_TC4_CTRL 0x016082#define REG_TCUNIT_BASE 0x016483#define REG_MBIST_START 0x017484#define REG_MBIST_DONE 0x017885#define REG_MBIST_FAIL 0x017C86#define REG_C2HEVT_MSG_NORMAL 0x01A087#define REG_C2HEVT_MSG_TEST 0x01B888#define REG_MCUTST_1 0x01c089#define REG_FMETHR 0x01C890#define REG_HMETFR 0x01CC91#define REG_HMEBOX_0 0x01D092#define REG_HMEBOX_1 0x01D493#define REG_HMEBOX_2 0x01D894#define REG_HMEBOX_3 0x01DC95 96#define REG_LLT_INIT 0x01E097#define REG_BB_ACCEESS_CTRL 0x01E898#define REG_BB_ACCESS_DATA 0x01EC99 100#define REG_RQPN 0x0200101#define REG_FIFOPAGE 0x0204102#define REG_TDECTRL 0x0208103#define REG_TXDMA_OFFSET_CHK 0x020C104#define REG_TXDMA_STATUS 0x0210105#define REG_RQPN_NPQ 0x0214106 107#define REG_RXDMA_AGG_PG_TH 0x0280108#define REG_RXPKT_NUM 0x0284109#define REG_RXDMA_STATUS 0x0288110 111#define REG_PCIE_CTRL_REG 0x0300112#define REG_INT_MIG 0x0304113#define REG_BCNQ_DESA 0x0308114#define REG_HQ_DESA 0x0310115#define REG_MGQ_DESA 0x0318116#define REG_VOQ_DESA 0x0320117#define REG_VIQ_DESA 0x0328118#define REG_BEQ_DESA 0x0330119#define REG_BKQ_DESA 0x0338120#define REG_RX_DESA 0x0340121#define REG_DBI 0x0348122#define REG_MDIO 0x0354123#define REG_DBG_SEL 0x0360124#define REG_PCIE_HRPWM 0x0361125#define REG_PCIE_HCPWM 0x0363126#define REG_UART_CTRL 0x0364127#define REG_UART_TX_DESA 0x0370128#define REG_UART_RX_DESA 0x0378129 130#define REG_HDAQ_DESA_NODEF 0x0000131#define REG_CMDQ_DESA_NODEF 0x0000132 133#define REG_VOQ_INFORMATION 0x0400134#define REG_VIQ_INFORMATION 0x0404135#define REG_BEQ_INFORMATION 0x0408136#define REG_BKQ_INFORMATION 0x040C137#define REG_MGQ_INFORMATION 0x0410138#define REG_HGQ_INFORMATION 0x0414139#define REG_BCNQ_INFORMATION 0x0418140 141#define REG_CPU_MGQ_INFORMATION 0x041C142#define REG_FWHW_TXQ_CTRL 0x0420143#define REG_HWSEQ_CTRL 0x0423144#define REG_TXPKTBUF_BCNQ_BDNY 0x0424145#define REG_TXPKTBUF_MGQ_BDNY 0x0425146#define REG_MULTI_BCNQ_EN 0x0426147#define REG_MULTI_BCNQ_OFFSET 0x0427148#define REG_SPEC_SIFS 0x0428149#define REG_RL 0x042A150#define REG_DARFRC 0x0430151#define REG_RARFRC 0x0438152#define REG_RRSR 0x0440153#define REG_ARFR0 0x0444154#define REG_ARFR1 0x0448155#define REG_ARFR2 0x044C156#define REG_ARFR3 0x0450157#define REG_AGGLEN_LMT 0x0458158#define REG_AMPDU_MIN_SPACE 0x045C159#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D160#define REG_FAST_EDCA_CTRL 0x0460161#define REG_RD_RESP_PKT_TH 0x0463162#define REG_INIRTS_RATE_SEL 0x0480163#define REG_INIDATA_RATE_SEL 0x0484164#define REG_POWER_STATUS 0x04A4165#define REG_POWER_STAGE1 0x04B4166#define REG_POWER_STAGE2 0x04B8167#define REG_PKT_LIFE_TIME 0x04C0168#define REG_STBC_SETTING 0x04C4169#define REG_PROT_MODE_CTRL 0x04C8170#define REG_BAR_MODE_CTRL 0x04CC171#define REG_RA_TRY_RATE_AGG_LMT 0x04CF172#define REG_NQOS_SEQ 0x04DC173#define REG_QOS_SEQ 0x04DE174#define REG_NEED_CPU_HANDLE 0x04E0175#define REG_PKT_LOSE_RPT 0x04E1176#define REG_PTCL_ERR_STATUS 0x04E2177#define REG_DUMMY 0x04FC178 179#define REG_EDCA_VO_PARAM 0x0500180#define REG_EDCA_VI_PARAM 0x0504181#define REG_EDCA_BE_PARAM 0x0508182#define REG_EDCA_BK_PARAM 0x050C183#define REG_BCNTCFG 0x0510184#define REG_PIFS 0x0512185#define REG_RDG_PIFS 0x0513186#define REG_SIFS_CTX 0x0514187#define REG_SIFS_TRX 0x0516188#define REG_AGGR_BREAK_TIME 0x051A189#define REG_SLOT 0x051B190#define REG_TX_PTCL_CTRL 0x0520191#define REG_TXPAUSE 0x0522192#define REG_DIS_TXREQ_CLR 0x0523193#define REG_RD_CTRL 0x0524194#define REG_TBTT_PROHIBIT 0x0540195#define REG_RD_NAV_NXT 0x0544196#define REG_NAV_PROT_LEN 0x0546197#define REG_BCN_CTRL 0x0550198#define REG_MBID_NUM 0x0552199#define REG_DUAL_TSF_RST 0x0553200#define REG_BCN_INTERVAL 0x0554201#define REG_MBSSID_BCN_SPACE 0x0554202#define REG_DRVERLYINT 0x0558203#define REG_BCNDMATIM 0x0559204#define REG_ATIMWND 0x055A205#define REG_USTIME_TSF 0x055C206#define REG_BCN_MAX_ERR 0x055D207#define REG_RXTSF_OFFSET_CCK 0x055E208#define REG_RXTSF_OFFSET_OFDM 0x055F209#define REG_TSFTR 0x0560210#define REG_INIT_TSFTR 0x0564211#define REG_PSTIMER 0x0580212#define REG_TIMER0 0x0584213#define REG_TIMER1 0x0588214#define REG_ACMHWCTRL 0x05C0215#define REG_ACMRSTCTRL 0x05C1216#define REG_ACMAVG 0x05C2217#define REG_VO_ADMTIME 0x05C4218#define REG_VI_ADMTIME 0x05C6219#define REG_BE_ADMTIME 0x05C8220#define REG_EDCA_RANDOM_GEN 0x05CC221#define REG_SCH_TXCMD 0x05D0222 223#define REG_APSD_CTRL 0x0600224#define REG_BWOPMODE 0x0603225#define REG_TCR 0x0604226#define REG_RCR 0x0608227#define REG_RX_PKT_LIMIT 0x060C228#define REG_RX_DLK_TIME 0x060D229#define REG_RX_DRVINFO_SZ 0x060F230 231#define REG_MACID 0x0610232#define REG_BSSID 0x0618233#define REG_MAR 0x0620234#define REG_MBIDCAMCFG 0x0628235 236#define REG_USTIME_EDCA 0x0638237#define REG_MAC_SPEC_SIFS 0x063A238#define REG_RESP_SIFS_CCK 0x063C239#define REG_RESP_SIFS_OFDM 0x063E240#define REG_ACKTO 0x0640241#define REG_CTS2TO 0x0641242#define REG_EIFS 0x0642243 244#define REG_NAV_CTRL 0x0650245#define REG_BACAMCMD 0x0654246#define REG_BACAMCONTENT 0x0658247#define REG_LBDLY 0x0660248#define REG_FWDLY 0x0661249#define REG_RXERR_RPT 0x0664250#define REG_WMAC_TRXPTCL_CTL 0x0668251 252#define REG_CAMCMD 0x0670253#define REG_CAMWRITE 0x0674254#define REG_CAMREAD 0x0678255#define REG_CAMDBG 0x067C256#define REG_SECCFG 0x0680257 258#define REG_WOW_CTRL 0x0690259#define REG_PSSTATUS 0x0691260#define REG_PS_RX_INFO 0x0692261#define REG_LPNAV_CTRL 0x0694262#define REG_WKFMCAM_CMD 0x0698263#define REG_WKFMCAM_RWD 0x069C264#define REG_RXFLTMAP0 0x06A0265#define REG_RXFLTMAP1 0x06A2266#define REG_RXFLTMAP2 0x06A4267#define REG_BCN_PSR_RPT 0x06A8268#define REG_CALB32K_CTRL 0x06AC269#define REG_PKT_MON_CTRL 0x06B4270#define REG_BT_COEX_TABLE 0x06C0271#define REG_WMAC_RESP_TXINFO 0x06D8272 273#define REG_USB_INFO 0xFE17274#define REG_USB_SPECIAL_OPTION 0xFE55275#define REG_USB_DMA_AGG_TO 0xFE5B276#define REG_USB_AGG_TO 0xFE5C277#define REG_USB_AGG_TH 0xFE5D278 279#define REG_TEST_USB_TXQS 0xFE48280#define REG_TEST_SIE_VID 0xFE60281#define REG_TEST_SIE_PID 0xFE62282#define REG_TEST_SIE_OPTIONAL 0xFE64283#define REG_TEST_SIE_CHIRP_K 0xFE65284#define REG_TEST_SIE_PHY 0xFE66285#define REG_TEST_SIE_MAC_ADDR 0xFE70286#define REG_TEST_SIE_STRING 0xFE80287 288#define REG_NORMAL_SIE_VID 0xFE60289#define REG_NORMAL_SIE_PID 0xFE62290#define REG_NORMAL_SIE_OPTIONAL 0xFE64291#define REG_NORMAL_SIE_EP 0xFE65292#define REG_NORMAL_SIE_PHY 0xFE68293#define REG_NORMAL_SIE_MAC_ADDR 0xFE70294#define REG_NORMAL_SIE_STRING 0xFE80295 296#define CR9346 REG_9346CR297#define MSR (REG_CR + 2)298#define ISR REG_HISR299#define TSFR REG_TSFTR300 301#define MACIDR0 REG_MACID302#define MACIDR4 (REG_MACID + 4)303 304#define PBP REG_PBP305 306#define IDR0 MACIDR0307#define IDR4 MACIDR4308 309#define UNUSED_REGISTER 0x1BF310#define DCAM UNUSED_REGISTER311#define PSR UNUSED_REGISTER312#define BBADDR UNUSED_REGISTER313#define PHYDATAR UNUSED_REGISTER314 315#define INVALID_BBRF_VALUE 0x12345678316 317#define MAX_MSS_DENSITY_2T 0x13318#define MAX_MSS_DENSITY_1T 0x0A319 320#define CMDEEPROM_EN BIT(5)321#define CMDEEPROM_SEL BIT(4)322#define CMD9346CR_9356SEL BIT(4)323#define AUTOLOAD_EEPROM (CMDEEPROM_EN|CMDEEPROM_SEL)324#define AUTOLOAD_EFUSE CMDEEPROM_EN325 326#define GPIOSEL_GPIO 0327#define GPIOSEL_ENBT BIT(5)328 329#define GPIO_IN REG_GPIO_PIN_CTRL330#define GPIO_OUT (REG_GPIO_PIN_CTRL+1)331#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2)332#define GPIO_MOD (REG_GPIO_PIN_CTRL+3)333 334#define MSR_NOLINK 0x00335#define MSR_ADHOC 0x01336#define MSR_INFRA 0x02337#define MSR_AP 0x03338 339#define RRSR_RSC_OFFSET 21340#define RRSR_SHORT_OFFSET 23341#define RRSR_RSC_BW_40M 0x600000342#define RRSR_RSC_UPSUBCHNL 0x400000343#define RRSR_RSC_LOWSUBCHNL 0x200000344#define RRSR_SHORT 0x800000345#define RRSR_1M BIT(0)346#define RRSR_2M BIT(1)347#define RRSR_5_5M BIT(2)348#define RRSR_11M BIT(3)349#define RRSR_6M BIT(4)350#define RRSR_9M BIT(5)351#define RRSR_12M BIT(6)352#define RRSR_18M BIT(7)353#define RRSR_24M BIT(8)354#define RRSR_36M BIT(9)355#define RRSR_48M BIT(10)356#define RRSR_54M BIT(11)357#define RRSR_MCS0 BIT(12)358#define RRSR_MCS1 BIT(13)359#define RRSR_MCS2 BIT(14)360#define RRSR_MCS3 BIT(15)361#define RRSR_MCS4 BIT(16)362#define RRSR_MCS5 BIT(17)363#define RRSR_MCS6 BIT(18)364#define RRSR_MCS7 BIT(19)365#define BRSR_ACKSHORTPMB BIT(23)366 367#define RATR_1M 0x00000001368#define RATR_2M 0x00000002369#define RATR_55M 0x00000004370#define RATR_11M 0x00000008371#define RATR_6M 0x00000010372#define RATR_9M 0x00000020373#define RATR_12M 0x00000040374#define RATR_18M 0x00000080375#define RATR_24M 0x00000100376#define RATR_36M 0x00000200377#define RATR_48M 0x00000400378#define RATR_54M 0x00000800379#define RATR_MCS0 0x00001000380#define RATR_MCS1 0x00002000381#define RATR_MCS2 0x00004000382#define RATR_MCS3 0x00008000383#define RATR_MCS4 0x00010000384#define RATR_MCS5 0x00020000385#define RATR_MCS6 0x00040000386#define RATR_MCS7 0x00080000387#define RATR_MCS8 0x00100000388#define RATR_MCS9 0x00200000389#define RATR_MCS10 0x00400000390#define RATR_MCS11 0x00800000391#define RATR_MCS12 0x01000000392#define RATR_MCS13 0x02000000393#define RATR_MCS14 0x04000000394#define RATR_MCS15 0x08000000395 396#define RATE_1M BIT(0)397#define RATE_2M BIT(1)398#define RATE_5_5M BIT(2)399#define RATE_11M BIT(3)400#define RATE_6M BIT(4)401#define RATE_9M BIT(5)402#define RATE_12M BIT(6)403#define RATE_18M BIT(7)404#define RATE_24M BIT(8)405#define RATE_36M BIT(9)406#define RATE_48M BIT(10)407#define RATE_54M BIT(11)408#define RATE_MCS0 BIT(12)409#define RATE_MCS1 BIT(13)410#define RATE_MCS2 BIT(14)411#define RATE_MCS3 BIT(15)412#define RATE_MCS4 BIT(16)413#define RATE_MCS5 BIT(17)414#define RATE_MCS6 BIT(18)415#define RATE_MCS7 BIT(19)416#define RATE_MCS8 BIT(20)417#define RATE_MCS9 BIT(21)418#define RATE_MCS10 BIT(22)419#define RATE_MCS11 BIT(23)420#define RATE_MCS12 BIT(24)421#define RATE_MCS13 BIT(25)422#define RATE_MCS14 BIT(26)423#define RATE_MCS15 BIT(27)424 425#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M)426#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M |\427 RATR_24M | RATR_36M | RATR_48M | RATR_54M)428#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 |\429 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 |\430 RATR_MCS6 | RATR_MCS7)431#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 |\432 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 |\433 RATR_MCS14 | RATR_MCS15)434 435#define BW_OPMODE_20MHZ BIT(2)436#define BW_OPMODE_5G BIT(1)437#define BW_OPMODE_11J BIT(0)438 439#define CAM_VALID BIT(15)440#define CAM_NOTVALID 0x0000441#define CAM_USEDK BIT(5)442 443#define CAM_NONE 0x0444#define CAM_WEP40 0x01445#define CAM_TKIP 0x02446#define CAM_AES 0x04447#define CAM_WEP104 0x05448 449#define TOTAL_CAM_ENTRY 32450#define HALF_CAM_ENTRY 16451 452#define CAM_WRITE BIT(16)453#define CAM_READ 0x00000000454#define CAM_POLLINIG BIT(31)455 456#define SCR_USEDK 0x01457#define SCR_TXSEC_ENABLE 0x02458#define SCR_RXSEC_ENABLE 0x04459 460#define WOW_PMEN BIT(0)461#define WOW_WOMEN BIT(1)462#define WOW_MAGIC BIT(2)463#define WOW_UWF BIT(3)464 465#define IMR8190_DISABLED 0x0466#define IMR_BCNDMAINT6 BIT(31)467#define IMR_BCNDMAINT5 BIT(30)468#define IMR_BCNDMAINT4 BIT(29)469#define IMR_BCNDMAINT3 BIT(28)470#define IMR_BCNDMAINT2 BIT(27)471#define IMR_BCNDMAINT1 BIT(26)472#define IMR_BCNDOK8 BIT(25)473#define IMR_BCNDOK7 BIT(24)474#define IMR_BCNDOK6 BIT(23)475#define IMR_BCNDOK5 BIT(22)476#define IMR_BCNDOK4 BIT(21)477#define IMR_BCNDOK3 BIT(20)478#define IMR_BCNDOK2 BIT(19)479#define IMR_BCNDOK1 BIT(18)480#define IMR_TIMEOUT2 BIT(17)481#define IMR_TIMEOUT1 BIT(16)482#define IMR_TXFOVW BIT(15)483#define IMR_PSTIMEOUT BIT(14)484#define IMR_BCNINT BIT(13)485#define IMR_RXFOVW BIT(12)486#define IMR_RDU BIT(11)487#define IMR_ATIMEND BIT(10)488#define IMR_BDOK BIT(9)489#define IMR_HIGHDOK BIT(8)490#define IMR_TBDOK BIT(7)491#define IMR_MGNTDOK BIT(6)492#define IMR_TBDER BIT(5)493#define IMR_BKDOK BIT(4)494#define IMR_BEDOK BIT(3)495#define IMR_VIDOK BIT(2)496#define IMR_VODOK BIT(1)497#define IMR_ROK BIT(0)498 499#define IMR_TXERR BIT(11)500#define IMR_RXERR BIT(10)501#define IMR_CPWM BIT(8)502#define IMR_OCPINT BIT(1)503#define IMR_WLANOFF BIT(0)504 505/* 8723E series PCIE Host IMR/ISR bit */506/* IMR DW0 Bit 0-31 */507#define PHIMR_TIMEOUT2 BIT(31)508#define PHIMR_TIMEOUT1 BIT(30)509#define PHIMR_PSTIMEOUT BIT(29)510#define PHIMR_GTINT4 BIT(28)511#define PHIMR_GTINT3 BIT(27)512#define PHIMR_TXBCNERR BIT(26)513#define PHIMR_TXBCNOK BIT(25)514#define PHIMR_TSF_BIT32_TOGGLE BIT(24)515#define PHIMR_BCNDMAINT3 BIT(23)516#define PHIMR_BCNDMAINT2 BIT(22)517#define PHIMR_BCNDMAINT1 BIT(21)518#define PHIMR_BCNDMAINT0 BIT(20)519#define PHIMR_BCNDOK3 BIT(19)520#define PHIMR_BCNDOK2 BIT(18)521#define PHIMR_BCNDOK1 BIT(17)522#define PHIMR_BCNDOK0 BIT(16)523#define PHIMR_HSISR_IND_ON BIT(15)524#define PHIMR_BCNDMAINT_E BIT(14)525#define PHIMR_ATIMEND_E BIT(13)526#define PHIMR_ATIM_CTW_END BIT(12)527#define PHIMR_HISRE_IND BIT(11)528#define PHIMR_C2HCMD BIT(10)529#define PHIMR_CPWM2 BIT(9)530#define PHIMR_CPWM BIT(8)531#define PHIMR_HIGHDOK BIT(7)532#define PHIMR_MGNTDOK BIT(6)533#define PHIMR_BKDOK BIT(5)534#define PHIMR_BEDOK BIT(4)535#define PHIMR_VIDOK BIT(3)536#define PHIMR_VODOK BIT(2)537#define PHIMR_RDU BIT(1)538#define PHIMR_ROK BIT(0)539 540/* PCIE Host Interrupt Status Extension bit */541#define PHIMR_BCNDMAINT7 BIT(23)542#define PHIMR_BCNDMAINT6 BIT(22)543#define PHIMR_BCNDMAINT5 BIT(21)544#define PHIMR_BCNDMAINT4 BIT(20)545#define PHIMR_BCNDOK7 BIT(19)546#define PHIMR_BCNDOK6 BIT(18)547#define PHIMR_BCNDOK5 BIT(17)548#define PHIMR_BCNDOK4 BIT(16)549/* bit12-15: RSVD */550#define PHIMR_TXERR BIT(11)551#define PHIMR_RXERR BIT(10)552#define PHIMR_TXFOVW BIT(9)553#define PHIMR_RXFOVW BIT(8)554/* bit2-7: RSVD */555#define PHIMR_OCPINT BIT(1)556 557#define HWSET_MAX_SIZE 256558#define EFUSE_MAX_SECTION 32559#define EFUSE_REAL_CONTENT_LEN 512560#define EFUSE_OOB_PROTECT_BYTES 15561 562#define EEPROM_DEFAULT_TSSI 0x0563#define EEPROM_DEFAULT_TXPOWERDIFF 0x0564#define EEPROM_DEFAULT_CRYSTALCAP 0x5565#define EEPROM_DEFAULT_BOARDTYPE 0x02566#define EEPROM_DEFAULT_TXPOWER 0x1010567#define EEPROM_DEFAULT_HT2T_TXPWR 0x10568 569#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3570#define EEPROM_DEFAULT_THERMALMETER 0x12571#define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0572#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5573#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22574#define EEPROM_DEFAULT_HT40_2SDIFF 0x0575#define EEPROM_DEFAULT_HT20_DIFF 2576#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3577#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0578#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0579 580#define EEPROM_DEFAULT_PID 0x1234581#define EEPROM_DEFAULT_VID 0x5678582#define EEPROM_DEFAULT_CUSTOMERID 0xAB583#define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD584#define EEPROM_DEFAULT_VERSION 0585 586#define EEPROM_CHANNEL_PLAN_FCC 0x0587#define EEPROM_CHANNEL_PLAN_IC 0x1588#define EEPROM_CHANNEL_PLAN_ETSI 0x2589#define EEPROM_CHANNEL_PLAN_SPAIN 0x3590#define EEPROM_CHANNEL_PLAN_FRANCE 0x4591#define EEPROM_CHANNEL_PLAN_MKK 0x5592#define EEPROM_CHANNEL_PLAN_MKK1 0x6593#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7594#define EEPROM_CHANNEL_PLAN_TELEC 0x8595#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9596#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA597#define EEPROM_CHANNEL_PLAN_NCC 0xB598#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80599 600#define EEPROM_CID_DEFAULT 0x0601#define EEPROM_CID_TOSHIBA 0x4602#define EEPROM_CID_CCX 0x10603#define EEPROM_CID_QMI 0x0D604#define EEPROM_CID_WHQL 0xFE605 606#define RTL8192_EEPROM_ID 0x8129607 608#define RTL8190_EEPROM_ID 0x8129609#define EEPROM_HPON 0x02610#define EEPROM_CLK 0x06611#define EEPROM_TESTR 0x08612 613#define EEPROM_VID 0x49614#define EEPROM_DID 0x4B615#define EEPROM_SVID 0x4D616#define EEPROM_SMID 0x4F617 618#define EEPROM_MAC_ADDR 0x67619 620#define EEPROM_CCK_TX_PWR_INX 0x5A621#define EEPROM_HT40_1S_TX_PWR_INX 0x60622#define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66623#define EEPROM_HT20_TX_PWR_INX_DIFF 0x69624#define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C625#define EEPROM_HT40_MAX_PWR_OFFSET 0x25626#define EEPROM_HT20_MAX_PWR_OFFSET 0x22627 628#define EEPROM_THERMAL_METER 0x2a629#define EEPROM_XTAL_K 0x78630#define EEPROM_RF_OPT1 0x79631#define EEPROM_RF_OPT2 0x7A632#define EEPROM_RF_OPT3 0x7B633#define EEPROM_RF_OPT4 0x7C634#define EEPROM_CHANNEL_PLAN 0x28635#define EEPROM_VERSION 0x30636#define EEPROM_CUSTOMER_ID 0x31637 638#define EEPROM_PWRDIFF 0x54639 640#define EEPROM_TXPOWERCCK 0x10641#define EEPROM_TXPOWERHT40_1S 0x16642#define EEPROM_TXPOWERHT40_2SDIFF 0x66643#define EEPROM_TXPOWERHT20DIFF 0x1C644#define EEPROM_TXPOWER_OFDMDIFF 0x1F645 646#define EEPROM_TXPWR_GROUP 0x22647 648#define EEPROM_TSSI_A 0x29649#define EEPROM_TSSI_B 0x77650 651#define EEPROM_CHANNELPLAN 0x28652 653#define RF_OPTION1 0x2B654#define RF_OPTION2 0x2C655#define RF_OPTION3 0x2D656#define RF_OPTION4 0x2E657 658#define STOPBECON BIT(6)659#define STOPHIGHT BIT(5)660#define STOPMGT BIT(4)661#define STOPVO BIT(3)662#define STOPVI BIT(2)663#define STOPBE BIT(1)664#define STOPBK BIT(0)665 666#define RCR_APPFCS BIT(31)667#define RCR_APP_MIC BIT(30)668#define RCR_APP_ICV BIT(29)669#define RCR_APP_PHYST_RXFF BIT(28)670#define RCR_APP_BA_SSN BIT(27)671#define RCR_ENMBID BIT(24)672#define RCR_LSIGEN BIT(23)673#define RCR_MFBEN BIT(22)674#define RCR_HTC_LOC_CTRL BIT(14)675#define RCR_AMF BIT(13)676#define RCR_ACF BIT(12)677#define RCR_ADF BIT(11)678#define RCR_AICV BIT(9)679#define RCR_ACRC32 BIT(8)680#define RCR_CBSSID_BCN BIT(7)681#define RCR_CBSSID_DATA BIT(6)682#define RCR_CBSSID RCR_CBSSID_DATA683#define RCR_APWRMGT BIT(5)684#define RCR_ADD3 BIT(4)685#define RCR_AB BIT(3)686#define RCR_AM BIT(2)687#define RCR_APM BIT(1)688#define RCR_AAP BIT(0)689#define RCR_MXDMA_OFFSET 8690#define RCR_FIFO_OFFSET 13691 692#define RSV_CTRL 0x001C693#define RD_CTRL 0x0524694 695#define REG_USB_INFO 0xFE17696#define REG_USB_SPECIAL_OPTION 0xFE55697#define REG_USB_DMA_AGG_TO 0xFE5B698#define REG_USB_AGG_TO 0xFE5C699#define REG_USB_AGG_TH 0xFE5D700 701#define REG_USB_VID 0xFE60702#define REG_USB_PID 0xFE62703#define REG_USB_OPTIONAL 0xFE64704#define REG_USB_CHIRP_K 0xFE65705#define REG_USB_PHY 0xFE66706#define REG_USB_MAC_ADDR 0xFE70707#define REG_USB_HRPWM 0xFE58708#define REG_USB_HCPWM 0xFE57709 710#define SW18_FPWM BIT(3)711 712#define ISO_MD2PP BIT(0)713#define ISO_UA2USB BIT(1)714#define ISO_UD2CORE BIT(2)715#define ISO_PA2PCIE BIT(3)716#define ISO_PD2CORE BIT(4)717#define ISO_IP2MAC BIT(5)718#define ISO_DIOP BIT(6)719#define ISO_DIOE BIT(7)720#define ISO_EB2CORE BIT(8)721#define ISO_DIOR BIT(9)722 723#define PWC_EV25V BIT(14)724#define PWC_EV12V BIT(15)725 726#define FEN_BBRSTB BIT(0)727#define FEN_BB_GLB_RSTN BIT(1)728#define FEN_USBA BIT(2)729#define FEN_UPLL BIT(3)730#define FEN_USBD BIT(4)731#define FEN_DIO_PCIE BIT(5)732#define FEN_PCIEA BIT(6)733#define FEN_PPLL BIT(7)734#define FEN_PCIED BIT(8)735#define FEN_DIOE BIT(9)736#define FEN_CPUEN BIT(10)737#define FEN_DCORE BIT(11)738#define FEN_ELDR BIT(12)739#define FEN_DIO_RF BIT(13)740#define FEN_HWPDN BIT(14)741#define FEN_MREGEN BIT(15)742 743#define PFM_LDALL BIT(0)744#define PFM_ALDN BIT(1)745#define PFM_LDKP BIT(2)746#define PFM_WOWL BIT(3)747#define ENPDN BIT(4)748#define PDN_PL BIT(5)749#define APFM_ONMAC BIT(8)750#define APFM_OFF BIT(9)751#define APFM_RSM BIT(10)752#define AFSM_HSUS BIT(11)753#define AFSM_PCIE BIT(12)754#define APDM_MAC BIT(13)755#define APDM_HOST BIT(14)756#define APDM_HPDN BIT(15)757#define RDY_MACON BIT(16)758#define SUS_HOST BIT(17)759#define ROP_ALD BIT(20)760#define ROP_PWR BIT(21)761#define ROP_SPS BIT(22)762#define SOP_MRST BIT(25)763#define SOP_FUSE BIT(26)764#define SOP_ABG BIT(27)765#define SOP_AMB BIT(28)766#define SOP_RCK BIT(29)767#define SOP_A8M BIT(30)768#define XOP_BTCK BIT(31)769 770#define ANAD16V_EN BIT(0)771#define ANA8M BIT(1)772#define MACSLP BIT(4)773#define LOADER_CLK_EN BIT(5)774#define _80M_SSC_DIS BIT(7)775#define _80M_SSC_EN_HO BIT(8)776#define PHY_SSC_RSTB BIT(9)777#define SEC_CLK_EN BIT(10)778#define MAC_CLK_EN BIT(11)779#define SYS_CLK_EN BIT(12)780#define RING_CLK_EN BIT(13)781 782#define BOOT_FROM_EEPROM BIT(4)783#define EEPROM_EN BIT(5)784 785#define AFE_BGEN BIT(0)786#define AFE_MBEN BIT(1)787#define MAC_ID_EN BIT(7)788 789#define WLOCK_ALL BIT(0)790#define WLOCK_00 BIT(1)791#define WLOCK_04 BIT(2)792#define WLOCK_08 BIT(3)793#define WLOCK_40 BIT(4)794#define R_DIS_PRST_0 BIT(5)795#define R_DIS_PRST_1 BIT(6)796#define LOCK_ALL_EN BIT(7)797 798#define RF_EN BIT(0)799#define RF_RSTB BIT(1)800#define RF_SDMRSTB BIT(2)801 802#define LDA15_EN BIT(0)803#define LDA15_STBY BIT(1)804#define LDA15_OBUF BIT(2)805#define LDA15_REG_VOS BIT(3)806#define _LDA15_VOADJ(x) (((x) & 0x7) << 4)807 808#define LDV12_EN BIT(0)809#define LDV12_SDBY BIT(1)810#define LPLDO_HSM BIT(2)811#define LPLDO_LSM_DIS BIT(3)812#define _LDV12_VADJ(x) (((x) & 0xF) << 4)813 814#define XTAL_EN BIT(0)815#define XTAL_BSEL BIT(1)816#define _XTAL_BOSC(x) (((x) & 0x3) << 2)817#define _XTAL_CADJ(x) (((x) & 0xF) << 4)818#define XTAL_GATE_USB BIT(8)819#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9)820#define XTAL_GATE_AFE BIT(11)821#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12)822#define XTAL_RF_GATE BIT(14)823#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15)824#define XTAL_GATE_DIG BIT(17)825#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18)826#define XTAL_BT_GATE BIT(20)827#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21)828#define _XTAL_GPIO(x) (((x) & 0x7) << 23)829 830#define CKDLY_AFE BIT(26)831#define CKDLY_USB BIT(27)832#define CKDLY_DIG BIT(28)833#define CKDLY_BT BIT(29)834 835#define APLL_EN BIT(0)836#define APLL_320_EN BIT(1)837#define APLL_FREF_SEL BIT(2)838#define APLL_EDGE_SEL BIT(3)839#define APLL_WDOGB BIT(4)840#define APLL_LPFEN BIT(5)841 842#define APLL_REF_CLK_13MHZ 0x1843#define APLL_REF_CLK_19_2MHZ 0x2844#define APLL_REF_CLK_20MHZ 0x3845#define APLL_REF_CLK_25MHZ 0x4846#define APLL_REF_CLK_26MHZ 0x5847#define APLL_REF_CLK_38_4MHZ 0x6848#define APLL_REF_CLK_40MHZ 0x7849 850#define APLL_320EN BIT(14)851#define APLL_80EN BIT(15)852#define APLL_1MEN BIT(24)853 854#define ALD_EN BIT(18)855#define EF_PD BIT(19)856#define EF_FLAG BIT(31)857 858#define EF_TRPT BIT(7)859#define LDOE25_EN BIT(31)860 861#define RSM_EN BIT(0)862#define TIMER_EN BIT(4)863 864#define TRSW0EN BIT(2)865#define TRSW1EN BIT(3)866#define EROM_EN BIT(4)867#define ENBT BIT(5)868#define ENUART BIT(8)869#define UART_910 BIT(9)870#define ENPMAC BIT(10)871#define SIC_SWRST BIT(11)872#define ENSIC BIT(12)873#define SIC_23 BIT(13)874#define ENHDP BIT(14)875#define SIC_LBK BIT(15)876 877#define LED0PL BIT(4)878#define LED1PL BIT(12)879#define LED0DIS BIT(7)880 881#define MCUFWDL_EN BIT(0)882#define MCUFWDL_RDY BIT(1)883#define FWDL_CHKSUM_RPT BIT(2)884#define MACINI_RDY BIT(3)885#define BBINI_RDY BIT(4)886#define RFINI_RDY BIT(5)887#define WINTINI_RDY BIT(6)888#define CPRST BIT(23)889 890#define XCLK_VLD BIT(0)891#define ACLK_VLD BIT(1)892#define UCLK_VLD BIT(2)893#define PCLK_VLD BIT(3)894#define PCIRSTB BIT(4)895#define V15_VLD BIT(5)896#define TRP_B15V_EN BIT(7)897#define SIC_IDLE BIT(8)898#define BD_MAC2 BIT(9)899#define BD_MAC1 BIT(10)900#define IC_MACPHY_MODE BIT(11)901#define BT_FUNC BIT(16)902#define VENDOR_ID BIT(19)903#define PAD_HWPD_IDN BIT(22)904#define TRP_VAUX_EN BIT(23)905#define TRP_BT_EN BIT(24)906#define BD_PKG_SEL BIT(25)907#define BD_HCI_SEL BIT(26)908#define TYPE_ID BIT(27)909 910#define CHIP_VER_RTL_MASK 0xF000911#define CHIP_VER_RTL_SHIFT 12912 913#define REG_LBMODE (REG_CR + 3)914 915#define HCI_TXDMA_EN BIT(0)916#define HCI_RXDMA_EN BIT(1)917#define TXDMA_EN BIT(2)918#define RXDMA_EN BIT(3)919#define PROTOCOL_EN BIT(4)920#define SCHEDULE_EN BIT(5)921#define MACTXEN BIT(6)922#define MACRXEN BIT(7)923#define ENSWBCN BIT(8)924#define ENSEC BIT(9)925 926#define _NETTYPE(x) (((x) & 0x3) << 16)927#define MASK_NETTYPE 0x30000928#define NT_NO_LINK 0x0929#define NT_LINK_AD_HOC 0x1930#define NT_LINK_AP 0x2931#define NT_AS_AP 0x3932 933#define _LBMODE(x) (((x) & 0xF) << 24)934#define MASK_LBMODE 0xF000000935#define LOOPBACK_NORMAL 0x0936#define LOOPBACK_IMMEDIATELY 0xB937#define LOOPBACK_MAC_DELAY 0x3938#define LOOPBACK_PHY 0x1939#define LOOPBACK_DMA 0x7940 941#define GET_RX_PAGE_SIZE(value) ((value) & 0xF)942#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)943#define _PSRX_MASK 0xF944#define _PSTX_MASK 0xF0945#define _PSRX(x) (x)946#define _PSTX(x) ((x) << 4)947 948#define PBP_64 0x0949#define PBP_128 0x1950#define PBP_256 0x2951#define PBP_512 0x3952#define PBP_1024 0x4953 954#define RXDMA_ARBBW_EN BIT(0)955#define RXSHFT_EN BIT(1)956#define RXDMA_AGG_EN BIT(2)957#define QS_VO_QUEUE BIT(8)958#define QS_VI_QUEUE BIT(9)959#define QS_BE_QUEUE BIT(10)960#define QS_BK_QUEUE BIT(11)961#define QS_MANAGER_QUEUE BIT(12)962#define QS_HIGH_QUEUE BIT(13)963 964#define HQSEL_VOQ BIT(0)965#define HQSEL_VIQ BIT(1)966#define HQSEL_BEQ BIT(2)967#define HQSEL_BKQ BIT(3)968#define HQSEL_MGTQ BIT(4)969#define HQSEL_HIQ BIT(5)970 971#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)972#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)973#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)974#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8)975#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6)976#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4)977 978#define QUEUE_LOW 1979#define QUEUE_NORMAL 2980#define QUEUE_HIGH 3981 982#define _LLT_NO_ACTIVE 0x0983#define _LLT_WRITE_ACCESS 0x1984#define _LLT_READ_ACCESS 0x2985 986#define _LLT_INIT_DATA(x) ((x) & 0xFF)987#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)988#define _LLT_OP(x) (((x) & 0x3) << 30)989#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)990 991#define BB_WRITE_READ_MASK (BIT(31) | BIT(30))992#define BB_WRITE_EN BIT(30)993#define BB_READ_EN BIT(31)994 995#define _HPQ(x) ((x) & 0xFF)996#define _LPQ(x) (((x) & 0xFF) << 8)997#define _PUBQ(x) (((x) & 0xFF) << 16)998#define _NPQ(x) ((x) & 0xFF)999 1000#define HPQ_PUBLIC_DIS BIT(24)1001#define LPQ_PUBLIC_DIS BIT(25)1002#define LD_RQPN BIT(31)1003 1004#define BCN_VALID BIT(16)1005#define BCN_HEAD(x) (((x) & 0xFF) << 8)1006#define BCN_HEAD_MASK 0xFF001007 1008#define BLK_DESC_NUM_SHIFT 41009#define BLK_DESC_NUM_MASK 0xF1010 1011#define DROP_DATA_EN BIT(9)1012 1013#define EN_AMPDU_RTY_NEW BIT(7)1014 1015#define _INIRTSMCS_SEL(x) ((x) & 0x3F)1016 1017#define _SPEC_SIFS_CCK(x) ((x) & 0xFF)1018#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)1019 1020#define RATE_REG_BITMAP_ALL 0xFFFFF1021 1022#define _RRSC_BITMAP(x) ((x) & 0xFFFFF)1023 1024#define _RRSR_RSC(x) (((x) & 0x3) << 21)1025#define RRSR_RSC_RESERVED 0x01026#define RRSR_RSC_UPPER_SUBCHANNEL 0x11027#define RRSR_RSC_LOWER_SUBCHANNEL 0x21028#define RRSR_RSC_DUPLICATE_MODE 0x31029 1030#define USE_SHORT_G1 BIT(20)1031 1032#define _AGGLMT_MCS0(x) ((x) & 0xF)1033#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4)1034#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8)1035#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12)1036#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16)1037#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20)1038#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24)1039#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28)1040 1041#define RETRY_LIMIT_SHORT_SHIFT 81042#define RETRY_LIMIT_LONG_SHIFT 01043 1044#define _DARF_RC1(x) ((x) & 0x1F)1045#define _DARF_RC2(x) (((x) & 0x1F) << 8)1046#define _DARF_RC3(x) (((x) & 0x1F) << 16)1047#define _DARF_RC4(x) (((x) & 0x1F) << 24)1048#define _DARF_RC5(x) ((x) & 0x1F)1049#define _DARF_RC6(x) (((x) & 0x1F) << 8)1050#define _DARF_RC7(x) (((x) & 0x1F) << 16)1051#define _DARF_RC8(x) (((x) & 0x1F) << 24)1052 1053#define _RARF_RC1(x) ((x) & 0x1F)1054#define _RARF_RC2(x) (((x) & 0x1F) << 8)1055#define _RARF_RC3(x) (((x) & 0x1F) << 16)1056#define _RARF_RC4(x) (((x) & 0x1F) << 24)1057#define _RARF_RC5(x) ((x) & 0x1F)1058#define _RARF_RC6(x) (((x) & 0x1F) << 8)1059#define _RARF_RC7(x) (((x) & 0x1F) << 16)1060#define _RARF_RC8(x) (((x) & 0x1F) << 24)1061 1062#define AC_PARAM_TXOP_LIMIT_OFFSET 161063#define AC_PARAM_ECW_MAX_OFFSET 121064#define AC_PARAM_ECW_MIN_OFFSET 81065#define AC_PARAM_AIFS_OFFSET 01066 1067#define _AIFS(x) (x)1068#define _ECW_MAX_MIN(x) ((x) << 8)1069#define _TXOP_LIMIT(x) ((x) << 16)1070 1071#define _BCNIFS(x) ((x) & 0xFF)1072#define _BCNECW(x) ((((x) & 0xF)) << 8)1073 1074#define _LRL(x) ((x) & 0x3F)1075#define _SRL(x) (((x) & 0x3F) << 8)1076 1077#define _SIFS_CCK_CTX(x) ((x) & 0xFF)1078#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8)1079 1080#define _SIFS_OFDM_CTX(x) ((x) & 0xFF)1081#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8)1082 1083#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8)1084 1085#define DIS_EDCA_CNT_DWN BIT(11)1086 1087#define EN_MBSSID BIT(1)1088#define EN_TXBCN_RPT BIT(2)1089#define EN_BCN_FUNCTION BIT(3)1090 1091#define TSFTR_RST BIT(0)1092#define TSFTR1_RST BIT(1)1093 1094#define STOP_BCNQ BIT(6)1095 1096#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4)1097#define DIS_TSF_UDT0_TEST_CHIP BIT(5)1098 1099#define ACMHW_HWEN BIT(0)1100#define ACMHW_BEQEN BIT(1)1101#define ACMHW_VIQEN BIT(2)1102#define ACMHW_VOQEN BIT(3)1103#define ACMHW_BEQSTATUS BIT(4)1104#define ACMHW_VIQSTATUS BIT(5)1105#define ACMHW_VOQSTATUS BIT(6)1106 1107#define APSDOFF BIT(6)1108#define APSDOFF_STATUS BIT(7)1109 1110#define BW_20MHZ BIT(2)1111 1112#define RATE_BITMAP_ALL 0xFFFFF1113 1114#define RATE_RRSR_CCK_ONLY_1M 0xFFFF11115 1116#define TSFRST BIT(0)1117#define DIS_GCLK BIT(1)1118#define PAD_SEL BIT(2)1119#define PWR_ST BIT(6)1120#define PWRBIT_OW_EN BIT(7)1121#define ACRC BIT(8)1122#define CFENDFORM BIT(9)1123#define ICV BIT(10)1124 1125#define AAP BIT(0)1126#define APM BIT(1)1127#define AM BIT(2)1128#define AB BIT(3)1129#define ADD3 BIT(4)1130#define APWRMGT BIT(5)1131#define CBSSID BIT(6)1132#define CBSSID_DATA BIT(6)1133#define CBSSID_BCN BIT(7)1134#define ACRC32 BIT(8)1135#define AICV BIT(9)1136#define ADF BIT(11)1137#define ACF BIT(12)1138#define AMF BIT(13)1139#define HTC_LOC_CTRL BIT(14)1140#define UC_DATA_EN BIT(16)1141#define BM_DATA_EN BIT(17)1142#define MFBEN BIT(22)1143#define LSIGEN BIT(23)1144#define ENMBID BIT(24)1145#define APP_BASSN BIT(27)1146#define APP_PHYSTS BIT(28)1147#define APP_ICV BIT(29)1148#define APP_MIC BIT(30)1149#define APP_FCS BIT(31)1150 1151#define _MIN_SPACE(x) ((x) & 0x7)1152#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3)1153 1154#define RXERR_TYPE_OFDM_PPDU 01155#define RXERR_TYPE_OFDM_FALSE_ALARM 11156#define RXERR_TYPE_OFDM_MPDU_OK 21157#define RXERR_TYPE_OFDM_MPDU_FAIL 31158#define RXERR_TYPE_CCK_PPDU 41159#define RXERR_TYPE_CCK_FALSE_ALARM 51160#define RXERR_TYPE_CCK_MPDU_OK 61161#define RXERR_TYPE_CCK_MPDU_FAIL 71162#define RXERR_TYPE_HT_PPDU 81163#define RXERR_TYPE_HT_FALSE_ALARM 91164#define RXERR_TYPE_HT_MPDU_TOTAL 101165#define RXERR_TYPE_HT_MPDU_OK 111166#define RXERR_TYPE_HT_MPDU_FAIL 121167#define RXERR_TYPE_RX_FULL_DROP 151168 1169#define RXERR_COUNTER_MASK 0xFFFFF1170#define RXERR_RPT_RST BIT(27)1171#define _RXERR_RPT_SEL(type) ((type) << 28)1172 1173#define SCR_TXUSEDK BIT(0)1174#define SCR_RXUSEDK BIT(1)1175#define SCR_TXENCENABLE BIT(2)1176#define SCR_RXDECENABLE BIT(3)1177#define SCR_SKBYA2 BIT(4)1178#define SCR_NOSKMC BIT(5)1179#define SCR_TXBCUSEDK BIT(6)1180#define SCR_RXBCUSEDK BIT(7)1181 1182#define USB_IS_HIGH_SPEED 01183#define USB_IS_FULL_SPEED 11184#define USB_SPEED_MASK BIT(5)1185 1186#define USB_NORMAL_SIE_EP_MASK 0xF1187#define USB_NORMAL_SIE_EP_SHIFT 41188 1189#define USB_TEST_EP_MASK 0x301190#define USB_TEST_EP_SHIFT 41191 1192#define USB_AGG_EN BIT(3)1193 1194#define MAC_ADDR_LEN 61195#define LAST_ENTRY_OF_TX_PKT_BUFFER 2551196 1197#define POLLING_LLT_THRESHOLD 201198#define POLLING_READY_TIMEOUT_COUNT 10001199 1200#define MAX_MSS_DENSITY_2T 0x131201#define MAX_MSS_DENSITY_1T 0x0A1202 1203#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))1204#define EPROM_CMD_CONFIG 0x31205#define EPROM_CMD_LOAD 11206 1207#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE1208 1209#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2)1210 1211#define RPMAC_RESET 0x1001212#define RPMAC_TXSTART 0x1041213#define RPMAC_TXLEGACYSIG 0x1081214#define RPMAC_TXHTSIG1 0x10c1215#define RPMAC_TXHTSIG2 0x1101216#define RPMAC_PHYDEBUG 0x1141217#define RPMAC_TXPACKETNUM 0x1181218#define RPMAC_TXIDLE 0x11c1219#define RPMAC_TXMACHEADER0 0x1201220#define RPMAC_TXMACHEADER1 0x1241221#define RPMAC_TXMACHEADER2 0x1281222#define RPMAC_TXMACHEADER3 0x12c1223#define RPMAC_TXMACHEADER4 0x1301224#define RPMAC_TXMACHEADER5 0x1341225#define RPMAC_TXDADATYPE 0x1381226#define RPMAC_TXRANDOMSEED 0x13c1227#define RPMAC_CCKPLCPPREAMBLE 0x1401228#define RPMAC_CCKPLCPHEADER 0x1441229#define RPMAC_CCKCRC16 0x1481230#define RPMAC_OFDMRXCRC32OK 0x1701231#define RPMAC_OFDMRXCRC32ER 0x1741232#define RPMAC_OFDMRXPARITYER 0x1781233#define RPMAC_OFDMRXCRC8ER 0x17c1234#define RPMAC_CCKCRXRC16ER 0x1801235#define RPMAC_CCKCRXRC32ER 0x1841236#define RPMAC_CCKCRXRC32OK 0x1881237#define RPMAC_TXSTATUS 0x18c1238 1239#define RFPGA0_RFMOD 0x8001240 1241#define RFPGA0_TXINFO 0x8041242#define RFPGA0_PSDFUNCTION 0x8081243 1244#define RFPGA0_TXGAINSTAGE 0x80c1245 1246#define RFPGA0_RFTIMING1 0x8101247#define RFPGA0_RFTIMING2 0x8141248 1249#define RFPGA0_XA_HSSIPARAMETER1 0x8201250#define RFPGA0_XA_HSSIPARAMETER2 0x8241251#define RFPGA0_XB_HSSIPARAMETER1 0x8281252#define RFPGA0_XB_HSSIPARAMETER2 0x82c1253 1254#define RFPGA0_XA_LSSIPARAMETER 0x8401255#define RFPGA0_XB_LSSIPARAMETER 0x8441256 1257#define RFPGA0_RFWAKEUPPARAMETER 0x8501258#define RFPGA0_RFSLEEPUPPARAMETER 0x8541259 1260#define RFPGA0_XAB_SWITCHCONTROL 0x8581261#define RFPGA0_XCD_SWITCHCONTROL 0x85c1262 1263#define RFPGA0_XA_RFINTERFACEOE 0x8601264#define RFPGA0_XB_RFINTERFACEOE 0x8641265 1266#define RFPGA0_XAB_RFINTERFACESW 0x8701267#define RFPGA0_XCD_RFINTERFACESW 0x8741268 1269#define RFPGA0_XAB_RFPARAMETER 0x8781270#define RFPGA0_XCD_RFPARAMETER 0x87c1271 1272#define RFPGA0_ANALOGPARAMETER1 0x8801273#define RFPGA0_ANALOGPARAMETER2 0x8841274#define RFPGA0_ANALOGPARAMETER3 0x8881275#define RFPGA0_ANALOGPARAMETER4 0x88c1276 1277#define RFPGA0_XA_LSSIREADBACK 0x8a01278#define RFPGA0_XB_LSSIREADBACK 0x8a41279#define RFPGA0_XC_LSSIREADBACK 0x8a81280#define RFPGA0_XD_LSSIREADBACK 0x8ac1281 1282#define RFPGA0_PSDREPORT 0x8b41283#define TRANSCEIVEA_HSPI_READBACK 0x8b81284#define TRANSCEIVEB_HSPI_READBACK 0x8bc1285#define RFPGA0_XAB_RFINTERFACERB 0x8e01286#define RFPGA0_XCD_RFINTERFACERB 0x8e41287 1288#define RFPGA1_RFMOD 0x9001289 1290#define RFPGA1_TXBLOCK 0x9041291#define RFPGA1_DEBUGSELECT 0x9081292#define RFPGA1_TXINFO 0x90c1293 1294#define RCCK0_SYSTEM 0xa001295 1296#define RCCK0_AFESETTING 0xa041297#define RCCK0_CCA 0xa081298 1299#define RCCK0_RXAGC1 0xa0c1300#define RCCK0_RXAGC2 0xa101301 1302#define RCCK0_RXHP 0xa141303 1304#define RCCK0_DSPPARAMETER1 0xa181305#define RCCK0_DSPPARAMETER2 0xa1c1306 1307#define RCCK0_TXFILTER1 0xa201308#define RCCK0_TXFILTER2 0xa241309#define RCCK0_DEBUGPORT 0xa281310#define RCCK0_FALSEALARMREPORT 0xa2c1311#define RCCK0_TRSSIREPORT 0xa501312#define RCCK0_RXREPORT 0xa541313#define RCCK0_FACOUNTERLOWER 0xa5c1314#define RCCK0_FACOUNTERUPPER 0xa581315 1316#define ROFDM0_LSTF 0xc001317 1318#define ROFDM0_TRXPATHENABLE 0xc041319#define ROFDM0_TRMUXPAR 0xc081320#define ROFDM0_TRSWISOLATION 0xc0c1321 1322#define ROFDM0_XARXAFE 0xc101323#define ROFDM0_XARXIQIMBALANCE 0xc141324#define ROFDM0_XBRXAFE 0xc181325#define ROFDM0_XBRXIQIMBALANCE 0xc1c1326#define ROFDM0_XCRXAFE 0xc201327#define ROFDM0_XCRXIQIMBANLANCE 0xc241328#define ROFDM0_XDRXAFE 0xc281329#define ROFDM0_XDRXIQIMBALANCE 0xc2c1330 1331#define ROFDM0_RXDETECTOR1 0xc301332#define ROFDM0_RXDETECTOR2 0xc341333#define ROFDM0_RXDETECTOR3 0xc381334#define ROFDM0_RXDETECTOR4 0xc3c1335 1336#define ROFDM0_RXDSP 0xc401337#define ROFDM0_CFOANDDAGC 0xc441338#define ROFDM0_CCADROPTHRESHOLD 0xc481339#define ROFDM0_ECCATHRESHOLD 0xc4c1340 1341#define ROFDM0_XAAGCCORE1 0xc501342#define ROFDM0_XAAGCCORE2 0xc541343#define ROFDM0_XBAGCCORE1 0xc581344#define ROFDM0_XBAGCCORE2 0xc5c1345#define ROFDM0_XCAGCCORE1 0xc601346#define ROFDM0_XCAGCCORE2 0xc641347#define ROFDM0_XDAGCCORE1 0xc681348#define ROFDM0_XDAGCCORE2 0xc6c1349 1350#define ROFDM0_AGCPARAMETER1 0xc701351#define ROFDM0_AGCPARAMETER2 0xc741352#define ROFDM0_AGCRSSITABLE 0xc781353#define ROFDM0_HTSTFAGC 0xc7c1354 1355#define ROFDM0_XATXIQIMBALANCE 0xc801356#define ROFDM0_XATXAFE 0xc841357#define ROFDM0_XBTXIQIMBALANCE 0xc881358#define ROFDM0_XBTXAFE 0xc8c1359#define ROFDM0_XCTXIQIMBALANCE 0xc901360#define ROFDM0_XCTXAFE 0xc941361#define ROFDM0_XDTXIQIMBALANCE 0xc981362#define ROFDM0_XDTXAFE 0xc9c1363 1364#define ROFDM0_RXIQEXTANTA 0xca01365 1366#define ROFDM0_RXHPPARAMETER 0xce01367#define ROFDM0_TXPSEUDONOISEWGT 0xce41368#define ROFDM0_FRAMESYNC 0xcf01369#define ROFDM0_DFSREPORT 0xcf41370#define ROFDM0_TXCOEFF1 0xca41371#define ROFDM0_TXCOEFF2 0xca81372#define ROFDM0_TXCOEFF3 0xcac1373#define ROFDM0_TXCOEFF4 0xcb01374#define ROFDM0_TXCOEFF5 0xcb41375#define ROFDM0_TXCOEFF6 0xcb81376 1377#define ROFDM1_LSTF 0xd001378#define ROFDM1_TRXPATHENABLE 0xd041379 1380#define ROFDM1_CF0 0xd081381#define ROFDM1_CSI1 0xd101382#define ROFDM1_SBD 0xd141383#define ROFDM1_CSI2 0xd181384#define ROFDM1_CFOTRACKING 0xd2c1385#define ROFDM1_TRXMESAURE1 0xd341386#define ROFDM1_INTFDET 0xd3c1387#define ROFDM1_PSEUDONOISESTATEAB 0xd501388#define ROFDM1_PSEUDONOISESTATECD 0xd541389#define ROFDM1_RXPSEUDONOISEWGT 0xd581390 1391#define ROFDM_PHYCOUNTER1 0xda01392#define ROFDM_PHYCOUNTER2 0xda41393#define ROFDM_PHYCOUNTER3 0xda81394 1395#define ROFDM_SHORTCFOAB 0xdac1396#define ROFDM_SHORTCFOCD 0xdb01397#define ROFDM_LONGCFOAB 0xdb41398#define ROFDM_LONGCFOCD 0xdb81399#define ROFDM_TAILCF0AB 0xdbc1400#define ROFDM_TAILCF0CD 0xdc01401#define ROFDM_PWMEASURE1 0xdc41402#define ROFDM_PWMEASURE2 0xdc81403#define ROFDM_BWREPORT 0xdcc1404#define ROFDM_AGCREPORT 0xdd01405#define ROFDM_RXSNR 0xdd41406#define ROFDM_RXEVMCSI 0xdd81407#define ROFDM_SIGREPORT 0xddc1408 1409#define RTXAGC_A_RATE18_06 0xe001410#define RTXAGC_A_RATE54_24 0xe041411#define RTXAGC_A_CCK1_MCS32 0xe081412#define RTXAGC_A_MCS03_MCS00 0xe101413#define RTXAGC_A_MCS07_MCS04 0xe141414#define RTXAGC_A_MCS11_MCS08 0xe181415#define RTXAGC_A_MCS15_MCS12 0xe1c1416 1417#define RTXAGC_B_RATE18_06 0x8301418#define RTXAGC_B_RATE54_24 0x8341419#define RTXAGC_B_CCK1_55_MCS32 0x8381420#define RTXAGC_B_MCS03_MCS00 0x83c1421#define RTXAGC_B_MCS07_MCS04 0x8481422#define RTXAGC_B_MCS11_MCS08 0x84c1423#define RTXAGC_B_MCS15_MCS12 0x8681424#define RTXAGC_B_CCK11_A_CCK2_11 0x86c1425 1426#define RZEBRA1_HSSIENABLE 0x01427#define RZEBRA1_TRXENABLE1 0x11428#define RZEBRA1_TRXENABLE2 0x21429#define RZEBRA1_AGC 0x41430#define RZEBRA1_CHARGEPUMP 0x51431#define RZEBRA1_CHANNEL 0x71432 1433#define RZEBRA1_TXGAIN 0x81434#define RZEBRA1_TXLPF 0x91435#define RZEBRA1_RXLPF 0xb1436#define RZEBRA1_RXHPFCORNER 0xc1437 1438#define RGLOBALCTRL 01439#define RRTL8256_TXLPF 191440#define RRTL8256_RXLPF 111441#define RRTL8258_TXLPF 0x111442#define RRTL8258_RXLPF 0x131443#define RRTL8258_RSSILPF 0xa1444 1445#define RF_AC 0x001446 1447#define RF_IQADJ_G1 0x011448#define RF_IQADJ_G2 0x021449#define RF_POW_TRSW 0x051450 1451#define RF_GAIN_RX 0x061452#define RF_GAIN_TX 0x071453 1454#define RF_TXM_IDAC 0x081455#define RF_BS_IQGEN 0x0F1456 1457#define RF_MODE1 0x101458#define RF_MODE2 0x111459 1460#define RF_RX_AGC_HP 0x121461#define RF_TX_AGC 0x131462#define RF_BIAS 0x141463#define RF_IPA 0x151464#define RF_POW_ABILITY 0x171465#define RF_MODE_AG 0x181466#define RRFCHANNEL 0x181467#define RF_CHNLBW 0x181468#define RF_TOP 0x191469 1470#define RF_RX_G1 0x1A1471#define RF_RX_G2 0x1B1472 1473#define RF_RX_BB2 0x1C1474#define RF_RX_BB1 0x1D1475 1476#define RF_RCK1 0x1E1477#define RF_RCK2 0x1F1478 1479#define RF_TX_G1 0x201480#define RF_TX_G2 0x211481#define RF_TX_G3 0x221482 1483#define RF_TX_BB1 0x231484#define RF_T_METER 0x241485 1486#define RF_SYN_G1 0x251487#define RF_SYN_G2 0x261488#define RF_SYN_G3 0x271489#define RF_SYN_G4 0x281490#define RF_SYN_G5 0x291491#define RF_SYN_G6 0x2A1492#define RF_SYN_G7 0x2B1493#define RF_SYN_G8 0x2C1494 1495#define RF_RCK_OS 0x301496#define RF_TXPA_G1 0x311497#define RF_TXPA_G2 0x321498#define RF_TXPA_G3 0x331499 1500#define BBBRESETB 0x1001501#define BGLOBALRESETB 0x2001502#define BOFDMTXSTART 0x41503#define BCCKTXSTART 0x81504#define BCRC32DEBUG 0x1001505#define BPMACLOOPBACK 0x101506#define BTXLSIG 0xffffff1507#define BOFDMTXRATE 0xf1508#define BOFDMTXRESERVED 0x101509#define BOFDMTXLENGTH 0x1ffe01510#define BOFDMTXPARITY 0x200001511#define BTXHTSIG1 0xffffff1512#define BTXHTMCSRATE 0x7f1513#define BTXHTBW 0x801514#define BTXHTLENGTH 0xffff001515#define BTXHTSIG2 0xffffff1516#define BTXHTSMOOTHING 0x11517#define BTXHTSOUNDING 0x21518#define BTXHTRESERVED 0x41519#define BTXHTAGGREATION 0x81520#define BTXHTSTBC 0x301521#define BTXHTADVANCECODING 0x401522#define BTXHTSHORTGI 0x801523#define BTXHTNUMBERHT_LTF 0x3001524#define BTXHTCRC8 0x3fc001525#define BCOUNTERRESET 0x100001526#define BNUMOFOFDMTX 0xffff1527#define BNUMOFCCKTX 0xffff00001528#define BTXIDLEINTERVAL 0xffff1529#define BOFDMSERVICE 0xffff00001530#define BTXMACHEADER 0xffffffff1531#define BTXDATAINIT 0xff1532#define BTXHTMODE 0x1001533#define BTXDATATYPE 0x300001534#define BTXRANDOMSEED 0xffffffff1535#define BCCKTXPREAMBLE 0x11536#define BCCKTXSFD 0xffff00001537#define BCCKTXSIG 0xff1538#define BCCKTXSERVICE 0xff001539#define BCCKLENGTHEXT 0x80001540#define BCCKTXLENGHT 0xffff00001541#define BCCKTXCRC16 0xffff1542#define BCCKTXSTATUS 0x11543#define BOFDMTXSTATUS 0x21544#define IS_BB_REG_OFFSET_92S(_offset) \1545 ((_offset >= 0x800) && (_offset <= 0xfff))1546 1547#define BRFMOD 0x11548#define BJAPANMODE 0x21549#define BCCKTXSC 0x301550#define BCCKEN 0x10000001551#define BOFDMEN 0x20000001552 1553#define BOFDMRXADCPHASE 0x100001554#define BOFDMTXDACPHASE 0x400001555#define BXATXAGC 0x3f1556 1557#define BXBTXAGC 0xf001558#define BXCTXAGC 0xf0001559#define BXDTXAGC 0xf00001560 1561#define BPASTART 0xf00000001562#define BTRSTART 0x00f000001563#define BRFSTART 0x0000f0001564#define BBBSTART 0x000000f01565#define BBBCCKSTART 0x0000000f1566#define BPAEND 0xf1567#define BTREND 0x0f0000001568#define BRFEND 0x000f00001569#define BCCAMASK 0x000000f01570#define BR2RCCAMASK 0x00000f001571#define BHSSI_R2TDELAY 0xf80000001572#define BHSSI_T2RDELAY 0xf800001573#define BCONTXHSSI 0x4001574#define BIGFROMCCK 0x2001575#define BAGCADDRESS 0x3f1576#define BRXHPTX 0x70001577#define BRXHP2RX 0x380001578#define BRXHPCCKINI 0xc00001579#define BAGCTXCODE 0xc000001580#define BAGCRXCODE 0x3000001581 1582#define B3WIREDATALENGTH 0x8001583#define B3WIREADDREAALENGTH 0x4001584 1585#define B3WIRERFPOWERDOWN 0x11586#define B5GPAPEPOLARITY 0x400000001587#define B2GPAPEPOLARITY 0x800000001588#define BRFSW_TXDEFAULTANT 0x31589#define BRFSW_TXOPTIONANT 0x301590#define BRFSW_RXDEFAULTANT 0x3001591#define BRFSW_RXOPTIONANT 0x30001592#define BRFSI_3WIREDATA 0x11593#define BRFSI_3WIRECLOCK 0x21594#define BRFSI_3WIRELOAD 0x41595#define BRFSI_3WIRERW 0x81596#define BRFSI_3WIRE 0xf1597 1598#define BRFSI_RFENV 0x101599 1600#define BRFSI_TRSW 0x201601#define BRFSI_TRSWB 0x401602#define BRFSI_ANTSW 0x1001603#define BRFSI_ANTSWB 0x2001604#define BRFSI_PAPE 0x4001605#define BRFSI_PAPE5G 0x8001606#define BBANDSELECT 0x11607#define BHTSIG2_GI 0x801608#define BHTSIG2_SMOOTHING 0x011609#define BHTSIG2_SOUNDING 0x021610#define BHTSIG2_AGGREATON 0x081611#define BHTSIG2_STBC 0x301612#define BHTSIG2_ADVCODING 0x401613#define BHTSIG2_NUMOFHTLTF 0x3001614#define BHTSIG2_CRC8 0x3fc1615#define BHTSIG1_MCS 0x7f1616#define BHTSIG1_BANDWIDTH 0x801617#define BHTSIG1_HTLENGTH 0xffff1618#define BLSIG_RATE 0xf1619#define BLSIG_RESERVED 0x101620#define BLSIG_LENGTH 0x1fffe1621#define BLSIG_PARITY 0x201622#define BCCKRXPHASE 0x41623 1624#define BLSSIREADADDRESS 0x7f8000001625#define BLSSIREADEDGE 0x800000001626 1627#define BLSSIREADBACKDATA 0xfffff1628 1629#define BLSSIREADOKFLAG 0x10001630#define BCCKSAMPLERATE 0x81631#define BREGULATOR0STANDBY 0x11632#define BREGULATORPLLSTANDBY 0x21633#define BREGULATOR1STANDBY 0x41634#define BPLLPOWERUP 0x81635#define BDPLLPOWERUP 0x101636#define BDA10POWERUP 0x201637#define BAD7POWERUP 0x2001638#define BDA6POWERUP 0x20001639#define BXTALPOWERUP 0x40001640#define B40MDCLKPOWERUP 0x80001641#define BDA6DEBUGMODE 0x200001642#define BDA6SWING 0x3800001643 1644#define BADCLKPHASE 0x40000001645#define B80MCLKDELAY 0x180000001646#define BAFEWATCHDOGENABLE 0x200000001647 1648#define BXTALCAP01 0xc00000001649#define BXTALCAP23 0x31650#define BXTALCAP92X 0x0f0000001651#define BXTALCAP 0x0f0000001652 1653#define BINTDIFCLKENABLE 0x4001654#define BEXTSIGCLKENABLE 0x8001655#define BBANDGAP_MBIAS_POWERUP 0x100001656#define BAD11SH_GAIN 0xc00001657#define BAD11NPUT_RANGE 0x7000001658#define BAD110P_CURRENT 0x38000001659#define BLPATH_LOOPBACK 0x40000001660#define BQPATH_LOOPBACK 0x80000001661#define BAFE_LOOPBACK 0x100000001662#define BDA10_SWING 0x7e01663#define BDA10_REVERSE 0x8001664#define BDA_CLK_SOURCE 0x10001665#define BDA7INPUT_RANGE 0x60001666#define BDA7_GAIN 0x380001667#define BDA7OUTPUT_CM_MODE 0x400001668#define BDA7INPUT_CM_MODE 0x3800001669#define BDA7CURRENT 0xc000001670#define BREGULATOR_ADJUST 0x70000001671#define BAD11POWERUP_ATTX 0x11672#define BDA10PS_ATTX 0x101673#define BAD11POWERUP_ATRX 0x1001674#define BDA10PS_ATRX 0x10001675#define BCCKRX_AGC_FORMAT 0x2001676#define BPSDFFT_SAMPLE_POINT 0xc0001677#define BPSD_AVERAGE_NUM 0x30001678#define BIQPATH_CONTROL 0xc001679#define BPSD_FREQ 0x3ff1680#define BPSD_ANTENNA_PATH 0x301681#define BPSD_IQ_SWITCH 0x401682#define BPSD_RX_TRIGGER 0x4000001683#define BPSD_TX_TRIGGER 0x800000001684#define BPSD_SINE_TONE_SCALE 0x7f0000001685#define BPSD_REPORT 0xffff1686 1687#define BOFDM_TXSC 0x300000001688#define BCCK_TXON 0x11689#define BOFDM_TXON 0x21690#define BDEBUG_PAGE 0xfff1691#define BDEBUG_ITEM 0xff1692#define BANTL 0x101693#define BANT_NONHT 0x1001694#define BANT_HT1 0x10001695#define BANT_HT2 0x100001696#define BANT_HT1S1 0x1000001697#define BANT_NONHTS1 0x10000001698 1699#define BCCK_BBMODE 0x31700#define BCCK_TXPOWERSAVING 0x801701#define BCCK_RXPOWERSAVING 0x401702 1703#define BCCK_SIDEBAND 0x101704 1705#define BCCK_SCRAMBLE 0x81706#define BCCK_ANTDIVERSITY 0x80001707#define BCCK_CARRIER_RECOVERY 0x40001708#define BCCK_TXRATE 0x30001709#define BCCK_DCCANCEL 0x08001710#define BCCK_ISICANCEL 0x04001711#define BCCK_MATCH_FILTER 0x02001712#define BCCK_EQUALIZER 0x01001713#define BCCK_PREAMBLE_DETECT 0x8000001714#define BCCK_FAST_FALSECCA 0x4000001715#define BCCK_CH_ESTSTART 0x3000001716#define BCCK_CCA_COUNT 0x0800001717#define BCCK_CS_LIM 0x0700001718#define BCCK_BIST_MODE 0x800000001719#define BCCK_CCAMASK 0x400000001720#define BCCK_TX_DAC_PHASE 0x41721#define BCCK_RX_ADC_PHASE 0x200000001722#define BCCKR_CP_MODE 0x01001723#define BCCK_TXDC_OFFSET 0xf01724#define BCCK_RXDC_OFFSET 0xf1725#define BCCK_CCA_MODE 0xc0001726#define BCCK_FALSECS_LIM 0x3f001727#define BCCK_CS_RATIO 0xc000001728#define BCCK_CORGBIT_SEL 0x3000001729#define BCCK_PD_LIM 0x0f00001730#define BCCK_NEWCCA 0x800000001731#define BCCK_RXHP_OF_IG 0x80001732#define BCCK_RXIG 0x7f001733#define BCCK_LNA_POLARITY 0x8000001734#define BCCK_RX1ST_BAIN 0x7f00001735#define BCCK_RF_EXTEND 0x200000001736#define BCCK_RXAGC_SATLEVEL 0x1f0000001737#define BCCK_RXAGC_SATCOUNT 0xe01738#define BCCKRXRFSETTLE 0x1f1739#define BCCK_FIXED_RXAGC 0x80001740#define BCCK_ANTENNA_POLARITY 0x20001741#define BCCK_TXFILTER_TYPE 0x0c001742#define BCCK_RXAGC_REPORTTYPE 0x03001743#define BCCK_RXDAGC_EN 0x800000001744#define BCCK_RXDAGC_PERIOD 0x200000001745#define BCCK_RXDAGC_SATLEVEL 0x1f0000001746#define BCCK_TIMING_RECOVERY 0x8000001747#define BCCK_TXC0 0x3f00001748#define BCCK_TXC1 0x3f0000001749#define BCCK_TXC2 0x3f1750#define BCCK_TXC3 0x3f001751#define BCCK_TXC4 0x3f00001752#define BCCK_TXC5 0x3f0000001753#define BCCK_TXC6 0x3f1754#define BCCK_TXC7 0x3f001755#define BCCK_DEBUGPORT 0xff00001756#define BCCK_DAC_DEBUG 0x0f0000001757#define BCCK_FALSEALARM_ENABLE 0x80001758#define BCCK_FALSEALARM_READ 0x40001759#define BCCK_TRSSI 0x7f1760#define BCCK_RXAGC_REPORT 0xfe1761#define BCCK_RXREPORT_ANTSEL 0x800000001762#define BCCK_RXREPORT_MFOFF 0x400000001763#define BCCK_RXREPORT_SQLOSS 0x200000001764#define BCCK_RXREPORT_PKTLOSS 0x100000001765#define BCCK_RXREPORT_LOCKEDBIT 0x080000001766#define BCCK_RXREPORT_RATEERROR 0x040000001767#define BCCK_RXREPORT_RXRATE 0x030000001768#define BCCK_RXFA_COUNTER_LOWER 0xff1769#define BCCK_RXFA_COUNTER_UPPER 0xff0000001770#define BCCK_RXHPAGC_START 0xe0001771#define BCCK_RXHPAGC_FINAL 0x1c001772#define BCCK_RXFALSEALARM_ENABLE 0x80001773#define BCCK_FACOUNTER_FREEZE 0x40001774#define BCCK_TXPATH_SEL 0x100000001775#define BCCK_DEFAULT_RXPATH 0xc0000001776#define BCCK_OPTION_RXPATH 0x30000001777 1778#define BNUM_OFSTF 0x31779#define BSHIFT_L 0xc01780#define BGI_TH 0xc1781#define BRXPATH_A 0x11782#define BRXPATH_B 0x21783#define BRXPATH_C 0x41784#define BRXPATH_D 0x81785#define BTXPATH_A 0x11786#define BTXPATH_B 0x21787#define BTXPATH_C 0x41788#define BTXPATH_D 0x81789#define BTRSSI_FREQ 0x2001790#define BADC_BACKOFF 0x30001791#define BDFIR_BACKOFF 0xc0001792#define BTRSSI_LATCH_PHASE 0x100001793#define BRX_LDC_OFFSET 0xff1794#define BRX_QDC_OFFSET 0xff001795#define BRX_DFIR_MODE 0x18000001796#define BRX_DCNF_TYPE 0xe0000001797#define BRXIQIMB_A 0x3ff1798#define BRXIQIMB_B 0xfc001799#define BRXIQIMB_C 0x3f00001800#define BRXIQIMB_D 0xffc000001801#define BDC_DC_NOTCH 0x600001802#define BRXNB_NOTCH 0x1f0000001803#define BPD_TH 0xf1804#define BPD_TH_OPT2 0xc0001805#define BPWED_TH 0x7001806#define BIFMF_WIN_L 0x8001807#define BPD_OPTION 0x10001808#define BMF_WIN_L 0xe0001809#define BBW_SEARCH_L 0x300001810#define BWIN_ENH_L 0xc00001811#define BBW_TH 0x7000001812#define BED_TH2 0x38000001813#define BBW_OPTION 0x40000001814#define BRADIO_TH 0x180000001815#define BWINDOW_L 0xe00000001816#define BSBD_OPTION 0x11817#define BFRAME_TH 0x1c1818#define BFS_OPTION 0x601819#define BDC_SLOPE_CHECK 0x801820#define BFGUARD_COUNTER_DC_L 0xe001821#define BFRAME_WEIGHT_SHORT 0x70001822#define BSUB_TUNE 0xe000001823#define BFRAME_DC_LENGTH 0xe0000001824#define BSBD_START_OFFSET 0x300000001825#define BFRAME_TH_2 0x71826#define BFRAME_GI2_TH 0x381827#define BGI2_SYNC_EN 0x401828#define BSARCH_SHORT_EARLY 0x3001829#define BSARCH_SHORT_LATE 0xc001830#define BSARCH_GI2_LATE 0x700001831#define BCFOANTSUM 0x11832#define BCFOACC 0x21833#define BCFOSTARTOFFSET 0xc1834#define BCFOLOOPBACK 0x701835#define BCFOSUMWEIGHT 0x801836#define BDAGCENABLE 0x100001837#define BTXIQIMB_A 0x3ff1838#define BTXIQIMB_b 0xfc001839#define BTXIQIMB_C 0x3f00001840#define BTXIQIMB_D 0xffc000001841#define BTXIDCOFFSET 0xff1842#define BTXIQDCOFFSET 0xff001843#define BTXDFIRMODE 0x100001844#define BTXPESUDO_NOISEON 0x40000001845#define BTXPESUDO_NOISE_A 0xff1846#define BTXPESUDO_NOISE_B 0xff001847#define BTXPESUDO_NOISE_C 0xff00001848#define BTXPESUDO_NOISE_D 0xff0000001849#define BCCA_DROPOPTION 0x200001850#define BCCA_DROPTHRES 0xfff000001851#define BEDCCA_H 0xf1852#define BEDCCA_L 0xf01853#define BLAMBDA_ED 0x3001854#define BRX_INITIALGAIN 0x7f1855#define BRX_ANTDIV_EN 0x801856#define BRX_AGC_ADDRESS_FOR_LNA 0x7f001857#define BRX_HIGHPOWER_FLOW 0x80001858#define BRX_AGC_FREEZE_THRES 0xc00001859#define BRX_FREEZESTEP_AGC1 0x3000001860#define BRX_FREEZESTEP_AGC2 0xc000001861#define BRX_FREEZESTEP_AGC3 0x30000001862#define BRX_FREEZESTEP_AGC0 0xc0000001863#define BRXRSSI_CMP_EN 0x100000001864#define BRXQUICK_AGCEN 0x200000001865#define BRXAGC_FREEZE_THRES_MODE 0x400000001866#define BRX_OVERFLOW_CHECKTYPE 0x800000001867#define BRX_AGCSHIFT 0x7f1868#define BTRSW_TRI_ONLY 0x801869#define BPOWER_THRES 0x3001870#define BRXAGC_EN 0x11871#define BRXAGC_TOGETHER_EN 0x21872#define BRXAGC_MIN 0x41873#define BRXHP_INI 0x71874#define BRXHP_TRLNA 0x701875#define BRXHP_RSSI 0x7001876#define BRXHP_BBP1 0x70001877#define BRXHP_BBP2 0x700001878#define BRXHP_BBP3 0x7000001879#define BRSSI_H 0x7f00001880#define BRSSI_GEN 0x7f0000001881#define BRXSETTLE_TRSW 0x71882#define BRXSETTLE_LNA 0x381883#define BRXSETTLE_RSSI 0x1c01884#define BRXSETTLE_BBP 0xe001885#define BRXSETTLE_RXHP 0x70001886#define BRXSETTLE_ANTSW_RSSI 0x380001887#define BRXSETTLE_ANTSW 0xc00001888#define BRXPROCESS_TIME_DAGC 0x3000001889#define BRXSETTLE_HSSI 0x4000001890#define BRXPROCESS_TIME_BBPPW 0x8000001891#define BRXANTENNA_POWER_SHIFT 0x30000001892#define BRSSI_TABLE_SELECT 0xc0000001893#define BRXHP_FINAL 0x70000001894#define BRXHPSETTLE_BBP 0x71895#define BRXHTSETTLE_HSSI 0x81896#define BRXHTSETTLE_RXHP 0x701897#define BRXHTSETTLE_BBPPW 0x801898#define BRXHTSETTLE_IDLE 0x3001899#define BRXHTSETTLE_RESERVED 0x1c001900#define BRXHT_RXHP_EN 0x80001901#define BRXAGC_FREEZE_THRES 0x300001902#define BRXAGC_TOGETHEREN 0x400001903#define BRXHTAGC_MIN 0x800001904#define BRXHTAGC_EN 0x1000001905#define BRXHTDAGC_EN 0x2000001906#define BRXHT_RXHP_BBP 0x1c000001907#define BRXHT_RXHP_FINAL 0xe00000001908#define BRXPW_RADIO_TH 0x31909#define BRXPW_RADIO_EN 0x41910#define BRXMF_HOLD 0x38001911#define BRXPD_DELAY_TH1 0x381912#define BRXPD_DELAY_TH2 0x1c01913#define BRXPD_DC_COUNT_MAX 0x6001914#define BRXPD_DELAY_TH 0x80001915#define BRXPROCESS_DELAY 0xf00001916#define BRXSEARCHRANGE_GI2_EARLY 0x7000001917#define BRXFRAME_FUARD_COUNTER_L 0x38000001918#define BRXSGI_GUARD_L 0xc0000001919#define BRXSGI_SEARCH_L 0x300000001920#define BRXSGI_TH 0xc00000001921#define BDFSCNT0 0xff1922#define BDFSCNT1 0xff001923#define BDFSFLAG 0xf00001924#define BMF_WEIGHT_SUM 0x3000001925#define BMINIDX_TH 0x7f0000001926#define BDAFORMAT 0x400001927#define BTXCH_EMU_ENABLE 0x010000001928#define BTRSW_ISOLATION_A 0x7f1929#define BTRSW_ISOLATION_B 0x7f001930#define BTRSW_ISOLATION_C 0x7f00001931#define BTRSW_ISOLATION_D 0x7f0000001932#define BEXT_LNA_GAIN 0x7c001933 1934#define BSTBC_EN 0x41935#define BANTENNA_MAPPING 0x101936#define BNSS 0x201937#define BCFO_ANTSUM_ID 0x2001938#define BPHY_COUNTER_RESET 0x80000001939#define BCFO_REPORT_GET 0x40000001940#define BOFDM_CONTINUE_TX 0x100000001941#define BOFDM_SINGLE_CARRIER 0x200000001942#define BOFDM_SINGLE_TONE 0x400000001943#define BHT_DETECT 0x1001944#define BCFOEN 0x100001945#define BCFOVALUE 0xfff000001946#define BSIGTONE_RE 0x3f1947#define BSIGTONE_IM 0x7f001948#define BCOUNTER_CCA 0xffff1949#define BCOUNTER_PARITYFAIL 0xffff00001950#define BCOUNTER_RATEILLEGAL 0xffff1951#define BCOUNTER_CRC8FAIL 0xffff00001952#define BCOUNTER_MCSNOSUPPORT 0xffff1953#define BCOUNTER_FASTSYNC 0xffff1954#define BSHORTCFO 0xfff1955#define BSHORTCFOT_LENGTH 121956#define BSHORTCFOF_LENGTH 111957#define BLONGCFO 0x7ff1958#define BLONGCFOT_LENGTH 111959#define BLONGCFOF_LENGTH 111960#define BTAILCFO 0x1fff1961#define BTAILCFOT_LENGTH 131962#define BTAILCFOF_LENGTH 121963#define BNOISE_EN_PWDB 0xffff1964#define BCC_POWER_DB 0xffff00001965#define BMOISE_PWDB 0xffff1966#define BPOWERMEAST_LENGTH 101967#define BPOWERMEASF_LENGTH 31968#define BRX_HT_BW 0x11969#define BRXSC 0x61970#define BRX_HT 0x81971#define BNB_INTF_DET_ON 0x11972#define BINTF_WIN_LEN_CFG 0x301973#define BNB_INTF_TH_CFG 0x1c01974#define BRFGAIN 0x3f1975#define BTABLESEL 0x401976#define BTRSW 0x801977#define BRXSNR_A 0xff1978#define BRXSNR_B 0xff001979#define BRXSNR_C 0xff00001980#define BRXSNR_D 0xff0000001981#define BSNR_EVMT_LENGTH 81982#define BSNR_EVMF_LENGTH 11983#define BCSI1ST 0xff1984#define BCSI2ND 0xff001985#define BRXEVM1ST 0xff00001986#define BRXEVM2ND 0xff0000001987#define BSIGEVM 0xff1988#define BPWDB 0xff001989#define BSGIEN 0x100001990 1991#define BSFACTOR_QMA1 0xf1992#define BSFACTOR_QMA2 0xf01993#define BSFACTOR_QMA3 0xf001994#define BSFACTOR_QMA4 0xf0001995#define BSFACTOR_QMA5 0xf00001996#define BSFACTOR_QMA6 0xf00001997#define BSFACTOR_QMA7 0xf000001998#define BSFACTOR_QMA8 0xf0000001999#define BSFACTOR_QMA9 0xf00000002000#define BCSI_SCHEME 0x1000002001 2002#define BNOISE_LVL_TOP_SET 0x32003#define BCHSMOOTH 0x42004#define BCHSMOOTH_CFG1 0x382005#define BCHSMOOTH_CFG2 0x1c02006#define BCHSMOOTH_CFG3 0xe002007#define BCHSMOOTH_CFG4 0x70002008#define BMRCMODE 0x8000002009#define BTHEVMCFG 0x70000002010 2011#define BLOOP_FIT_TYPE 0x12012#define BUPD_CFO 0x402013#define BUPD_CFO_OFFDATA 0x802014#define BADV_UPD_CFO 0x1002015#define BADV_TIME_CTRL 0x8002016#define BUPD_CLKO 0x10002017#define BFC 0x60002018#define BTRACKING_MODE 0x80002019#define BPHCMP_ENABLE 0x100002020#define BUPD_CLKO_LTF 0x200002021#define BCOM_CH_CFO 0x400002022#define BCSI_ESTI_MODE 0x800002023#define BADV_UPD_EQZ 0x1000002024#define BUCHCFG 0x70000002025#define BUPDEQZ 0x80000002026 2027#define BRX_PESUDO_NOISE_ON 0x200000002028#define BRX_PESUDO_NOISE_A 0xff2029#define BRX_PESUDO_NOISE_B 0xff002030#define BRX_PESUDO_NOISE_C 0xff00002031#define BRX_PESUDO_NOISE_D 0xff0000002032#define BRX_PESUDO_NOISESTATE_A 0xffff2033#define BRX_PESUDO_NOISESTATE_B 0xffff00002034#define BRX_PESUDO_NOISESTATE_C 0xffff2035#define BRX_PESUDO_NOISESTATE_D 0xffff00002036 2037#define BZEBRA1_HSSIENABLE 0x82038#define BZEBRA1_TRXCONTROL 0xc002039#define BZEBRA1_TRXGAINSETTING 0x07f2040#define BZEBRA1_RXCOUNTER 0xc002041#define BZEBRA1_TXCHANGEPUMP 0x382042#define BZEBRA1_RXCHANGEPUMP 0x72043#define BZEBRA1_CHANNEL_NUM 0xf802044#define BZEBRA1_TXLPFBW 0x4002045#define BZEBRA1_RXLPFBW 0x6002046 2047#define BRTL8256REG_MODE_CTRL1 0x1002048#define BRTL8256REG_MODE_CTRL0 0x402049#define BRTL8256REG_TXLPFBW 0x182050#define BRTL8256REG_RXLPFBW 0x6002051 2052#define BRTL8258_TXLPFBW 0xc2053#define BRTL8258_RXLPFBW 0xc002054#define BRTL8258_RSSILPFBW 0xc02055 2056#define BBYTE0 0x12057#define BBYTE1 0x22058#define BBYTE2 0x42059#define BBYTE3 0x82060#define BWORD0 0x32061#define BWORD1 0xc2062#define BWORD 0xf2063 2064#define MASKBYTE0 0xff2065#define MASKBYTE1 0xff002066#define MASKBYTE2 0xff00002067#define MASKBYTE3 0xff0000002068#define MASKHWORD 0xffff00002069#define MASKLWORD 0x0000ffff2070#define MASKDWORD 0xffffffff2071#define MASK12BITS 0xfff2072#define MASKH4BITS 0xf00000002073#define MASKOFDM_D 0xffc000002074#define MASKCCK 0x3f3f3f3f2075 2076#define MASK4BITS 0x0f2077#define MASK20BITS 0xfffff2078#define RFREG_OFFSET_MASK 0xfffff2079 2080#define BENABLE 0x12081#define BDISABLE 0x02082 2083#define LEFT_ANTENNA 0x02084#define RIGHT_ANTENNA 0x12085 2086#define TCHECK_TXSTATUS 5002087#define TUPDATE_RXCOUNTER 1002088 2089/* 2 EFUSE_TEST (For RTL8723 partially) */2090#define EFUSE_SEL(x) (((x) & 0x3) << 8)2091#define EFUSE_SEL_MASK 0x3002092#define EFUSE_WIFI_SEL_0 0x02093/* Enable GPIO[9] as WiFi HW PDn source*/2094#define WL_HWPDN_EN BIT(0)2095/* WiFi HW PDn polarity control*/2096#define WL_HWPDN_SL BIT(1)2097 2098#endif2099