249 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright(c) 2009-2014 Realtek Corporation.*/3 4#ifndef __RTL8723BE_DM_H__5#define __RTL8723BE_DM_H__6 7#define MAIN_ANT 08#define AUX_ANT 19#define MAIN_ANT_CG_TRX 110#define AUX_ANT_CG_TRX 011#define MAIN_ANT_CGCS_RX 012#define AUX_ANT_CGCS_RX 113 14#define TXSCALE_TABLE_SIZE 3015 16/*RF REG LIST*/17#define DM_REG_RF_MODE_11N 0x0018#define DM_REG_RF_0B_11N 0x0B19#define DM_REG_CHNBW_11N 0x1820#define DM_REG_T_METER_11N 0x2421#define DM_REG_RF_25_11N 0x2522#define DM_REG_RF_26_11N 0x2623#define DM_REG_RF_27_11N 0x2724#define DM_REG_RF_2B_11N 0x2B25#define DM_REG_RF_2C_11N 0x2C26#define DM_REG_RXRF_A3_11N 0x3C27#define DM_REG_T_METER_92D_11N 0x4228#define DM_REG_T_METER_88E_11N 0x4229 30/*BB REG LIST*/31/*PAGE 8 */32#define DM_REG_BB_CTRL_11N 0x80033#define DM_REG_RF_PIN_11N 0x80434#define DM_REG_PSD_CTRL_11N 0x80835#define DM_REG_TX_ANT_CTRL_11N 0x80C36#define DM_REG_BB_PWR_SAV5_11N 0x81837#define DM_REG_CCK_RPT_FORMAT_11N 0x82438#define DM_REG_RX_DEFUALT_A_11N 0x85839#define DM_REG_RX_DEFUALT_B_11N 0x85A40#define DM_REG_BB_PWR_SAV3_11N 0x85C41#define DM_REG_ANTSEL_CTRL_11N 0x86042#define DM_REG_RX_ANT_CTRL_11N 0x86443#define DM_REG_PIN_CTRL_11N 0x87044#define DM_REG_BB_PWR_SAV1_11N 0x87445#define DM_REG_ANTSEL_PATH_11N 0x87846#define DM_REG_BB_3WIRE_11N 0x88C47#define DM_REG_SC_CNT_11N 0x8C448#define DM_REG_PSD_DATA_11N 0x8B449/*PAGE 9*/50#define DM_REG_ANT_MAPPING1_11N 0x91451#define DM_REG_ANT_MAPPING2_11N 0x91852/*PAGE A*/53#define DM_REG_CCK_ANTDIV_PARA1_11N 0xA0054#define DM_REG_CCK_CCA_11N 0xA0A55#define DM_REG_CCK_ANTDIV_PARA2_11N 0xA0C56#define DM_REG_CCK_ANTDIV_PARA3_11N 0xA1057#define DM_REG_CCK_ANTDIV_PARA4_11N 0xA1458#define DM_REG_CCK_FILTER_PARA1_11N 0xA2259#define DM_REG_CCK_FILTER_PARA2_11N 0xA2360#define DM_REG_CCK_FILTER_PARA3_11N 0xA2461#define DM_REG_CCK_FILTER_PARA4_11N 0xA2562#define DM_REG_CCK_FILTER_PARA5_11N 0xA2663#define DM_REG_CCK_FILTER_PARA6_11N 0xA2764#define DM_REG_CCK_FILTER_PARA7_11N 0xA2865#define DM_REG_CCK_FILTER_PARA8_11N 0xA2966#define DM_REG_CCK_FA_RST_11N 0xA2C67#define DM_REG_CCK_FA_MSB_11N 0xA5868#define DM_REG_CCK_FA_LSB_11N 0xA5C69#define DM_REG_CCK_CCA_CNT_11N 0xA6070#define DM_REG_BB_PWR_SAV4_11N 0xA7471/*PAGE B */72#define DM_REG_LNA_SWITCH_11N 0xB2C73#define DM_REG_PATH_SWITCH_11N 0xB3074#define DM_REG_RSSI_CTRL_11N 0xB3875#define DM_REG_CONFIG_ANTA_11N 0xB6876#define DM_REG_RSSI_BT_11N 0xB9C77/*PAGE C */78#define DM_REG_OFDM_FA_HOLDC_11N 0xC0079#define DM_REG_RX_PATH_11N 0xC0480#define DM_REG_TRMUX_11N 0xC0881#define DM_REG_OFDM_FA_RSTC_11N 0xC0C82#define DM_REG_RXIQI_MATRIX_11N 0xC1483#define DM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C84#define DM_REG_IGI_A_11N 0xC5085#define DM_REG_ANTDIV_PARA2_11N 0xC5486#define DM_REG_IGI_B_11N 0xC5887#define DM_REG_ANTDIV_PARA3_11N 0xC5C88#define DM_REG_BB_PWR_SAV2_11N 0xC7089#define DM_REG_RX_OFF_11N 0xC7C90#define DM_REG_TXIQK_MATRIXA_11N 0xC8091#define DM_REG_TXIQK_MATRIXB_11N 0xC8892#define DM_REG_TXIQK_MATRIXA_LSB2_11N 0xC9493#define DM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C94#define DM_REG_RXIQK_MATRIX_LSB_11N 0xCA095#define DM_REG_ANTDIV_PARA1_11N 0xCA496#define DM_REG_OFDM_FA_TYPE1_11N 0xCF097/*PAGE D */98#define DM_REG_OFDM_FA_RSTD_11N 0xD0099#define DM_REG_OFDM_FA_TYPE2_11N 0xDA0100#define DM_REG_OFDM_FA_TYPE3_11N 0xDA4101#define DM_REG_OFDM_FA_TYPE4_11N 0xDA8102/*PAGE E */103#define DM_REG_TXAGC_A_6_18_11N 0xE00104#define DM_REG_TXAGC_A_24_54_11N 0xE04105#define DM_REG_TXAGC_A_1_MCS32_11N 0xE08106#define DM_REG_TXAGC_A_MCS0_3_11N 0xE10107#define DM_REG_TXAGC_A_MCS4_7_11N 0xE14108#define DM_REG_TXAGC_A_MCS8_11_11N 0xE18109#define DM_REG_TXAGC_A_MCS12_15_11N 0xE1C110#define DM_REG_FPGA0_IQK_11N 0xE28111#define DM_REG_TXIQK_TONE_A_11N 0xE30112#define DM_REG_RXIQK_TONE_A_11N 0xE34113#define DM_REG_TXIQK_PI_A_11N 0xE38114#define DM_REG_RXIQK_PI_A_11N 0xE3C115#define DM_REG_TXIQK_11N 0xE40116#define DM_REG_RXIQK_11N 0xE44117#define DM_REG_IQK_AGC_PTS_11N 0xE48118#define DM_REG_IQK_AGC_RSP_11N 0xE4C119#define DM_REG_BLUETOOTH_11N 0xE6C120#define DM_REG_RX_WAIT_CCA_11N 0xE70121#define DM_REG_TX_CCK_RFON_11N 0xE74122#define DM_REG_TX_CCK_BBON_11N 0xE78123#define DM_REG_OFDM_RFON_11N 0xE7C124#define DM_REG_OFDM_BBON_11N 0xE80125#define DM_REG_TX2RX_11N 0xE84126#define DM_REG_TX2TX_11N 0xE88127#define DM_REG_RX_CCK_11N 0xE8C128#define DM_REG_RX_OFDM_11N 0xED0129#define DM_REG_RX_WAIT_RIFS_11N 0xED4130#define DM_REG_RX2RX_11N 0xED8131#define DM_REG_STANDBY_11N 0xEDC132#define DM_REG_SLEEP_11N 0xEE0133#define DM_REG_PMPD_ANAEN_11N 0xEEC134 135/*MAC REG LIST*/136#define DM_REG_BB_RST_11N 0x02137#define DM_REG_ANTSEL_PIN_11N 0x4C138#define DM_REG_EARLY_MODE_11N 0x4D0139#define DM_REG_RSSI_MONITOR_11N 0x4FE140#define DM_REG_EDCA_VO_11N 0x500141#define DM_REG_EDCA_VI_11N 0x504142#define DM_REG_EDCA_BE_11N 0x508143#define DM_REG_EDCA_BK_11N 0x50C144#define DM_REG_TXPAUSE_11N 0x522145#define DM_REG_RESP_TX_11N 0x6D8146#define DM_REG_ANT_TRAIN_PARA1_11N 0x7b0147#define DM_REG_ANT_TRAIN_PARA2_11N 0x7b4148 149/*DIG Related*/150#define DM_BIT_IGI_11N 0x0000007F151 152#define HAL_DM_DIG_DISABLE BIT(0)153#define HAL_DM_HIPWR_DISABLE BIT(1)154 155#define OFDM_TABLE_LENGTH 43156#define CCK_TABLE_LENGTH 33157 158#define OFDM_TABLE_SIZE 37159#define CCK_TABLE_SIZE 33160 161#define BW_AUTO_SWITCH_HIGH_LOW 25162#define BW_AUTO_SWITCH_LOW_HIGH 30163 164#define DM_DIG_FA_UPPER 0x3e165#define DM_DIG_FA_LOWER 0x1e166#define DM_DIG_FA_TH0 0x200167#define DM_DIG_FA_TH1 0x300168#define DM_DIG_FA_TH2 0x400169 170#define RXPATHSELECTION_SS_TH_LOW 30171#define RXPATHSELECTION_DIFF_TH 18172 173#define DM_RATR_STA_INIT 0174#define DM_RATR_STA_HIGH 1175#define DM_RATR_STA_MIDDLE 2176#define DM_RATR_STA_LOW 3177 178#define CTS2SELF_THVAL 30179#define REGC38_TH 20180 181#define WAIOTTHVAL 25182 183#define TXHIGHPWRLEVEL_NORMAL 0184#define TXHIGHPWRLEVEL_LEVEL1 1185#define TXHIGHPWRLEVEL_LEVEL2 2186#define TXHIGHPWRLEVEL_BT1 3187#define TXHIGHPWRLEVEL_BT2 4188 189#define DM_TYPE_BYFW 0190#define DM_TYPE_BYDRIVER 1191 192#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74193#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67194#define TXPWRTRACK_MAX_IDX 6195 196/* Dynamic ATC switch */197#define ATC_STATUS_OFF 0x0 /* enable */198#define ATC_STATUS_ON 0x1 /* disable */199#define CFO_THRESHOLD_XTAL 10 /* kHz */200#define CFO_THRESHOLD_ATC 80 /* kHz */201 202enum dm_1r_cca_e {203 CCA_1R = 0,204 CCA_2R = 1,205 CCA_MAX = 2,206};207 208enum dm_rf_e {209 RF_SAVE = 0,210 RF_NORMAL = 1,211 RF_MAX = 2,212};213 214enum dm_sw_ant_switch_e {215 ANS_ANTENNA_B = 1,216 ANS_ANTENNA_A = 2,217 ANS_ANTENNA_MAX = 3,218};219 220enum pwr_track_control_method {221 BBSWING,222 TXAGC223};224 225#define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1)226#define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1)227#define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)228#define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1)229#define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1)230#define GET_UNDECORATED_AVERAGE_RSSI(_priv) \231 ((((struct rtl_priv *)(_priv))->mac80211.opmode == \232 NL80211_IFTYPE_ADHOC) ? \233 (((struct rtl_priv *)(_priv))->dm.entry_min_undecoratedsmoothed_pwdb) :\234 (((struct rtl_priv *)(_priv))->dm.undecorated_smoothed_pwdb))235 236void rtl8723be_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw, u8 *pdesc,237 u32 mac_id);238void rtl8723be_dm_ant_sel_statistics(struct ieee80211_hw *hw, u8 antsel_tr_mux,239 u32 mac_id, u32 rx_pwdb_all);240void rtl8723be_dm_fast_antenna_training_callback(unsigned long data);241void rtl8723be_dm_init(struct ieee80211_hw *hw);242void rtl8723be_dm_watchdog(struct ieee80211_hw *hw);243void rtl8723be_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi);244void rtl8723be_dm_check_txpower_tracking(struct ieee80211_hw *hw);245void rtl8723be_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);246void rtl8723be_dm_txpower_track_adjust(struct ieee80211_hw *hw, u8 type,247 u8 *pdirection, u32 *poutwrite_val);248#endif249