114 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright(c) 2009-2014 Realtek Corporation.*/3 4#ifndef __RTL8723BE_PHY_H__5#define __RTL8723BE_PHY_H__6 7/* MAX_TX_COUNT must always set to 4, otherwise read efuse table sequence8 * will be wrong.9 */10#define MAX_TX_COUNT 411#define TX_1S 012#define TX_2S 113#define TX_3S 214#define TX_4S 315 16#define MAX_POWER_INDEX 0x3F17 18#define MAX_PRECMD_CNT 1619#define MAX_RFDEPENDCMD_CNT 1620#define MAX_POSTCMD_CNT 1621 22#define MAX_DOZE_WAITING_TIMES_9x 6423 24#define RT_CANNOT_IO(hw) false25#define HIGHPOWER_RADIOA_ARRAYLEN 2226 27#define TARGET_CHNL_NUM_2G_5G 5928 29#define IQK_ADDA_REG_NUM 1630#define IQK_BB_REG_NUM 931#define MAX_TOLERANCE 532#define IQK_DELAY_TIME 1033#define index_mapping_NUM 1534 35#define APK_BB_REG_NUM 536#define APK_AFE_REG_NUM 1637#define APK_CURVE_REG_NUM 438#define PATH_NUM 139 40#define LOOP_LIMIT 541#define MAX_STALL_TIME 5042#define ANTENNADIVERSITYVALUE 0x8043#define MAX_TXPWR_IDX_NMODE_92S 6344#define RESET_CNT_LIMIT 345 46#define IQK_ADDA_REG_NUM 1647#define IQK_MAC_REG_NUM 448 49#define RF6052_MAX_PATH 250 51#define CT_OFFSET_MAC_ADDR 0X1652 53#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A54#define CT_OFFSET_HT401S_TX_PWR_IDX 0x6055#define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x6656#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x6957#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C58 59#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F60#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x7261 62#define CT_OFFSET_CHANNEL_PLAH 0x7563#define CT_OFFSET_THERMAL_METER 0x7864#define CT_OFFSET_RF_OPTION 0x7965#define CT_OFFSET_VERSION 0x7E66#define CT_OFFSET_CUSTOMER_ID 0x7F67 68#define RTL92C_MAX_PATH_NUM 269 70enum baseband_config_type {71 BASEBAND_CONFIG_PHY_REG = 0,72 BASEBAND_CONFIG_AGC_TAB = 1,73};74 75enum ant_div_type {76 NO_ANTDIV = 0xFF,77 CG_TRX_HW_ANTDIV = 0x01,78 CGCS_RX_HW_ANTDIV = 0x02,79 FIXED_HW_ANTDIV = 0x03,80 CG_TRX_SMART_ANTDIV = 0x04,81 CGCS_RX_SW_ANTDIV = 0x05,82 83};84 85u32 rtl8723be_phy_query_rf_reg(struct ieee80211_hw *hw,86 enum radio_path rfpath,87 u32 regaddr, u32 bitmask);88void rtl8723be_phy_set_rf_reg(struct ieee80211_hw *hw,89 enum radio_path rfpath,90 u32 regaddr, u32 bitmask, u32 data);91bool rtl8723be_phy_mac_config(struct ieee80211_hw *hw);92bool rtl8723be_phy_bb_config(struct ieee80211_hw *hw);93bool rtl8723be_phy_rf_config(struct ieee80211_hw *hw);94void rtl8723be_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);95void rtl8723be_phy_set_txpower_level(struct ieee80211_hw *hw,96 u8 channel);97void rtl8723be_phy_scan_operation_backup(struct ieee80211_hw *hw,98 u8 operation);99void rtl8723be_phy_set_bw_mode_callback(struct ieee80211_hw *hw);100void rtl8723be_phy_set_bw_mode(struct ieee80211_hw *hw,101 enum nl80211_channel_type ch_type);102void rtl8723be_phy_sw_chnl_callback(struct ieee80211_hw *hw);103u8 rtl8723be_phy_sw_chnl(struct ieee80211_hw *hw);104void rtl8723be_phy_iq_calibrate(struct ieee80211_hw *hw,105 bool b_recovery);106void rtl8723be_phy_lc_calibrate(struct ieee80211_hw *hw);107void rtl8723be_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);108bool rtl8723be_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,109 enum radio_path rfpath);110bool rtl8723be_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);111bool rtl8723be_phy_set_rf_power_state(struct ieee80211_hw *hw,112 enum rf_pwrstate rfpwr_state);113#endif114