2274 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright(c) 2009-2014 Realtek Corporation.*/3 4#ifndef __RTL8723BE_REG_H__5#define __RTL8723BE_REG_H__6 7#define TXPKT_BUF_SELECT 0x698#define RXPKT_BUF_SELECT 0xA59#define DISABLE_TRXPKT_BUF_ACCESS 0x010 11#define REG_SYS_ISO_CTRL 0x000012#define REG_SYS_FUNC_EN 0x000213#define REG_APS_FSMCO 0x000414#define REG_SYS_CLKR 0x000815#define REG_9346CR 0x000A16#define REG_EE_VPD 0x000C17#define REG_AFE_MISC 0x001018#define REG_SPS0_CTRL 0x001119#define REG_SPS_OCP_CFG 0x001820#define REG_RSV_CTRL 0x001C21#define REG_RF_CTRL 0x001F22#define REG_LDOA15_CTRL 0x002023#define REG_LDOV12D_CTRL 0x002124#define REG_LDOHCI12_CTRL 0x002225#define REG_LPLDO_CTRL 0x002326#define REG_AFE_XTAL_CTRL 0x002427/* 1.5v for 8188EE test chip, 1.4v for MP chip */28#define REG_AFE_LDO_CTRL 0x002729#define REG_AFE_PLL_CTRL 0x002830#define REG_MAC_PHY_CTRL 0x002c31#define REG_EFUSE_CTRL 0x003032#define REG_EFUSE_TEST 0x003433#define REG_PWR_DATA 0x003834#define REG_CAL_TIMER 0x003C35#define REG_ACLK_MON 0x003E36#define REG_GPIO_MUXCFG 0x004037#define REG_GPIO_IO_SEL 0x004238#define REG_MAC_PINMUX_CFG 0x004339#define REG_GPIO_PIN_CTRL 0x004440#define REG_GPIO_INTM 0x004841#define REG_LEDCFG0 0x004C42#define REG_LEDCFG1 0x004D43#define REG_LEDCFG2 0x004E44#define REG_LEDCFG3 0x004F45#define REG_FSIMR 0x005046#define REG_FSISR 0x005447#define REG_HSIMR 0x005848#define REG_HSISR 0x005c49#define REG_GPIO_PIN_CTRL_2 0x006050#define REG_GPIO_IO_SEL_2 0x006251#define REG_MULTI_FUNC_CTRL 0x006852#define REG_GPIO_OUTPUT 0x006c53#define REG_AFE_XTAL_CTRL_EXT 0x007854#define REG_XCK_OUT_CTRL 0x007c55#define REG_MCUFWDL 0x008056#define REG_WOL_EVENT 0x008157#define REG_MCUTSTCFG 0x008458 59#define REG_HIMR 0x00B060#define REG_HISR 0x00B461#define REG_HIMRE 0x00B862#define REG_HISRE 0x00BC63#define REG_PMC_DBG_CTRL2 0x00CC64 65#define REG_EFUSE_ACCESS 0x00CF66 67#define REG_BIST_SCAN 0x00D068#define REG_BIST_RPT 0x00D469#define REG_BIST_ROM_RPT 0x00D870#define REG_USB_SIE_INTF 0x00E071#define REG_PCIE_MIO_INTF 0x00E472#define REG_PCIE_MIO_INTD 0x00E873#define REG_HPON_FSM 0x00EC74#define REG_SYS_CFG 0x00F075#define REG_GPIO_OUTSTS 0x00F476#define REG_MAC_PHY_CTRL_NORMAL 0x00F877#define REG_SYS_CFG1 0x00FC78#define REG_ROM_VERSION 0x00FD79 80#define REG_CR 0x010081#define REG_PBP 0x010482#define REG_PKT_BUFF_ACCESS_CTRL 0x010683#define REG_TRXDMA_CTRL 0x010C84#define REG_TRXFF_BNDY 0x011485#define REG_TRXFF_STATUS 0x011886#define REG_RXFF_PTR 0x011C87 88#define REG_CPWM 0x012F89#define REG_FWIMR 0x013090#define REG_FWISR 0x013491#define REG_PKTBUF_DBG_CTRL 0x014092#define REG_PKTBUF_DBG_DATA_L 0x014493#define REG_PKTBUF_DBG_DATA_H 0x014894#define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL + 2)95 96#define REG_TC0_CTRL 0x015097#define REG_TC1_CTRL 0x015498#define REG_TC2_CTRL 0x015899#define REG_TC3_CTRL 0x015C100#define REG_TC4_CTRL 0x0160101#define REG_TCUNIT_BASE 0x0164102#define REG_MBIST_START 0x0174103#define REG_MBIST_DONE 0x0178104#define REG_MBIST_FAIL 0x017C105#define REG_32K_CTRL 0x0194106#define REG_C2HEVT_MSG_NORMAL 0x01A0107#define REG_C2HEVT_CLEAR 0x01AF108#define REG_C2HEVT_MSG_TEST 0x01B8109#define REG_MCUTST_1 0x01c0110#define REG_FMETHR 0x01C8111#define REG_HMETFR 0x01CC112#define REG_HMEBOX_0 0x01D0113#define REG_HMEBOX_1 0x01D4114#define REG_HMEBOX_2 0x01D8115#define REG_HMEBOX_3 0x01DC116 117#define REG_LLT_INIT 0x01E0118#define REG_BB_ACCEESS_CTRL 0x01E8119#define REG_BB_ACCESS_DATA 0x01EC120 121#define REG_HMEBOX_EXT_0 0x01F0122#define REG_HMEBOX_EXT_1 0x01F4123#define REG_HMEBOX_EXT_2 0x01F8124#define REG_HMEBOX_EXT_3 0x01FC125 126#define REG_RQPN 0x0200127#define REG_FIFOPAGE 0x0204128#define REG_TDECTRL 0x0208129#define REG_TXDMA_OFFSET_CHK 0x020C130#define REG_TXDMA_STATUS 0x0210131#define REG_RQPN_NPQ 0x0214132 133#define REG_RXDMA_AGG_PG_TH 0x0280134/* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */135#define REG_FW_UPD_RDPTR 0x0284136/* Control the RX DMA.*/137#define REG_RXDMA_CONTROL 0x0286138/* The number of packets in RXPKTBUF. */139#define REG_RXPKT_NUM 0x0287140 141#define REG_PCIE_CTRL_REG 0x0300142#define REG_INT_MIG 0x0304143#define REG_BCNQ_DESA 0x0308144#define REG_HQ_DESA 0x0310145#define REG_MGQ_DESA 0x0318146#define REG_VOQ_DESA 0x0320147#define REG_VIQ_DESA 0x0328148#define REG_BEQ_DESA 0x0330149#define REG_BKQ_DESA 0x0338150#define REG_RX_DESA 0x0340151 152#define REG_DBI_WDATA 0x0348153#define REG_DBI_RDATA 0x034C154#define REG_DBI_CTRL 0x0350155#define REG_DBI_ADDR 0x0350156#define REG_DBI_FLAG 0x0352157#define REG_MDIO_WDATA 0x0354158#define REG_MDIO_RDATA 0x0356159#define REG_MDIO_CTL 0x0358160#define REG_DBG_SEL 0x0360161#define REG_PCIE_HRPWM 0x0361162#define REG_PCIE_HCPWM 0x0363163#define REG_UART_CTRL 0x0364164#define REG_WATCH_DOG 0x0368165#define REG_UART_TX_DESA 0x0370166#define REG_UART_RX_DESA 0x0378167 168#define REG_HDAQ_DESA_NODEF 0x0000169#define REG_CMDQ_DESA_NODEF 0x0000170 171#define REG_VOQ_INFORMATION 0x0400172#define REG_VIQ_INFORMATION 0x0404173#define REG_BEQ_INFORMATION 0x0408174#define REG_BKQ_INFORMATION 0x040C175#define REG_MGQ_INFORMATION 0x0410176#define REG_HGQ_INFORMATION 0x0414177#define REG_BCNQ_INFORMATION 0x0418178#define REG_TXPKT_EMPTY 0x041A179 180#define REG_CPU_MGQ_INFORMATION 0x041C181#define REG_FWHW_TXQ_CTRL 0x0420182#define REG_HWSEQ_CTRL 0x0423183#define REG_TXPKTBUF_BCNQ_BDNY 0x0424184#define REG_TXPKTBUF_MGQ_BDNY 0x0425185#define REG_MULTI_BCNQ_EN 0x0426186#define REG_MULTI_BCNQ_OFFSET 0x0427187#define REG_SPEC_SIFS 0x0428188#define REG_RL 0x042A189#define REG_DARFRC 0x0430190#define REG_RARFRC 0x0438191#define REG_RRSR 0x0440192#define REG_ARFR0 0x0444193#define REG_ARFR1 0x044C194#define REG_AMPDU_MAX_TIME 0x0456195#define REG_AGGLEN_LMT 0x0458196#define REG_AMPDU_MIN_SPACE 0x045C197#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D198#define REG_FAST_EDCA_CTRL 0x0460199#define REG_RD_RESP_PKT_TH 0x0463200#define REG_INIRTS_RATE_SEL 0x0480201#define REG_INIDATA_RATE_SEL 0x0484202#define REG_POWER_STATUS 0x04A4203#define REG_POWER_STAGE1 0x04B4204#define REG_POWER_STAGE2 0x04B8205#define REG_PKT_LIFE_TIME 0x04C0206#define REG_STBC_SETTING 0x04C4207#define REG_HT_SINGLE_AMPDU 0x04C7208 209#define REG_PROT_MODE_CTRL 0x04C8210#define REG_MAX_AGGR_NUM 0x04CA211#define REG_BAR_MODE_CTRL 0x04CC212#define REG_RA_TRY_RATE_AGG_LMT 0x04CF213#define REG_EARLY_MODE_CONTROL 0x04D0214#define REG_NQOS_SEQ 0x04DC215#define REG_QOS_SEQ 0x04DE216#define REG_NEED_CPU_HANDLE 0x04E0217#define REG_PKT_LOSE_RPT 0x04E1218#define REG_PTCL_ERR_STATUS 0x04E2219#define REG_TX_RPT_CTRL 0x04EC220#define REG_TX_RPT_TIME 0x04F0221#define REG_DUMMY 0x04FC222 223#define REG_EDCA_VO_PARAM 0x0500224#define REG_EDCA_VI_PARAM 0x0504225#define REG_EDCA_BE_PARAM 0x0508226#define REG_EDCA_BK_PARAM 0x050C227#define REG_BCNTCFG 0x0510228#define REG_PIFS 0x0512229#define REG_RDG_PIFS 0x0513230#define REG_SIFS_CTX 0x0514231#define REG_SIFS_TRX 0x0516232#define REG_AGGR_BREAK_TIME 0x051A233#define REG_SLOT 0x051B234#define REG_TX_PTCL_CTRL 0x0520235#define REG_TXPAUSE 0x0522236#define REG_DIS_TXREQ_CLR 0x0523237#define REG_RD_CTRL 0x0524238#define REG_TBTT_PROHIBIT 0x0540239#define REG_RD_NAV_NXT 0x0544240#define REG_NAV_PROT_LEN 0x0546241#define REG_BCN_CTRL 0x0550242#define REG_MBID_NUM 0x0552243#define REG_DUAL_TSF_RST 0x0553244#define REG_BCN_INTERVAL 0x0554245#define REG_MBSSID_BCN_SPACE 0x0554246#define REG_DRVERLYINT 0x0558247#define REG_BCNDMATIM 0x0559248#define REG_ATIMWND 0x055A249#define REG_USTIME_TSF 0x055C250#define REG_BCN_MAX_ERR 0x055D251#define REG_RXTSF_OFFSET_CCK 0x055E252#define REG_RXTSF_OFFSET_OFDM 0x055F253#define REG_TSFTR 0x0560254#define REG_INIT_TSFTR 0x0564255#define REG_SECONDARY_CCA_CTRL 0x0577256#define REG_PSTIMER 0x0580257#define REG_TIMER0 0x0584258#define REG_TIMER1 0x0588259#define REG_ACMHWCTRL 0x05C0260#define REG_ACMRSTCTRL 0x05C1261#define REG_ACMAVG 0x05C2262#define REG_VO_ADMTIME 0x05C4263#define REG_VI_ADMTIME 0x05C6264#define REG_BE_ADMTIME 0x05C8265#define REG_EDCA_RANDOM_GEN 0x05CC266#define REG_SCH_TXCMD 0x05D0267 268#define REG_APSD_CTRL 0x0600269#define REG_BWOPMODE 0x0603270#define REG_TCR 0x0604271#define REG_RCR 0x0608272#define REG_RX_PKT_LIMIT 0x060C273#define REG_RX_DLK_TIME 0x060D274#define REG_RX_DRVINFO_SZ 0x060F275 276#define REG_MACID 0x0610277#define REG_BSSID 0x0618278#define REG_MAR 0x0620279#define REG_MBIDCAMCFG 0x0628280 281#define REG_USTIME_EDCA 0x0638282#define REG_MAC_SPEC_SIFS 0x063A283#define REG_RESP_SIFS_CCK 0x063C284#define REG_RESP_SIFS_OFDM 0x063E285#define REG_ACKTO 0x0640286#define REG_CTS2TO 0x0641287#define REG_EIFS 0x0642288 289#define REG_NAV_CTRL 0x0650290#define REG_NAV_UPPER 0x0652291#define REG_BACAMCMD 0x0654292#define REG_BACAMCONTENT 0x0658293#define REG_LBDLY 0x0660294#define REG_FWDLY 0x0661295#define REG_RXERR_RPT 0x0664296#define REG_TRXPTCL_CTL 0x0668297 298#define REG_CAMCMD 0x0670299#define REG_CAMWRITE 0x0674300#define REG_CAMREAD 0x0678301#define REG_CAMDBG 0x067C302#define REG_SECCFG 0x0680303 304#define REG_WOW_CTRL 0x0690305#define REG_PSSTATUS 0x0691306#define REG_PS_RX_INFO 0x0692307#define REG_UAPSD_TID 0x0693308#define REG_LPNAV_CTRL 0x0694309#define REG_WKFMCAM_NUM 0x0698310#define REG_WKFMCAM_RWD 0x069C311#define REG_RXFLTMAP0 0x06A0312#define REG_RXFLTMAP1 0x06A2313#define REG_RXFLTMAP2 0x06A4314#define REG_BCN_PSR_RPT 0x06A8315#define REG_CALB32K_CTRL 0x06AC316#define REG_PKT_MON_CTRL 0x06B4317#define REG_BT_COEX_TABLE 0x06C0318#define REG_WMAC_RESP_TXINFO 0x06D8319 320#define REG_USB_INFO 0xFE17321#define REG_USB_SPECIAL_OPTION 0xFE55322#define REG_USB_DMA_AGG_TO 0xFE5B323#define REG_USB_AGG_TO 0xFE5C324#define REG_USB_AGG_TH 0xFE5D325 326#define REG_TEST_USB_TXQS 0xFE48327#define REG_TEST_SIE_VID 0xFE60328#define REG_TEST_SIE_PID 0xFE62329#define REG_TEST_SIE_OPTIONAL 0xFE64330#define REG_TEST_SIE_CHIRP_K 0xFE65331#define REG_TEST_SIE_PHY 0xFE66332#define REG_TEST_SIE_MAC_ADDR 0xFE70333#define REG_TEST_SIE_STRING 0xFE80334 335#define REG_NORMAL_SIE_VID 0xFE60336#define REG_NORMAL_SIE_PID 0xFE62337#define REG_NORMAL_SIE_OPTIONAL 0xFE64338#define REG_NORMAL_SIE_EP 0xFE65339#define REG_NORMAL_SIE_PHY 0xFE68340#define REG_NORMAL_SIE_MAC_ADDR 0xFE70341#define REG_NORMAL_SIE_STRING 0xFE80342 343#define CR9346 REG_9346CR344#define MSR (REG_CR + 2)345#define ISR REG_HISR346#define TSFR REG_TSFTR347 348#define MACIDR0 REG_MACID349#define MACIDR4 (REG_MACID + 4)350 351#define PBP REG_PBP352 353#define IDR0 MACIDR0354#define IDR4 MACIDR4355 356#define UNUSED_REGISTER 0x1BF357#define DCAM UNUSED_REGISTER358#define PSR UNUSED_REGISTER359#define BBADDR UNUSED_REGISTER360#define PHYDATAR UNUSED_REGISTER361 362#define INVALID_BBRF_VALUE 0x12345678363 364#define MAX_MSS_DENSITY_2T 0x13365#define MAX_MSS_DENSITY_1T 0x0A366 367#define CMDEEPROM_EN BIT(5)368#define CMDEEPROM_SEL BIT(4)369#define CMD9346CR_9356SEL BIT(4)370#define AUTOLOAD_EEPROM (CMDEEPROM_EN | CMDEEPROM_SEL)371#define AUTOLOAD_EFUSE CMDEEPROM_EN372 373#define GPIOSEL_GPIO 0374#define GPIOSEL_ENBT BIT(5)375 376#define GPIO_IN REG_GPIO_PIN_CTRL377#define GPIO_OUT (REG_GPIO_PIN_CTRL + 1)378#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL + 2)379#define GPIO_MOD (REG_GPIO_PIN_CTRL + 3)380 381/* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */382#define HSIMR_GPIO12_0_INT_EN BIT(0)383#define HSIMR_SPS_OCP_INT_EN BIT(5)384#define HSIMR_RON_INT_EN BIT(6)385#define HSIMR_PDN_INT_EN BIT(7)386#define HSIMR_GPIO9_INT_EN BIT(25)387 388/* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */389#define HSISR_GPIO12_0_INT BIT(0)390#define HSISR_SPS_OCP_INT BIT(5)391#define HSISR_RON_INT_EN BIT(6)392#define HSISR_PDNINT BIT(7)393#define HSISR_GPIO9_INT BIT(25)394 395#define MSR_NOLINK 0x00396#define MSR_ADHOC 0x01397#define MSR_INFRA 0x02398#define MSR_AP 0x03399 400#define RRSR_RSC_OFFSET 21401#define RRSR_SHORT_OFFSET 23402#define RRSR_RSC_BW_40M 0x600000403#define RRSR_RSC_UPSUBCHNL 0x400000404#define RRSR_RSC_LOWSUBCHNL 0x200000405#define RRSR_SHORT 0x800000406#define RRSR_1M BIT(0)407#define RRSR_2M BIT(1)408#define RRSR_5_5M BIT(2)409#define RRSR_11M BIT(3)410#define RRSR_6M BIT(4)411#define RRSR_9M BIT(5)412#define RRSR_12M BIT(6)413#define RRSR_18M BIT(7)414#define RRSR_24M BIT(8)415#define RRSR_36M BIT(9)416#define RRSR_48M BIT(10)417#define RRSR_54M BIT(11)418#define RRSR_MCS0 BIT(12)419#define RRSR_MCS1 BIT(13)420#define RRSR_MCS2 BIT(14)421#define RRSR_MCS3 BIT(15)422#define RRSR_MCS4 BIT(16)423#define RRSR_MCS5 BIT(17)424#define RRSR_MCS6 BIT(18)425#define RRSR_MCS7 BIT(19)426#define BRSR_ACKSHORTPMB BIT(23)427 428#define RATR_1M 0x00000001429#define RATR_2M 0x00000002430#define RATR_55M 0x00000004431#define RATR_11M 0x00000008432#define RATR_6M 0x00000010433#define RATR_9M 0x00000020434#define RATR_12M 0x00000040435#define RATR_18M 0x00000080436#define RATR_24M 0x00000100437#define RATR_36M 0x00000200438#define RATR_48M 0x00000400439#define RATR_54M 0x00000800440#define RATR_MCS0 0x00001000441#define RATR_MCS1 0x00002000442#define RATR_MCS2 0x00004000443#define RATR_MCS3 0x00008000444#define RATR_MCS4 0x00010000445#define RATR_MCS5 0x00020000446#define RATR_MCS6 0x00040000447#define RATR_MCS7 0x00080000448#define RATR_MCS8 0x00100000449#define RATR_MCS9 0x00200000450#define RATR_MCS10 0x00400000451#define RATR_MCS11 0x00800000452#define RATR_MCS12 0x01000000453#define RATR_MCS13 0x02000000454#define RATR_MCS14 0x04000000455#define RATR_MCS15 0x08000000456 457#define RATE_1M BIT(0)458#define RATE_2M BIT(1)459#define RATE_5_5M BIT(2)460#define RATE_11M BIT(3)461#define RATE_6M BIT(4)462#define RATE_9M BIT(5)463#define RATE_12M BIT(6)464#define RATE_18M BIT(7)465#define RATE_24M BIT(8)466#define RATE_36M BIT(9)467#define RATE_48M BIT(10)468#define RATE_54M BIT(11)469#define RATE_MCS0 BIT(12)470#define RATE_MCS1 BIT(13)471#define RATE_MCS2 BIT(14)472#define RATE_MCS3 BIT(15)473#define RATE_MCS4 BIT(16)474#define RATE_MCS5 BIT(17)475#define RATE_MCS6 BIT(18)476#define RATE_MCS7 BIT(19)477#define RATE_MCS8 BIT(20)478#define RATE_MCS9 BIT(21)479#define RATE_MCS10 BIT(22)480#define RATE_MCS11 BIT(23)481#define RATE_MCS12 BIT(24)482#define RATE_MCS13 BIT(25)483#define RATE_MCS14 BIT(26)484#define RATE_MCS15 BIT(27)485 486#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M)487#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M |\488 RATR_24M | RATR_36M | RATR_48M | RATR_54M)489#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 |\490 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 |\491 RATR_MCS6 | RATR_MCS7)492#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 |\493 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 |\494 RATR_MCS14 | RATR_MCS15)495 496#define BW_OPMODE_20MHZ BIT(2)497#define BW_OPMODE_5G BIT(1)498#define BW_OPMODE_11J BIT(0)499 500#define CAM_VALID BIT(15)501#define CAM_NOTVALID 0x0000502#define CAM_USEDK BIT(5)503 504#define CAM_NONE 0x0505#define CAM_WEP40 0x01506#define CAM_TKIP 0x02507#define CAM_AES 0x04508#define CAM_WEP104 0x05509 510#define TOTAL_CAM_ENTRY 32511#define HALF_CAM_ENTRY 16512 513#define CAM_WRITE BIT(16)514#define CAM_READ 0x00000000515#define CAM_POLLINIG BIT(31)516 517#define SCR_USEDK 0x01518#define SCR_TXSEC_ENABLE 0x02519#define SCR_RXSEC_ENABLE 0x04520 521#define WOW_PMEN BIT(0)522#define WOW_WOMEN BIT(1)523#define WOW_MAGIC BIT(2)524#define WOW_UWF BIT(3)525 526/*********************************************527* 8723BE IMR/ISR bits528*********************************************529*/530#define IMR_DISABLED 0x0531/* IMR DW0(0x0060-0063) Bit 0-31 */532#define IMR_TXCCK BIT(30) /* TXRPT interrupt when533 * CCX bit of the packet is set534 */535#define IMR_PSTIMEOUT BIT(29) /* Power Save Time Out Interrupt */536#define IMR_GTINT4 BIT(28) /* When GTIMER4 expires,537 * this bit is set to 1538 */539#define IMR_GTINT3 BIT(27) /* When GTIMER3 expires,540 * this bit is set to 1541 */542#define IMR_TBDER BIT(26) /* Transmit Beacon0 Error */543#define IMR_TBDOK BIT(25) /* Transmit Beacon0 OK */544#define IMR_TSF_BIT32_TOGGLE BIT(24) /* TSF Timer BIT32 toggle545 * indication interrupt546 */547#define IMR_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */548#define IMR_BCNDOK0 BIT(16) /* Beacon Queue DMA OK0 */549#define IMR_HSISR_IND_ON_INT BIT(15) /* HSISR Indicator (HSIMR & HSISR is550 * true, this bit is set to 1)551 */552#define IMR_BCNDMAINT_E BIT(14) /* Beacon DMA Interrupt553 * Extension for Win7554 */555#define IMR_ATIMEND BIT(12) /* CTWidnow End or ATIM Window End */556#define IMR_HISR1_IND_INT BIT(11) /* HISR1 Indicator (HISR1 & HIMR1 is557 * true, this bit is set to 1)558 */559#define IMR_C2HCMD BIT(10) /* CPU to Host Command INT Status,560 * Write 1 clear561 */562#define IMR_CPWM2 BIT(9) /* CPU power Mode exchange INT Status,563 * Write 1 clear564 */565#define IMR_CPWM BIT(8) /* CPU power Mode exchange INT Status,566 * Write 1 clear567 */568#define IMR_HIGHDOK BIT(7) /* High Queue DMA OK */569#define IMR_MGNTDOK BIT(6) /* Management Queue DMA OK */570#define IMR_BKDOK BIT(5) /* AC_BK DMA OK */571#define IMR_BEDOK BIT(4) /* AC_BE DMA OK */572#define IMR_VIDOK BIT(3) /* AC_VI DMA OK */573#define IMR_VODOK BIT(2) /* AC_VO DMA OK */574#define IMR_RDU BIT(1) /* Rx Descriptor Unavailable */575#define IMR_ROK BIT(0) /* Receive DMA OK */576 577/* IMR DW1(0x00B4-00B7) Bit 0-31 */578#define IMR_BCNDMAINT7 BIT(27) /* Beacon DMA Interrupt 7 */579#define IMR_BCNDMAINT6 BIT(26) /* Beacon DMA Interrupt 6 */580#define IMR_BCNDMAINT5 BIT(25) /* Beacon DMA Interrupt 5 */581#define IMR_BCNDMAINT4 BIT(24) /* Beacon DMA Interrupt 4 */582#define IMR_BCNDMAINT3 BIT(23) /* Beacon DMA Interrupt 3 */583#define IMR_BCNDMAINT2 BIT(22) /* Beacon DMA Interrupt 2 */584#define IMR_BCNDMAINT1 BIT(21) /* Beacon DMA Interrupt 1 */585#define IMR_BCNDOK7 BIT(20) /* Beacon Queue DMA OK Interrup 7 */586#define IMR_BCNDOK6 BIT(19) /* Beacon Queue DMA OK Interrup 6 */587#define IMR_BCNDOK5 BIT(18) /* Beacon Queue DMA OK Interrup 5 */588#define IMR_BCNDOK4 BIT(17) /* Beacon Queue DMA OK Interrup 4 */589#define IMR_BCNDOK3 BIT(16) /* Beacon Queue DMA OK Interrup 3 */590#define IMR_BCNDOK2 BIT(15) /* Beacon Queue DMA OK Interrup 2 */591#define IMR_BCNDOK1 BIT(14) /* Beacon Queue DMA OK Interrup 1 */592#define IMR_ATIMEND_E BIT(13) /* ATIM Window End Extension for Win7 */593#define IMR_TXERR BIT(11) /* Tx Error Flag Interrupt Status,594 * write 1 clear.595 */596#define IMR_RXERR BIT(10) /* Rx Error Flag INT Status,597 * Write 1 clear598 */599#define IMR_TXFOVW BIT(9) /* Transmit FIFO Overflow */600#define IMR_RXFOVW BIT(8) /* Receive FIFO Overflow */601 602#define HWSET_MAX_SIZE 512603#define EFUSE_MAX_SECTION 64604#define EFUSE_REAL_CONTENT_LEN 256605#define EFUSE_OOB_PROTECT_BYTES 18 /* PG data exclude header,606 * dummy 7 bytes frome CP test607 * and reserved 1byte.608 */609 610#define EEPROM_DEFAULT_TSSI 0x0611#define EEPROM_DEFAULT_TXPOWERDIFF 0x0612#define EEPROM_DEFAULT_CRYSTALCAP 0x5613#define EEPROM_DEFAULT_BOARDTYPE 0x02614#define EEPROM_DEFAULT_TXPOWER 0x1010615#define EEPROM_DEFAULT_HT2T_TXPWR 0x10616 617#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3618#define EEPROM_DEFAULT_THERMALMETER 0x18619#define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0620#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5621#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22622#define EEPROM_DEFAULT_HT40_2SDIFF 0x0623#define EEPROM_DEFAULT_HT20_DIFF 2624#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3625#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0626#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0627 628#define RF_OPTION1 0x79629#define RF_OPTION2 0x7A630#define RF_OPTION3 0x7B631#define EEPROM_RF_BT_SETTING_8723B 0xC3632 633#define EEPROM_DEFAULT_PID 0x1234634#define EEPROM_DEFAULT_VID 0x5678635#define EEPROM_DEFAULT_CUSTOMERID 0xAB636#define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD637#define EEPROM_DEFAULT_VERSION 0638 639#define EEPROM_CHANNEL_PLAN_FCC 0x0640#define EEPROM_CHANNEL_PLAN_IC 0x1641#define EEPROM_CHANNEL_PLAN_ETSI 0x2642#define EEPROM_CHANNEL_PLAN_SPAIN 0x3643#define EEPROM_CHANNEL_PLAN_FRANCE 0x4644#define EEPROM_CHANNEL_PLAN_MKK 0x5645#define EEPROM_CHANNEL_PLAN_MKK1 0x6646#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7647#define EEPROM_CHANNEL_PLAN_TELEC 0x8648#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9649#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA650#define EEPROM_CHANNEL_PLAN_NCC 0xB651#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80652 653#define EEPROM_CID_DEFAULT 0x0654#define EEPROM_CID_TOSHIBA 0x4655#define EEPROM_CID_CCX 0x10656#define EEPROM_CID_QMI 0x0D657#define EEPROM_CID_WHQL 0xFE658 659#define RTL8723BE_EEPROM_ID 0x8129660 661#define EEPROM_HPON 0x02662#define EEPROM_CLK 0x06663#define EEPROM_TESTR 0x08664 665#define EEPROM_TXPOWERCCK 0x10666#define EEPROM_TXPOWERHT40_1S 0x16667#define EEPROM_TXPOWERHT20DIFF 0x1B668#define EEPROM_TXPOWER_OFDMDIFF 0x1B669 670#define EEPROM_TX_PWR_INX 0x10671 672#define EEPROM_CHANNELPLAN 0xB8673#define EEPROM_XTAL_8723BE 0xB9674#define EEPROM_THERMAL_METER_88E 0xBA675#define EEPROM_IQK_LCK_88E 0xBB676 677#define EEPROM_RF_BOARD_OPTION_88E 0xC1678#define EEPROM_RF_FEATURE_OPTION_88E 0xC2679#define EEPROM_RF_BT_SETTING_88E 0xC3680#define EEPROM_VERSION 0xC4681#define EEPROM_CUSTOMER_ID 0xC5682#define EEPROM_RF_ANTENNA_OPT_88E 0xC9683 684#define EEPROM_MAC_ADDR 0xD0685#define EEPROM_VID 0xD6686#define EEPROM_DID 0xD8687#define EEPROM_SVID 0xDA688#define EEPROM_SMID 0xDC689 690#define STOPBECON BIT(6)691#define STOPHIGHT BIT(5)692#define STOPMGT BIT(4)693#define STOPVO BIT(3)694#define STOPVI BIT(2)695#define STOPBE BIT(1)696#define STOPBK BIT(0)697 698#define RCR_APPFCS BIT(31)699#define RCR_APP_MIC BIT(30)700#define RCR_APP_ICV BIT(29)701#define RCR_APP_PHYST_RXFF BIT(28)702#define RCR_APP_BA_SSN BIT(27)703#define RCR_ENMBID BIT(24)704#define RCR_LSIGEN BIT(23)705#define RCR_MFBEN BIT(22)706#define RCR_HTC_LOC_CTRL BIT(14)707#define RCR_AMF BIT(13)708#define RCR_ACF BIT(12)709#define RCR_ADF BIT(11)710#define RCR_AICV BIT(9)711#define RCR_ACRC32 BIT(8)712#define RCR_CBSSID_BCN BIT(7)713#define RCR_CBSSID_DATA BIT(6)714#define RCR_CBSSID RCR_CBSSID_DATA715#define RCR_APWRMGT BIT(5)716#define RCR_ADD3 BIT(4)717#define RCR_AB BIT(3)718#define RCR_AM BIT(2)719#define RCR_APM BIT(1)720#define RCR_AAP BIT(0)721#define RCR_MXDMA_OFFSET 8722#define RCR_FIFO_OFFSET 13723 724#define RSV_CTRL 0x001C725#define RD_CTRL 0x0524726 727#define REG_USB_INFO 0xFE17728#define REG_USB_SPECIAL_OPTION 0xFE55729#define REG_USB_DMA_AGG_TO 0xFE5B730#define REG_USB_AGG_TO 0xFE5C731#define REG_USB_AGG_TH 0xFE5D732 733#define REG_USB_VID 0xFE60734#define REG_USB_PID 0xFE62735#define REG_USB_OPTIONAL 0xFE64736#define REG_USB_CHIRP_K 0xFE65737#define REG_USB_PHY 0xFE66738#define REG_USB_MAC_ADDR 0xFE70739#define REG_USB_HRPWM 0xFE58740#define REG_USB_HCPWM 0xFE57741 742#define SW18_FPWM BIT(3)743 744#define ISO_MD2PP BIT(0)745#define ISO_UA2USB BIT(1)746#define ISO_UD2CORE BIT(2)747#define ISO_PA2PCIE BIT(3)748#define ISO_PD2CORE BIT(4)749#define ISO_IP2MAC BIT(5)750#define ISO_DIOP BIT(6)751#define ISO_DIOE BIT(7)752#define ISO_EB2CORE BIT(8)753#define ISO_DIOR BIT(9)754 755#define PWC_EV25V BIT(14)756#define PWC_EV12V BIT(15)757 758#define FEN_BBRSTB BIT(0)759#define FEN_BB_GLB_RSTN BIT(1)760#define FEN_USBA BIT(2)761#define FEN_UPLL BIT(3)762#define FEN_USBD BIT(4)763#define FEN_DIO_PCIE BIT(5)764#define FEN_PCIEA BIT(6)765#define FEN_PPLL BIT(7)766#define FEN_PCIED BIT(8)767#define FEN_DIOE BIT(9)768#define FEN_CPUEN BIT(10)769#define FEN_DCORE BIT(11)770#define FEN_ELDR BIT(12)771#define FEN_DIO_RF BIT(13)772#define FEN_HWPDN BIT(14)773#define FEN_MREGEN BIT(15)774 775#define PFM_LDALL BIT(0)776#define PFM_ALDN BIT(1)777#define PFM_LDKP BIT(2)778#define PFM_WOWL BIT(3)779#define ENPDN BIT(4)780#define PDN_PL BIT(5)781#define APFM_ONMAC BIT(8)782#define APFM_OFF BIT(9)783#define APFM_RSM BIT(10)784#define AFSM_HSUS BIT(11)785#define AFSM_PCIE BIT(12)786#define APDM_MAC BIT(13)787#define APDM_HOST BIT(14)788#define APDM_HPDN BIT(15)789#define RDY_MACON BIT(16)790#define SUS_HOST BIT(17)791#define ROP_ALD BIT(20)792#define ROP_PWR BIT(21)793#define ROP_SPS BIT(22)794#define SOP_MRST BIT(25)795#define SOP_FUSE BIT(26)796#define SOP_ABG BIT(27)797#define SOP_AMB BIT(28)798#define SOP_RCK BIT(29)799#define SOP_A8M BIT(30)800#define XOP_BTCK BIT(31)801 802#define ANAD16V_EN BIT(0)803#define ANA8M BIT(1)804#define MACSLP BIT(4)805#define LOADER_CLK_EN BIT(5)806#define _80M_SSC_DIS BIT(7)807#define _80M_SSC_EN_HO BIT(8)808#define PHY_SSC_RSTB BIT(9)809#define SEC_CLK_EN BIT(10)810#define MAC_CLK_EN BIT(11)811#define SYS_CLK_EN BIT(12)812#define RING_CLK_EN BIT(13)813 814#define BOOT_FROM_EEPROM BIT(4)815#define EEPROM_EN BIT(5)816 817#define AFE_BGEN BIT(0)818#define AFE_MBEN BIT(1)819#define MAC_ID_EN BIT(7)820 821#define WLOCK_ALL BIT(0)822#define WLOCK_00 BIT(1)823#define WLOCK_04 BIT(2)824#define WLOCK_08 BIT(3)825#define WLOCK_40 BIT(4)826#define R_DIS_PRST_0 BIT(5)827#define R_DIS_PRST_1 BIT(6)828#define LOCK_ALL_EN BIT(7)829 830#define RF_EN BIT(0)831#define RF_RSTB BIT(1)832#define RF_SDMRSTB BIT(2)833 834#define LDA15_EN BIT(0)835#define LDA15_STBY BIT(1)836#define LDA15_OBUF BIT(2)837#define LDA15_REG_VOS BIT(3)838#define _LDA15_VOADJ(x) (((x) & 0x7) << 4)839 840#define LDV12_EN BIT(0)841#define LDV12_SDBY BIT(1)842#define LPLDO_HSM BIT(2)843#define LPLDO_LSM_DIS BIT(3)844#define _LDV12_VADJ(x) (((x) & 0xF) << 4)845 846#define XTAL_EN BIT(0)847#define XTAL_BSEL BIT(1)848#define _XTAL_BOSC(x) (((x) & 0x3) << 2)849#define _XTAL_CADJ(x) (((x) & 0xF) << 4)850#define XTAL_GATE_USB BIT(8)851#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9)852#define XTAL_GATE_AFE BIT(11)853#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12)854#define XTAL_RF_GATE BIT(14)855#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15)856#define XTAL_GATE_DIG BIT(17)857#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18)858#define XTAL_BT_GATE BIT(20)859#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21)860#define _XTAL_GPIO(x) (((x) & 0x7) << 23)861 862#define CKDLY_AFE BIT(26)863#define CKDLY_USB BIT(27)864#define CKDLY_DIG BIT(28)865#define CKDLY_BT BIT(29)866 867#define APLL_EN BIT(0)868#define APLL_320_EN BIT(1)869#define APLL_FREF_SEL BIT(2)870#define APLL_EDGE_SEL BIT(3)871#define APLL_WDOGB BIT(4)872#define APLL_LPFEN BIT(5)873 874#define APLL_REF_CLK_13MHZ 0x1875#define APLL_REF_CLK_19_2MHZ 0x2876#define APLL_REF_CLK_20MHZ 0x3877#define APLL_REF_CLK_25MHZ 0x4878#define APLL_REF_CLK_26MHZ 0x5879#define APLL_REF_CLK_38_4MHZ 0x6880#define APLL_REF_CLK_40MHZ 0x7881 882#define APLL_320EN BIT(14)883#define APLL_80EN BIT(15)884#define APLL_1MEN BIT(24)885 886#define ALD_EN BIT(18)887#define EF_PD BIT(19)888#define EF_FLAG BIT(31)889 890#define EF_TRPT BIT(7)891#define LDOE25_EN BIT(31)892 893#define RSM_EN BIT(0)894#define TIMER_EN BIT(4)895 896#define TRSW0EN BIT(2)897#define TRSW1EN BIT(3)898#define EROM_EN BIT(4)899#define ENBT BIT(5)900#define ENUART BIT(8)901#define UART_910 BIT(9)902#define ENPMAC BIT(10)903#define SIC_SWRST BIT(11)904#define ENSIC BIT(12)905#define SIC_23 BIT(13)906#define ENHDP BIT(14)907#define SIC_LBK BIT(15)908 909#define LED0PL BIT(4)910#define LED1PL BIT(12)911#define LED0DIS BIT(7)912 913#define MCUFWDL_EN BIT(0)914#define MCUFWDL_RDY BIT(1)915#define FWDL_CHKSUM_RPT BIT(2)916#define MACINI_RDY BIT(3)917#define BBINI_RDY BIT(4)918#define RFINI_RDY BIT(5)919#define WINTINI_RDY BIT(6)920#define CPRST BIT(23)921 922#define XCLK_VLD BIT(0)923#define ACLK_VLD BIT(1)924#define UCLK_VLD BIT(2)925#define PCLK_VLD BIT(3)926#define PCIRSTB BIT(4)927#define V15_VLD BIT(5)928#define TRP_B15V_EN BIT(7)929#define SIC_IDLE BIT(8)930#define BD_MAC2 BIT(9)931#define BD_MAC1 BIT(10)932#define IC_MACPHY_MODE BIT(11)933#define VENDOR_ID BIT(19)934#define PAD_HWPD_IDN BIT(22)935#define TRP_VAUX_EN BIT(23)936#define TRP_BT_EN BIT(24)937#define BD_PKG_SEL BIT(25)938#define BD_HCI_SEL BIT(26)939#define TYPE_ID BIT(27)940 941#define CHIP_VER_RTL_MASK 0xF000942#define CHIP_VER_RTL_SHIFT 12943 944#define REG_LBMODE (REG_CR + 3)945 946#define HCI_TXDMA_EN BIT(0)947#define HCI_RXDMA_EN BIT(1)948#define TXDMA_EN BIT(2)949#define RXDMA_EN BIT(3)950#define PROTOCOL_EN BIT(4)951#define SCHEDULE_EN BIT(5)952#define MACTXEN BIT(6)953#define MACRXEN BIT(7)954#define ENSWBCN BIT(8)955#define ENSEC BIT(9)956 957#define _NETTYPE(x) (((x) & 0x3) << 16)958#define MASK_NETTYPE 0x30000959#define NT_NO_LINK 0x0960#define NT_LINK_AD_HOC 0x1961#define NT_LINK_AP 0x2962#define NT_AS_AP 0x3963 964#define _LBMODE(x) (((x) & 0xF) << 24)965#define MASK_LBMODE 0xF000000966#define LOOPBACK_NORMAL 0x0967#define LOOPBACK_IMMEDIATELY 0xB968#define LOOPBACK_MAC_DELAY 0x3969#define LOOPBACK_PHY 0x1970#define LOOPBACK_DMA 0x7971 972#define GET_RX_PAGE_SIZE(value) ((value) & 0xF)973#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)974#define _PSRX_MASK 0xF975#define _PSTX_MASK 0xF0976#define _PSRX(x) (x)977#define _PSTX(x) ((x) << 4)978 979#define PBP_64 0x0980#define PBP_128 0x1981#define PBP_256 0x2982#define PBP_512 0x3983#define PBP_1024 0x4984 985#define RXDMA_ARBBW_EN BIT(0)986#define RXSHFT_EN BIT(1)987#define RXDMA_AGG_EN BIT(2)988#define QS_VO_QUEUE BIT(8)989#define QS_VI_QUEUE BIT(9)990#define QS_BE_QUEUE BIT(10)991#define QS_BK_QUEUE BIT(11)992#define QS_MANAGER_QUEUE BIT(12)993#define QS_HIGH_QUEUE BIT(13)994 995#define HQSEL_VOQ BIT(0)996#define HQSEL_VIQ BIT(1)997#define HQSEL_BEQ BIT(2)998#define HQSEL_BKQ BIT(3)999#define HQSEL_MGTQ BIT(4)1000#define HQSEL_HIQ BIT(5)1001 1002#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)1003#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)1004#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)1005#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8)1006#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6)1007#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4)1008 1009#define QUEUE_LOW 11010#define QUEUE_NORMAL 21011#define QUEUE_HIGH 31012 1013#define _LLT_NO_ACTIVE 0x01014#define _LLT_WRITE_ACCESS 0x11015#define _LLT_READ_ACCESS 0x21016 1017#define _LLT_INIT_DATA(x) ((x) & 0xFF)1018#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)1019#define _LLT_OP(x) (((x) & 0x3) << 30)1020#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)1021 1022#define BB_WRITE_READ_MASK (BIT(31) | BIT(30))1023#define BB_WRITE_EN BIT(30)1024#define BB_READ_EN BIT(31)1025 1026#define _HPQ(x) ((x) & 0xFF)1027#define _LPQ(x) (((x) & 0xFF) << 8)1028#define _PUBQ(x) (((x) & 0xFF) << 16)1029#define _NPQ(x) ((x) & 0xFF)1030 1031#define HPQ_PUBLIC_DIS BIT(24)1032#define LPQ_PUBLIC_DIS BIT(25)1033#define LD_RQPN BIT(31)1034 1035#define BCN_VALID BIT(16)1036#define BCN_HEAD(x) (((x) & 0xFF) << 8)1037#define BCN_HEAD_MASK 0xFF001038 1039#define BLK_DESC_NUM_SHIFT 41040#define BLK_DESC_NUM_MASK 0xF1041 1042#define DROP_DATA_EN BIT(9)1043 1044#define EN_AMPDU_RTY_NEW BIT(7)1045 1046#define _INIRTSMCS_SEL(x) ((x) & 0x3F)1047 1048#define _SPEC_SIFS_CCK(x) ((x) & 0xFF)1049#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)1050 1051#define RATE_REG_BITMAP_ALL 0xFFFFF1052 1053#define _RRSC_BITMAP(x) ((x) & 0xFFFFF)1054 1055#define _RRSR_RSC(x) (((x) & 0x3) << 21)1056#define RRSR_RSC_RESERVED 0x01057#define RRSR_RSC_UPPER_SUBCHANNEL 0x11058#define RRSR_RSC_LOWER_SUBCHANNEL 0x21059#define RRSR_RSC_DUPLICATE_MODE 0x31060 1061#define USE_SHORT_G1 BIT(20)1062 1063#define _AGGLMT_MCS0(x) ((x) & 0xF)1064#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4)1065#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8)1066#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12)1067#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16)1068#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20)1069#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24)1070#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28)1071 1072#define RETRY_LIMIT_SHORT_SHIFT 81073#define RETRY_LIMIT_LONG_SHIFT 01074 1075#define _DARF_RC1(x) ((x) & 0x1F)1076#define _DARF_RC2(x) (((x) & 0x1F) << 8)1077#define _DARF_RC3(x) (((x) & 0x1F) << 16)1078#define _DARF_RC4(x) (((x) & 0x1F) << 24)1079#define _DARF_RC5(x) ((x) & 0x1F)1080#define _DARF_RC6(x) (((x) & 0x1F) << 8)1081#define _DARF_RC7(x) (((x) & 0x1F) << 16)1082#define _DARF_RC8(x) (((x) & 0x1F) << 24)1083 1084#define _RARF_RC1(x) ((x) & 0x1F)1085#define _RARF_RC2(x) (((x) & 0x1F) << 8)1086#define _RARF_RC3(x) (((x) & 0x1F) << 16)1087#define _RARF_RC4(x) (((x) & 0x1F) << 24)1088#define _RARF_RC5(x) ((x) & 0x1F)1089#define _RARF_RC6(x) (((x) & 0x1F) << 8)1090#define _RARF_RC7(x) (((x) & 0x1F) << 16)1091#define _RARF_RC8(x) (((x) & 0x1F) << 24)1092 1093#define AC_PARAM_TXOP_LIMIT_OFFSET 161094#define AC_PARAM_ECW_MAX_OFFSET 121095#define AC_PARAM_ECW_MIN_OFFSET 81096#define AC_PARAM_AIFS_OFFSET 01097 1098#define _AIFS(x) (x)1099#define _ECW_MAX_MIN(x) ((x) << 8)1100#define _TXOP_LIMIT(x) ((x) << 16)1101 1102#define _BCNIFS(x) ((x) & 0xFF)1103#define _BCNECW(x) ((((x) & 0xF)) << 8)1104 1105#define _LRL(x) ((x) & 0x3F)1106#define _SRL(x) (((x) & 0x3F) << 8)1107 1108#define _SIFS_CCK_CTX(x) ((x) & 0xFF)1109#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8)1110 1111#define _SIFS_OFDM_CTX(x) ((x) & 0xFF)1112#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8)1113 1114#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8)1115 1116#define DIS_EDCA_CNT_DWN BIT(11)1117 1118#define EN_MBSSID BIT(1)1119#define EN_TXBCN_RPT BIT(2)1120#define EN_BCN_FUNCTION BIT(3)1121 1122#define TSFTR_RST BIT(0)1123#define TSFTR1_RST BIT(1)1124 1125#define STOP_BCNQ BIT(6)1126 1127#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4)1128#define DIS_TSF_UDT0_TEST_CHIP BIT(5)1129 1130#define ACMHW_HWEN BIT(0)1131#define ACMHW_BEQEN BIT(1)1132#define ACMHW_VIQEN BIT(2)1133#define ACMHW_VOQEN BIT(3)1134#define ACMHW_BEQSTATUS BIT(4)1135#define ACMHW_VIQSTATUS BIT(5)1136#define ACMHW_VOQSTATUS BIT(6)1137 1138#define APSDOFF BIT(6)1139#define APSDOFF_STATUS BIT(7)1140 1141#define BW_20MHZ BIT(2)1142 1143#define RATE_BITMAP_ALL 0xFFFFF1144 1145#define RATE_RRSR_CCK_ONLY_1M 0xFFFF11146 1147#define TSFRST BIT(0)1148#define DIS_GCLK BIT(1)1149#define PAD_SEL BIT(2)1150#define PWR_ST BIT(6)1151#define PWRBIT_OW_EN BIT(7)1152#define ACRC BIT(8)1153#define CFENDFORM BIT(9)1154#define ICV BIT(10)1155 1156#define AAP BIT(0)1157#define APM BIT(1)1158#define AM BIT(2)1159#define AB BIT(3)1160#define ADD3 BIT(4)1161#define APWRMGT BIT(5)1162#define CBSSID BIT(6)1163#define CBSSID_DATA BIT(6)1164#define CBSSID_BCN BIT(7)1165#define ACRC32 BIT(8)1166#define AICV BIT(9)1167#define ADF BIT(11)1168#define ACF BIT(12)1169#define AMF BIT(13)1170#define HTC_LOC_CTRL BIT(14)1171#define UC_DATA_EN BIT(16)1172#define BM_DATA_EN BIT(17)1173#define MFBEN BIT(22)1174#define LSIGEN BIT(23)1175#define ENMBID BIT(24)1176#define APP_BASSN BIT(27)1177#define APP_PHYSTS BIT(28)1178#define APP_ICV BIT(29)1179#define APP_MIC BIT(30)1180#define APP_FCS BIT(31)1181 1182#define _MIN_SPACE(x) ((x) & 0x7)1183#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3)1184 1185#define RXERR_TYPE_OFDM_PPDU 01186#define RXERR_TYPE_OFDM_FALSE_ALARM 11187#define RXERR_TYPE_OFDM_MPDU_OK 21188#define RXERR_TYPE_OFDM_MPDU_FAIL 31189#define RXERR_TYPE_CCK_PPDU 41190#define RXERR_TYPE_CCK_FALSE_ALARM 51191#define RXERR_TYPE_CCK_MPDU_OK 61192#define RXERR_TYPE_CCK_MPDU_FAIL 71193#define RXERR_TYPE_HT_PPDU 81194#define RXERR_TYPE_HT_FALSE_ALARM 91195#define RXERR_TYPE_HT_MPDU_TOTAL 101196#define RXERR_TYPE_HT_MPDU_OK 111197#define RXERR_TYPE_HT_MPDU_FAIL 121198#define RXERR_TYPE_RX_FULL_DROP 151199 1200#define RXERR_COUNTER_MASK 0xFFFFF1201#define RXERR_RPT_RST BIT(27)1202#define _RXERR_RPT_SEL(type) ((type) << 28)1203 1204#define SCR_TXUSEDK BIT(0)1205#define SCR_RXUSEDK BIT(1)1206#define SCR_TXENCENABLE BIT(2)1207#define SCR_RXDECENABLE BIT(3)1208#define SCR_SKBYA2 BIT(4)1209#define SCR_NOSKMC BIT(5)1210#define SCR_TXBCUSEDK BIT(6)1211#define SCR_RXBCUSEDK BIT(7)1212 1213#define XCLK_VLD BIT(0)1214#define ACLK_VLD BIT(1)1215#define UCLK_VLD BIT(2)1216#define PCLK_VLD BIT(3)1217#define PCIRSTB BIT(4)1218#define V15_VLD BIT(5)1219#define TRP_B15V_EN BIT(7)1220#define SIC_IDLE BIT(8)1221#define BD_MAC2 BIT(9)1222#define BD_MAC1 BIT(10)1223#define IC_MACPHY_MODE BIT(11)1224#define BT_FUNC BIT(16)1225#define VENDOR_ID BIT(19)1226#define PAD_HWPD_IDN BIT(22)1227#define TRP_VAUX_EN BIT(23)1228#define TRP_BT_EN BIT(24)1229#define BD_PKG_SEL BIT(25)1230#define BD_HCI_SEL BIT(26)1231#define TYPE_ID BIT(27)1232 1233#define USB_IS_HIGH_SPEED 01234#define USB_IS_FULL_SPEED 11235#define USB_SPEED_MASK BIT(5)1236 1237#define USB_NORMAL_SIE_EP_MASK 0xF1238#define USB_NORMAL_SIE_EP_SHIFT 41239 1240#define USB_TEST_EP_MASK 0x301241#define USB_TEST_EP_SHIFT 41242 1243#define USB_AGG_EN BIT(3)1244 1245#define MAC_ADDR_LEN 61246#define LAST_ENTRY_OF_TX_PKT_BUFFER 175/*255 88e*/1247 1248#define POLLING_LLT_THRESHOLD 201249#define POLLING_READY_TIMEOUT_COUNT 30001250 1251#define MAX_MSS_DENSITY_2T 0x131252#define MAX_MSS_DENSITY_1T 0x0A1253 1254#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))1255#define EPROM_CMD_CONFIG 0x31256#define EPROM_CMD_LOAD 11257 1258#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE1259 1260#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2)1261 1262#define RPMAC_RESET 0x1001263#define RPMAC_TXSTART 0x1041264#define RPMAC_TXLEGACYSIG 0x1081265#define RPMAC_TXHTSIG1 0x10c1266#define RPMAC_TXHTSIG2 0x1101267#define RPMAC_PHYDEBUG 0x1141268#define RPMAC_TXPACKETNUM 0x1181269#define RPMAC_TXIDLE 0x11c1270#define RPMAC_TXMACHEADER0 0x1201271#define RPMAC_TXMACHEADER1 0x1241272#define RPMAC_TXMACHEADER2 0x1281273#define RPMAC_TXMACHEADER3 0x12c1274#define RPMAC_TXMACHEADER4 0x1301275#define RPMAC_TXMACHEADER5 0x1341276#define RPMAC_TXDADATYPE 0x1381277#define RPMAC_TXRANDOMSEED 0x13c1278#define RPMAC_CCKPLCPPREAMBLE 0x1401279#define RPMAC_CCKPLCPHEADER 0x1441280#define RPMAC_CCKCRC16 0x1481281#define RPMAC_OFDMRXCRC32OK 0x1701282#define RPMAC_OFDMRXCRC32ER 0x1741283#define RPMAC_OFDMRXPARITYER 0x1781284#define RPMAC_OFDMRXCRC8ER 0x17c1285#define RPMAC_CCKCRXRC16ER 0x1801286#define RPMAC_CCKCRXRC32ER 0x1841287#define RPMAC_CCKCRXRC32OK 0x1881288#define RPMAC_TXSTATUS 0x18c1289 1290#define RFPGA0_RFMOD 0x8001291 1292#define RFPGA0_TXINFO 0x8041293#define RFPGA0_PSDFUNCTION 0x8081294 1295#define RFPGA0_TXGAINSTAGE 0x80c1296 1297#define RFPGA0_RFTIMING1 0x8101298#define RFPGA0_RFTIMING2 0x8141299 1300#define RFPGA0_XA_HSSIPARAMETER1 0x8201301#define RFPGA0_XA_HSSIPARAMETER2 0x8241302#define RFPGA0_XB_HSSIPARAMETER1 0x8281303#define RFPGA0_XB_HSSIPARAMETER2 0x82c1304 1305#define RFPGA0_XA_LSSIPARAMETER 0x8401306#define RFPGA0_XB_LSSIPARAMETER 0x8441307 1308#define RFPGA0_RFWAKEUPPARAMETER 0x8501309#define RFPGA0_RFSLEEPUPPARAMETER 0x8541310 1311#define RFPGA0_XAB_SWITCHCONTROL 0x8581312#define RFPGA0_XCD_SWITCHCONTROL 0x85c1313 1314#define RFPGA0_XA_RFINTERFACEOE 0x8601315#define RFPGA0_XB_RFINTERFACEOE 0x8641316 1317#define RFPGA0_XAB_RFINTERFACESW 0x8701318#define RFPGA0_XCD_RFINTERFACESW 0x8741319 1320#define RFPGA0_XAB_RFPARAMETER 0x8781321#define RFPGA0_XCD_RFPARAMETER 0x87c1322 1323#define RFPGA0_ANALOGPARAMETER1 0x8801324#define RFPGA0_ANALOGPARAMETER2 0x8841325#define RFPGA0_ANALOGPARAMETER3 0x8881326#define RFPGA0_ANALOGPARAMETER4 0x88c1327 1328#define RFPGA0_XA_LSSIREADBACK 0x8a01329#define RFPGA0_XB_LSSIREADBACK 0x8a41330#define RFPGA0_XC_LSSIREADBACK 0x8a81331#define RFPGA0_XD_LSSIREADBACK 0x8ac1332 1333#define RFPGA0_PSDREPORT 0x8b41334#define TRANSCEIVEA_HSPI_READBACK 0x8b81335#define TRANSCEIVEB_HSPI_READBACK 0x8bc1336#define REG_SC_CNT 0x8c41337#define RFPGA0_XAB_RFINTERFACERB 0x8e01338#define RFPGA0_XCD_RFINTERFACERB 0x8e41339 1340#define RFPGA1_RFMOD 0x9001341 1342#define RFPGA1_TXBLOCK 0x9041343#define RFPGA1_DEBUGSELECT 0x9081344#define RFPGA1_TXINFO 0x90c1345 1346#define RCCK0_SYSTEM 0xa001347 1348#define RCCK0_AFESETTING 0xa041349#define RCCK0_CCA 0xa081350 1351#define RCCK0_RXAGC1 0xa0c1352#define RCCK0_RXAGC2 0xa101353 1354#define RCCK0_RXHP 0xa141355 1356#define RCCK0_DSPPARAMETER1 0xa181357#define RCCK0_DSPPARAMETER2 0xa1c1358 1359#define RCCK0_TXFILTER1 0xa201360#define RCCK0_TXFILTER2 0xa241361#define RCCK0_DEBUGPORT 0xa281362#define RCCK0_FALSEALARMREPORT 0xa2c1363#define RCCK0_TRSSIREPORT 0xa501364#define RCCK0_RXREPORT 0xa541365#define RCCK0_FACOUNTERLOWER 0xa5c1366#define RCCK0_FACOUNTERUPPER 0xa581367#define RCCK0_CCA_CNT 0xa601368 1369/* PageB(0xB00) */1370#define RPDP_ANTA 0xb001371#define RPDP_ANTA_4 0xb041372#define RPDP_ANTA_8 0xb081373#define RPDP_ANTA_C 0xb0c1374#define RPDP_ANTA_10 0xb101375#define RPDP_ANTA_14 0xb141376#define RPDP_ANTA_18 0xb181377#define RPDP_ANTA_1C 0xb1c1378#define RPDP_ANTA_20 0xb201379#define RPDP_ANTA_24 0xb241380 1381#define RCONFIG_PMPD_ANTA 0xb281382#define RCONFIG_ram64x16 0xb2c1383 1384#define RBNDA 0xb301385#define RHSSIPAR 0xb341386 1387#define RCONFIG_ANTA 0xb681388#define RCONFIG_ANTB 0xb6c1389 1390#define RPDP_ANTB 0xb701391#define RPDP_ANTB_4 0xb741392#define RPDP_ANTB_8 0xb781393#define RPDP_ANTB_C 0xb7c1394#define RPDP_ANTB_10 0xb801395#define RPDP_ANTB_14 0xb841396#define RPDP_ANTB_18 0xb881397#define RPDP_ANTB_1C 0xb8c1398#define RPDP_ANTB_20 0xb901399#define RPDP_ANTB_24 0xb941400 1401#define RCONFIG_PMPD_ANTB 0xb981402 1403#define RBNDB 0xba01404 1405#define RAPK 0xbd81406#define RPM_RX0_ANTA 0xbdc1407#define RPM_RX1_ANTA 0xbe01408#define RPM_RX2_ANTA 0xbe41409#define RPM_RX3_ANTA 0xbe81410#define RPM_RX0_ANTB 0xbec1411#define RPM_RX1_ANTB 0xbf01412#define RPM_RX2_ANTB 0xbf41413#define RPM_RX3_ANTB 0xbf81414 1415/*Page C*/1416#define ROFDM0_LSTF 0xc001417 1418#define ROFDM0_TRXPATHENABLE 0xc041419#define ROFDM0_TRMUXPAR 0xc081420#define ROFDM0_TRSWISOLATION 0xc0c1421 1422#define ROFDM0_XARXAFE 0xc101423#define ROFDM0_XARXIQIMBALANCE 0xc141424#define ROFDM0_XBRXAFE 0xc181425#define ROFDM0_XBRXIQIMBALANCE 0xc1c1426#define ROFDM0_XCRXAFE 0xc201427#define ROFDM0_XCRXIQIMBANLANCE 0xc241428#define ROFDM0_XDRXAFE 0xc281429#define ROFDM0_XDRXIQIMBALANCE 0xc2c1430 1431#define ROFDM0_RXDETECTOR1 0xc301432#define ROFDM0_RXDETECTOR2 0xc341433#define ROFDM0_RXDETECTOR3 0xc381434#define ROFDM0_RXDETECTOR4 0xc3c1435 1436#define ROFDM0_RXDSP 0xc401437#define ROFDM0_CFOANDDAGC 0xc441438#define ROFDM0_CCADROPTHRESHOLD 0xc481439#define ROFDM0_ECCATHRESHOLD 0xc4c1440 1441#define ROFDM0_XAAGCCORE1 0xc501442#define ROFDM0_XAAGCCORE2 0xc541443#define ROFDM0_XBAGCCORE1 0xc581444#define ROFDM0_XBAGCCORE2 0xc5c1445#define ROFDM0_XCAGCCORE1 0xc601446#define ROFDM0_XCAGCCORE2 0xc641447#define ROFDM0_XDAGCCORE1 0xc681448#define ROFDM0_XDAGCCORE2 0xc6c1449 1450#define ROFDM0_AGCPARAMETER1 0xc701451#define ROFDM0_AGCPARAMETER2 0xc741452#define ROFDM0_AGCRSSITABLE 0xc781453#define ROFDM0_HTSTFAGC 0xc7c1454 1455#define ROFDM0_XATXIQIMBALANCE 0xc801456#define ROFDM0_XATXAFE 0xc841457#define ROFDM0_XBTXIQIMBALANCE 0xc881458#define ROFDM0_XBTXAFE 0xc8c1459#define ROFDM0_XCTXIQIMBALANCE 0xc901460#define ROFDM0_XCTXAFE 0xc941461#define ROFDM0_XDTXIQIMBALANCE 0xc981462#define ROFDM0_XDTXAFE 0xc9c1463 1464#define ROFDM0_RXIQEXTANTA 0xca01465#define ROFDM0_TXCOEFF1 0xca41466#define ROFDM0_TXCOEFF2 0xca81467#define ROFDM0_TXCOEFF3 0xcac1468#define ROFDM0_TXCOEFF4 0xcb01469#define ROFDM0_TXCOEFF5 0xcb41470#define ROFDM0_TXCOEFF6 0xcb81471 1472#define ROFDM0_RXHPPARAMETER 0xce01473#define ROFDM0_TXPSEUDONOISEWGT 0xce41474#define ROFDM0_FRAMESYNC 0xcf01475#define ROFDM0_DFSREPORT 0xcf41476 1477#define ROFDM1_LSTF 0xd001478#define ROFDM1_TRXPATHENABLE 0xd041479 1480#define ROFDM1_CF0 0xd081481#define ROFDM1_CSI1 0xd101482#define ROFDM1_SBD 0xd141483#define ROFDM1_CSI2 0xd181484#define ROFDM1_CFOTRACKING 0xd2c1485#define ROFDM1_TRXMESAURE1 0xd341486#define ROFDM1_INTFDET 0xd3c1487#define ROFDM1_PSEUDONOISESTATEAB 0xd501488#define ROFDM1_PSEUDONOISESTATECD 0xd541489#define ROFDM1_RXPSEUDONOISEWGT 0xd581490 1491#define ROFDM_PHYCOUNTER1 0xda01492#define ROFDM_PHYCOUNTER2 0xda41493#define ROFDM_PHYCOUNTER3 0xda81494 1495#define ROFDM_SHORTCFOAB 0xdac1496#define ROFDM_SHORTCFOCD 0xdb01497#define ROFDM_LONGCFOAB 0xdb41498#define ROFDM_LONGCFOCD 0xdb81499#define ROFDM_TAILCF0AB 0xdbc1500#define ROFDM_TAILCF0CD 0xdc01501#define ROFDM_PWMEASURE1 0xdc41502#define ROFDM_PWMEASURE2 0xdc81503#define ROFDM_BWREPORT 0xdcc1504#define ROFDM_AGCREPORT 0xdd01505#define ROFDM_RXSNR 0xdd41506#define ROFDM_RXEVMCSI 0xdd81507#define ROFDM_SIGREPORT 0xddc1508 1509#define RTXAGC_A_RATE18_06 0xe001510#define RTXAGC_A_RATE54_24 0xe041511#define RTXAGC_A_CCK1_MCS32 0xe081512#define RTXAGC_A_MCS03_MCS00 0xe101513#define RTXAGC_A_MCS07_MCS04 0xe141514#define RTXAGC_A_MCS11_MCS08 0xe181515#define RTXAGC_A_MCS15_MCS12 0xe1c1516 1517#define RTXAGC_B_RATE18_06 0x8301518#define RTXAGC_B_RATE54_24 0x8341519#define RTXAGC_B_CCK1_55_MCS32 0x8381520#define RTXAGC_B_MCS03_MCS00 0x83c1521#define RTXAGC_B_MCS07_MCS04 0x8481522#define RTXAGC_B_MCS11_MCS08 0x84c1523#define RTXAGC_B_MCS15_MCS12 0x8681524#define RTXAGC_B_CCK11_A_CCK2_11 0x86c1525 1526#define RFPGA0_IQK 0xe281527#define RTX_IQK_TONE_A 0xe301528#define RRX_IQK_TONE_A 0xe341529#define RTX_IQK_PI_A 0xe381530#define RRX_IQK_PI_A 0xe3c1531 1532#define RTX_IQK 0xe401533#define RRX_IQK 0xe441534#define RIQK_AGC_PTS 0xe481535#define RIQK_AGC_RSP 0xe4c1536#define RTX_IQK_TONE_B 0xe501537#define RRX_IQK_TONE_B 0xe541538#define RTX_IQK_PI_B 0xe581539#define RRX_IQK_PI_B 0xe5c1540#define RIQK_AGC_CONT 0xe601541 1542#define RBLUE_TOOTH 0xe6c1543#define RRX_WAIT_CCA 0xe701544#define RTX_CCK_RFON 0xe741545#define RTX_CCK_BBON 0xe781546#define RTX_OFDM_RFON 0xe7c1547#define RTX_OFDM_BBON 0xe801548#define RTX_TO_RX 0xe841549#define RTX_TO_TX 0xe881550#define RRX_CCK 0xe8c1551 1552#define RTX_POWER_BEFORE_IQK_A 0xe941553#define RTX_POWER_AFTER_IQK_A 0xe9c1554 1555#define RRX_POWER_BEFORE_IQK_A 0xea01556#define RRX_POWER_BEFORE_IQK_A_2 0xea41557#define RRX_POWER_AFTER_IQK_A 0xea81558#define RRX_POWER_AFTER_IQK_A_2 0xeac1559 1560#define RTX_POWER_BEFORE_IQK_B 0xeb41561#define RTX_POWER_AFTER_IQK_B 0xebc1562 1563#define RRX_POWER_BEFORE_IQK_B 0xec01564#define RRX_POWER_BEFORE_IQK_B_2 0xec41565#define RRX_POWER_AFTER_IQK_B 0xec81566#define RRX_POWER_AFTER_IQK_B_2 0xecc1567 1568#define RRX_OFDM 0xed01569#define RRX_WAIT_RIFS 0xed41570#define RRX_TO_RX 0xed81571#define RSTANDBY 0xedc1572#define RSLEEP 0xee01573#define RPMPD_ANAEN 0xeec1574 1575#define RZEBRA1_HSSIENABLE 0x01576#define RZEBRA1_TRXENABLE1 0x11577#define RZEBRA1_TRXENABLE2 0x21578#define RZEBRA1_AGC 0x41579#define RZEBRA1_CHARGEPUMP 0x51580#define RZEBRA1_CHANNEL 0x71581 1582#define RZEBRA1_TXGAIN 0x81583#define RZEBRA1_TXLPF 0x91584#define RZEBRA1_RXLPF 0xb1585#define RZEBRA1_RXHPFCORNER 0xc1586 1587#define RGLOBALCTRL 01588#define RRTL8256_TXLPF 191589#define RRTL8256_RXLPF 111590#define RRTL8258_TXLPF 0x111591#define RRTL8258_RXLPF 0x131592#define RRTL8258_RSSILPF 0xa1593 1594#define RF_AC 0x001595 1596#define RF_IQADJ_G1 0x011597#define RF_IQADJ_G2 0x021598#define RF_POW_TRSW 0x051599 1600#define RF_GAIN_RX 0x061601#define RF_GAIN_TX 0x071602 1603#define RF_TXM_IDAC 0x081604#define RF_BS_IQGEN 0x0F1605 1606#define RF_MODE1 0x101607#define RF_MODE2 0x111608 1609#define RF_RX_AGC_HP 0x121610#define RF_TX_AGC 0x131611#define RF_BIAS 0x141612#define RF_IPA 0x151613#define RF_POW_ABILITY 0x171614#define RF_MODE_AG 0x181615#define RRFCHANNEL 0x181616#define RF_CHNLBW 0x181617#define RF_TOP 0x191618 1619#define RF_RX_G1 0x1A1620#define RF_RX_G2 0x1B1621 1622#define RF_RX_BB2 0x1C1623#define RF_RX_BB1 0x1D1624 1625#define RF_RCK1 0x1E1626#define RF_RCK2 0x1F1627 1628#define RF_TX_G1 0x201629#define RF_TX_G2 0x211630#define RF_TX_G3 0x221631 1632#define RF_TX_BB1 0x231633#define RF_T_METER 0x421634 1635#define RF_SYN_G1 0x251636#define RF_SYN_G2 0x261637#define RF_SYN_G3 0x271638#define RF_SYN_G4 0x281639#define RF_SYN_G5 0x291640#define RF_SYN_G6 0x2A1641#define RF_SYN_G7 0x2B1642#define RF_SYN_G8 0x2C1643 1644#define RF_RCK_OS 0x301645#define RF_TXPA_G1 0x311646#define RF_TXPA_G2 0x321647#define RF_TXPA_G3 0x331648 1649#define RF_TX_BIAS_A 0x351650#define RF_TX_BIAS_D 0x361651#define RF_LOBF_9 0x381652#define RF_RXRF_A3 0x3C1653#define RF_TRSW 0x3F1654 1655#define RF_TXRF_A2 0x411656#define RF_TXPA_G4 0x461657#define RF_TXPA_A4 0x4B1658 1659#define RF_WE_LUT 0xEF1660 1661#define BBBRESETB 0x1001662#define BGLOBALRESETB 0x2001663#define BOFDMTXSTART 0x41664#define BCCKTXSTART 0x81665#define BCRC32DEBUG 0x1001666#define BPMACLOOPBACK 0x101667#define BTXLSIG 0xffffff1668#define BOFDMTXRATE 0xf1669#define BOFDMTXRESERVED 0x101670#define BOFDMTXLENGTH 0x1ffe01671#define BOFDMTXPARITY 0x200001672#define BTXHTSIG1 0xffffff1673#define BTXHTMCSRATE 0x7f1674#define BTXHTBW 0x801675#define BTXHTLENGTH 0xffff001676#define BTXHTSIG2 0xffffff1677#define BTXHTSMOOTHING 0x11678#define BTXHTSOUNDING 0x21679#define BTXHTRESERVED 0x41680#define BTXHTAGGREATION 0x81681#define BTXHTSTBC 0x301682#define BTXHTADVANCECODING 0x401683#define BTXHTSHORTGI 0x801684#define BTXHTNUMBERHT_LTF 0x3001685#define BTXHTCRC8 0x3fc001686#define BCOUNTERRESET 0x100001687#define BNUMOFOFDMTX 0xffff1688#define BNUMOFCCKTX 0xffff00001689#define BTXIDLEINTERVAL 0xffff1690#define BOFDMSERVICE 0xffff00001691#define BTXMACHEADER 0xffffffff1692#define BTXDATAINIT 0xff1693#define BTXHTMODE 0x1001694#define BTXDATATYPE 0x300001695#define BTXRANDOMSEED 0xffffffff1696#define BCCKTXPREAMBLE 0x11697#define BCCKTXSFD 0xffff00001698#define BCCKTXSIG 0xff1699#define BCCKTXSERVICE 0xff001700#define BCCKLENGTHEXT 0x80001701#define BCCKTXLENGHT 0xffff00001702#define BCCKTXCRC16 0xffff1703#define BCCKTXSTATUS 0x11704#define BOFDMTXSTATUS 0x21705#define IS_BB_REG_OFFSET_92S(_offset) \1706 ((_offset >= 0x800) && (_offset <= 0xfff))1707 1708#define BRFMOD 0x11709#define BJAPANMODE 0x21710#define BCCKTXSC 0x301711#define BCCKEN 0x10000001712#define BOFDMEN 0x20000001713 1714#define BOFDMRXADCPHASE 0x100001715#define BOFDMTXDACPHASE 0x400001716#define BXATXAGC 0x3f1717 1718#define BXBTXAGC 0xf001719#define BXCTXAGC 0xf0001720#define BXDTXAGC 0xf00001721 1722#define BPASTART 0xf00000001723#define BTRSTART 0x00f000001724#define BRFSTART 0x0000f0001725#define BBBSTART 0x000000f01726#define BBBCCKSTART 0x0000000f1727#define BPAEND 0xf1728#define BTREND 0x0f0000001729#define BRFEND 0x000f00001730#define BCCAMASK 0x000000f01731#define BR2RCCAMASK 0x00000f001732#define BHSSI_R2TDELAY 0xf80000001733#define BHSSI_T2RDELAY 0xf800001734#define BCONTXHSSI 0x4001735#define BIGFROMCCK 0x2001736#define BAGCADDRESS 0x3f1737#define BRXHPTX 0x70001738#define BRXHP2RX 0x380001739#define BRXHPCCKINI 0xc00001740#define BAGCTXCODE 0xc000001741#define BAGCRXCODE 0x3000001742 1743#define B3WIREDATALENGTH 0x8001744#define B3WIREADDREAALENGTH 0x4001745 1746#define B3WIRERFPOWERDOWN 0x11747#define B5GPAPEPOLARITY 0x400000001748#define B2GPAPEPOLARITY 0x800000001749#define BRFSW_TXDEFAULTANT 0x31750#define BRFSW_TXOPTIONANT 0x301751#define BRFSW_RXDEFAULTANT 0x3001752#define BRFSW_RXOPTIONANT 0x30001753#define BRFSI_3WIREDATA 0x11754#define BRFSI_3WIRECLOCK 0x21755#define BRFSI_3WIRELOAD 0x41756#define BRFSI_3WIRERW 0x81757#define BRFSI_3WIRE 0xf1758 1759#define BRFSI_RFENV 0x101760 1761#define BRFSI_TRSW 0x201762#define BRFSI_TRSWB 0x401763#define BRFSI_ANTSW 0x1001764#define BRFSI_ANTSWB 0x2001765#define BRFSI_PAPE 0x4001766#define BRFSI_PAPE5G 0x8001767#define BBANDSELECT 0x11768#define BHTSIG2_GI 0x801769#define BHTSIG2_SMOOTHING 0x011770#define BHTSIG2_SOUNDING 0x021771#define BHTSIG2_AGGREATON 0x081772#define BHTSIG2_STBC 0x301773#define BHTSIG2_ADVCODING 0x401774#define BHTSIG2_NUMOFHTLTF 0x3001775#define BHTSIG2_CRC8 0x3fc1776#define BHTSIG1_MCS 0x7f1777#define BHTSIG1_BANDWIDTH 0x801778#define BHTSIG1_HTLENGTH 0xffff1779#define BLSIG_RATE 0xf1780#define BLSIG_RESERVED 0x101781#define BLSIG_LENGTH 0x1fffe1782#define BLSIG_PARITY 0x201783#define BCCKRXPHASE 0x41784 1785#define BLSSIREADADDRESS 0x7f8000001786#define BLSSIREADEDGE 0x800000001787 1788#define BLSSIREADBACKDATA 0xfffff1789 1790#define BLSSIREADOKFLAG 0x10001791#define BCCKSAMPLERATE 0x81792#define BREGULATOR0STANDBY 0x11793#define BREGULATORPLLSTANDBY 0x21794#define BREGULATOR1STANDBY 0x41795#define BPLLPOWERUP 0x81796#define BDPLLPOWERUP 0x101797#define BDA10POWERUP 0x201798#define BAD7POWERUP 0x2001799#define BDA6POWERUP 0x20001800#define BXTALPOWERUP 0x40001801#define B40MDCLKPOWERUP 0x80001802#define BDA6DEBUGMODE 0x200001803#define BDA6SWING 0x3800001804 1805#define BADCLKPHASE 0x40000001806#define B80MCLKDELAY 0x180000001807#define BAFEWATCHDOGENABLE 0x200000001808 1809#define BXTALCAP01 0xc00000001810#define BXTALCAP23 0x31811#define BXTALCAP92X 0x0f0000001812#define BXTALCAP 0x0f0000001813 1814#define BINTDIFCLKENABLE 0x4001815#define BEXTSIGCLKENABLE 0x8001816#define BBANDGAP_MBIAS_POWERUP 0x100001817#define BAD11SH_GAIN 0xc00001818#define BAD11NPUT_RANGE 0x7000001819#define BAD110P_CURRENT 0x38000001820#define BLPATH_LOOPBACK 0x40000001821#define BQPATH_LOOPBACK 0x80000001822#define BAFE_LOOPBACK 0x100000001823#define BDA10_SWING 0x7e01824#define BDA10_REVERSE 0x8001825#define BDA_CLK_SOURCE 0x10001826#define BDA7INPUT_RANGE 0x60001827#define BDA7_GAIN 0x380001828#define BDA7OUTPUT_CM_MODE 0x400001829#define BDA7INPUT_CM_MODE 0x3800001830#define BDA7CURRENT 0xc000001831#define BREGULATOR_ADJUST 0x70000001832#define BAD11POWERUP_ATTX 0x11833#define BDA10PS_ATTX 0x101834#define BAD11POWERUP_ATRX 0x1001835#define BDA10PS_ATRX 0x10001836#define BCCKRX_AGC_FORMAT 0x2001837#define BPSDFFT_SAMPLE_POINT 0xc0001838#define BPSD_AVERAGE_NUM 0x30001839#define BIQPATH_CONTROL 0xc001840#define BPSD_FREQ 0x3ff1841#define BPSD_ANTENNA_PATH 0x301842#define BPSD_IQ_SWITCH 0x401843#define BPSD_RX_TRIGGER 0x4000001844#define BPSD_TX_TRIGGER 0x800000001845#define BPSD_SINE_TONE_SCALE 0x7f0000001846#define BPSD_REPORT 0xffff1847 1848#define BOFDM_TXSC 0x300000001849#define BCCK_TXON 0x11850#define BOFDM_TXON 0x21851#define BDEBUG_PAGE 0xfff1852#define BDEBUG_ITEM 0xff1853#define BANTL 0x101854#define BANT_NONHT 0x1001855#define BANT_HT1 0x10001856#define BANT_HT2 0x100001857#define BANT_HT1S1 0x1000001858#define BANT_NONHTS1 0x10000001859 1860#define BCCK_BBMODE 0x31861#define BCCK_TXPOWERSAVING 0x801862#define BCCK_RXPOWERSAVING 0x401863 1864#define BCCK_SIDEBAND 0x101865 1866#define BCCK_SCRAMBLE 0x81867#define BCCK_ANTDIVERSITY 0x80001868#define BCCK_CARRIER_RECOVERY 0x40001869#define BCCK_TXRATE 0x30001870#define BCCK_DCCANCEL 0x08001871#define BCCK_ISICANCEL 0x04001872#define BCCK_MATCH_FILTER 0x02001873#define BCCK_EQUALIZER 0x01001874#define BCCK_PREAMBLE_DETECT 0x8000001875#define BCCK_FAST_FALSECCA 0x4000001876#define BCCK_CH_ESTSTART 0x3000001877#define BCCK_CCA_COUNT 0x0800001878#define BCCK_CS_LIM 0x0700001879#define BCCK_BIST_MODE 0x800000001880#define BCCK_CCAMASK 0x400000001881#define BCCK_TX_DAC_PHASE 0x41882#define BCCK_RX_ADC_PHASE 0x200000001883#define BCCKR_CP_MODE 0x01001884#define BCCK_TXDC_OFFSET 0xf01885#define BCCK_RXDC_OFFSET 0xf1886#define BCCK_CCA_MODE 0xc0001887#define BCCK_FALSECS_LIM 0x3f001888#define BCCK_CS_RATIO 0xc000001889#define BCCK_CORGBIT_SEL 0x3000001890#define BCCK_PD_LIM 0x0f00001891#define BCCK_NEWCCA 0x800000001892#define BCCK_RXHP_OF_IG 0x80001893#define BCCK_RXIG 0x7f001894#define BCCK_LNA_POLARITY 0x8000001895#define BCCK_RX1ST_BAIN 0x7f00001896#define BCCK_RF_EXTEND 0x200000001897#define BCCK_RXAGC_SATLEVEL 0x1f0000001898#define BCCK_RXAGC_SATCOUNT 0xe01899#define BCCKRXRFSETTLE 0x1f1900#define BCCK_FIXED_RXAGC 0x80001901#define BCCK_ANTENNA_POLARITY 0x20001902#define BCCK_TXFILTER_TYPE 0x0c001903#define BCCK_RXAGC_REPORTTYPE 0x03001904#define BCCK_RXDAGC_EN 0x800000001905#define BCCK_RXDAGC_PERIOD 0x200000001906#define BCCK_RXDAGC_SATLEVEL 0x1f0000001907#define BCCK_TIMING_RECOVERY 0x8000001908#define BCCK_TXC0 0x3f00001909#define BCCK_TXC1 0x3f0000001910#define BCCK_TXC2 0x3f1911#define BCCK_TXC3 0x3f001912#define BCCK_TXC4 0x3f00001913#define BCCK_TXC5 0x3f0000001914#define BCCK_TXC6 0x3f1915#define BCCK_TXC7 0x3f001916#define BCCK_DEBUGPORT 0xff00001917#define BCCK_DAC_DEBUG 0x0f0000001918#define BCCK_FALSEALARM_ENABLE 0x80001919#define BCCK_FALSEALARM_READ 0x40001920#define BCCK_TRSSI 0x7f1921#define BCCK_RXAGC_REPORT 0xfe1922#define BCCK_RXREPORT_ANTSEL 0x800000001923#define BCCK_RXREPORT_MFOFF 0x400000001924#define BCCK_RXREPORT_SQLOSS 0x200000001925#define BCCK_RXREPORT_PKTLOSS 0x100000001926#define BCCK_RXREPORT_LOCKEDBIT 0x080000001927#define BCCK_RXREPORT_RATEERROR 0x040000001928#define BCCK_RXREPORT_RXRATE 0x030000001929#define BCCK_RXFA_COUNTER_LOWER 0xff1930#define BCCK_RXFA_COUNTER_UPPER 0xff0000001931#define BCCK_RXHPAGC_START 0xe0001932#define BCCK_RXHPAGC_FINAL 0x1c001933#define BCCK_RXFALSEALARM_ENABLE 0x80001934#define BCCK_FACOUNTER_FREEZE 0x40001935#define BCCK_TXPATH_SEL 0x100000001936#define BCCK_DEFAULT_RXPATH 0xc0000001937#define BCCK_OPTION_RXPATH 0x30000001938 1939#define BNUM_OFSTF 0x31940#define BSHIFT_L 0xc01941#define BGI_TH 0xc1942#define BRXPATH_A 0x11943#define BRXPATH_B 0x21944#define BRXPATH_C 0x41945#define BRXPATH_D 0x81946#define BTXPATH_A 0x11947#define BTXPATH_B 0x21948#define BTXPATH_C 0x41949#define BTXPATH_D 0x81950#define BTRSSI_FREQ 0x2001951#define BADC_BACKOFF 0x30001952#define BDFIR_BACKOFF 0xc0001953#define BTRSSI_LATCH_PHASE 0x100001954#define BRX_LDC_OFFSET 0xff1955#define BRX_QDC_OFFSET 0xff001956#define BRX_DFIR_MODE 0x18000001957#define BRX_DCNF_TYPE 0xe0000001958#define BRXIQIMB_A 0x3ff1959#define BRXIQIMB_B 0xfc001960#define BRXIQIMB_C 0x3f00001961#define BRXIQIMB_D 0xffc000001962#define BDC_DC_NOTCH 0x600001963#define BRXNB_NOTCH 0x1f0000001964#define BPD_TH 0xf1965#define BPD_TH_OPT2 0xc0001966#define BPWED_TH 0x7001967#define BIFMF_WIN_L 0x8001968#define BPD_OPTION 0x10001969#define BMF_WIN_L 0xe0001970#define BBW_SEARCH_L 0x300001971#define BWIN_ENH_L 0xc00001972#define BBW_TH 0x7000001973#define BED_TH2 0x38000001974#define BBW_OPTION 0x40000001975#define BRADIO_TH 0x180000001976#define BWINDOW_L 0xe00000001977#define BSBD_OPTION 0x11978#define BFRAME_TH 0x1c1979#define BFS_OPTION 0x601980#define BDC_SLOPE_CHECK 0x801981#define BFGUARD_COUNTER_DC_L 0xe001982#define BFRAME_WEIGHT_SHORT 0x70001983#define BSUB_TUNE 0xe000001984#define BFRAME_DC_LENGTH 0xe0000001985#define BSBD_START_OFFSET 0x300000001986#define BFRAME_TH_2 0x71987#define BFRAME_GI2_TH 0x381988#define BGI2_SYNC_EN 0x401989#define BSARCH_SHORT_EARLY 0x3001990#define BSARCH_SHORT_LATE 0xc001991#define BSARCH_GI2_LATE 0x700001992#define BCFOANTSUM 0x11993#define BCFOACC 0x21994#define BCFOSTARTOFFSET 0xc1995#define BCFOLOOPBACK 0x701996#define BCFOSUMWEIGHT 0x801997#define BDAGCENABLE 0x100001998#define BTXIQIMB_A 0x3ff1999#define BTXIQIMB_b 0xfc002000#define BTXIQIMB_C 0x3f00002001#define BTXIQIMB_D 0xffc000002002#define BTXIDCOFFSET 0xff2003#define BTXIQDCOFFSET 0xff002004#define BTXDFIRMODE 0x100002005#define BTXPESUDO_NOISEON 0x40000002006#define BTXPESUDO_NOISE_A 0xff2007#define BTXPESUDO_NOISE_B 0xff002008#define BTXPESUDO_NOISE_C 0xff00002009#define BTXPESUDO_NOISE_D 0xff0000002010#define BCCA_DROPOPTION 0x200002011#define BCCA_DROPTHRES 0xfff000002012#define BEDCCA_H 0xf2013#define BEDCCA_L 0xf02014#define BLAMBDA_ED 0x3002015#define BRX_INITIALGAIN 0x7f2016#define BRX_ANTDIV_EN 0x802017#define BRX_AGC_ADDRESS_FOR_LNA 0x7f002018#define BRX_HIGHPOWER_FLOW 0x80002019#define BRX_AGC_FREEZE_THRES 0xc00002020#define BRX_FREEZESTEP_AGC1 0x3000002021#define BRX_FREEZESTEP_AGC2 0xc000002022#define BRX_FREEZESTEP_AGC3 0x30000002023#define BRX_FREEZESTEP_AGC0 0xc0000002024#define BRXRSSI_CMP_EN 0x100000002025#define BRXQUICK_AGCEN 0x200000002026#define BRXAGC_FREEZE_THRES_MODE 0x400000002027#define BRX_OVERFLOW_CHECKTYPE 0x800000002028#define BRX_AGCSHIFT 0x7f2029#define BTRSW_TRI_ONLY 0x802030#define BPOWER_THRES 0x3002031#define BRXAGC_EN 0x12032#define BRXAGC_TOGETHER_EN 0x22033#define BRXAGC_MIN 0x42034#define BRXHP_INI 0x72035#define BRXHP_TRLNA 0x702036#define BRXHP_RSSI 0x7002037#define BRXHP_BBP1 0x70002038#define BRXHP_BBP2 0x700002039#define BRXHP_BBP3 0x7000002040#define BRSSI_H 0x7f00002041#define BRSSI_GEN 0x7f0000002042#define BRXSETTLE_TRSW 0x72043#define BRXSETTLE_LNA 0x382044#define BRXSETTLE_RSSI 0x1c02045#define BRXSETTLE_BBP 0xe002046#define BRXSETTLE_RXHP 0x70002047#define BRXSETTLE_ANTSW_RSSI 0x380002048#define BRXSETTLE_ANTSW 0xc00002049#define BRXPROCESS_TIME_DAGC 0x3000002050#define BRXSETTLE_HSSI 0x4000002051#define BRXPROCESS_TIME_BBPPW 0x8000002052#define BRXANTENNA_POWER_SHIFT 0x30000002053#define BRSSI_TABLE_SELECT 0xc0000002054#define BRXHP_FINAL 0x70000002055#define BRXHPSETTLE_BBP 0x72056#define BRXHTSETTLE_HSSI 0x82057#define BRXHTSETTLE_RXHP 0x702058#define BRXHTSETTLE_BBPPW 0x802059#define BRXHTSETTLE_IDLE 0x3002060#define BRXHTSETTLE_RESERVED 0x1c002061#define BRXHT_RXHP_EN 0x80002062#define BRXAGC_FREEZE_THRES 0x300002063#define BRXAGC_TOGETHEREN 0x400002064#define BRXHTAGC_MIN 0x800002065#define BRXHTAGC_EN 0x1000002066#define BRXHTDAGC_EN 0x2000002067#define BRXHT_RXHP_BBP 0x1c000002068#define BRXHT_RXHP_FINAL 0xe00000002069#define BRXPW_RADIO_TH 0x32070#define BRXPW_RADIO_EN 0x42071#define BRXMF_HOLD 0x38002072#define BRXPD_DELAY_TH1 0x382073#define BRXPD_DELAY_TH2 0x1c02074#define BRXPD_DC_COUNT_MAX 0x6002075#define BRXPD_DELAY_TH 0x80002076#define BRXPROCESS_DELAY 0xf00002077#define BRXSEARCHRANGE_GI2_EARLY 0x7000002078#define BRXFRAME_FUARD_COUNTER_L 0x38000002079#define BRXSGI_GUARD_L 0xc0000002080#define BRXSGI_SEARCH_L 0x300000002081#define BRXSGI_TH 0xc00000002082#define BDFSCNT0 0xff2083#define BDFSCNT1 0xff002084#define BDFSFLAG 0xf00002085#define BMF_WEIGHT_SUM 0x3000002086#define BMINIDX_TH 0x7f0000002087#define BDAFORMAT 0x400002088#define BTXCH_EMU_ENABLE 0x010000002089#define BTRSW_ISOLATION_A 0x7f2090#define BTRSW_ISOLATION_B 0x7f002091#define BTRSW_ISOLATION_C 0x7f00002092#define BTRSW_ISOLATION_D 0x7f0000002093#define BEXT_LNA_GAIN 0x7c002094 2095#define BSTBC_EN 0x42096#define BANTENNA_MAPPING 0x102097#define BNSS 0x202098#define BCFO_ANTSUM_ID 0x2002099#define BPHY_COUNTER_RESET 0x80000002100#define BCFO_REPORT_GET 0x40000002101#define BOFDM_CONTINUE_TX 0x100000002102#define BOFDM_SINGLE_CARRIER 0x200000002103#define BOFDM_SINGLE_TONE 0x400000002104#define BHT_DETECT 0x1002105#define BCFOEN 0x100002106#define BCFOVALUE 0xfff000002107#define BSIGTONE_RE 0x3f2108#define BSIGTONE_IM 0x7f002109#define BCOUNTER_CCA 0xffff2110#define BCOUNTER_PARITYFAIL 0xffff00002111#define BCOUNTER_RATEILLEGAL 0xffff2112#define BCOUNTER_CRC8FAIL 0xffff00002113#define BCOUNTER_MCSNOSUPPORT 0xffff2114#define BCOUNTER_FASTSYNC 0xffff2115#define BSHORTCFO 0xfff2116#define BSHORTCFOT_LENGTH 122117#define BSHORTCFOF_LENGTH 112118#define BLONGCFO 0x7ff2119#define BLONGCFOT_LENGTH 112120#define BLONGCFOF_LENGTH 112121#define BTAILCFO 0x1fff2122#define BTAILCFOT_LENGTH 132123#define BTAILCFOF_LENGTH 122124#define BNOISE_EN_PWDB 0xffff2125#define BCC_POWER_DB 0xffff00002126#define BMOISE_PWDB 0xffff2127#define BPOWERMEAST_LENGTH 102128#define BPOWERMEASF_LENGTH 32129#define BRX_HT_BW 0x12130#define BRXSC 0x62131#define BRX_HT 0x82132#define BNB_INTF_DET_ON 0x12133#define BINTF_WIN_LEN_CFG 0x302134#define BNB_INTF_TH_CFG 0x1c02135#define BRFGAIN 0x3f2136#define BTABLESEL 0x402137#define BTRSW 0x802138#define BRXSNR_A 0xff2139#define BRXSNR_B 0xff002140#define BRXSNR_C 0xff00002141#define BRXSNR_D 0xff0000002142#define BSNR_EVMT_LENGTH 82143#define BSNR_EVMF_LENGTH 12144#define BCSI1ST 0xff2145#define BCSI2ND 0xff002146#define BRXEVM1ST 0xff00002147#define BRXEVM2ND 0xff0000002148#define BSIGEVM 0xff2149#define BPWDB 0xff002150#define BSGIEN 0x100002151 2152#define BSFACTOR_QMA1 0xf2153#define BSFACTOR_QMA2 0xf02154#define BSFACTOR_QMA3 0xf002155#define BSFACTOR_QMA4 0xf0002156#define BSFACTOR_QMA5 0xf00002157#define BSFACTOR_QMA6 0xf00002158#define BSFACTOR_QMA7 0xf000002159#define BSFACTOR_QMA8 0xf0000002160#define BSFACTOR_QMA9 0xf00000002161#define BCSI_SCHEME 0x1000002162 2163#define BNOISE_LVL_TOP_SET 0x32164#define BCHSMOOTH 0x42165#define BCHSMOOTH_CFG1 0x382166#define BCHSMOOTH_CFG2 0x1c02167#define BCHSMOOTH_CFG3 0xe002168#define BCHSMOOTH_CFG4 0x70002169#define BMRCMODE 0x8000002170#define BTHEVMCFG 0x70000002171 2172#define BLOOP_FIT_TYPE 0x12173#define BUPD_CFO 0x402174#define BUPD_CFO_OFFDATA 0x802175#define BADV_UPD_CFO 0x1002176#define BADV_TIME_CTRL 0x8002177#define BUPD_CLKO 0x10002178#define BFC 0x60002179#define BTRACKING_MODE 0x80002180#define BPHCMP_ENABLE 0x100002181#define BUPD_CLKO_LTF 0x200002182#define BCOM_CH_CFO 0x400002183#define BCSI_ESTI_MODE 0x800002184#define BADV_UPD_EQZ 0x1000002185#define BUCHCFG 0x70000002186#define BUPDEQZ 0x80000002187 2188#define BRX_PESUDO_NOISE_ON 0x200000002189#define BRX_PESUDO_NOISE_A 0xff2190#define BRX_PESUDO_NOISE_B 0xff002191#define BRX_PESUDO_NOISE_C 0xff00002192#define BRX_PESUDO_NOISE_D 0xff0000002193#define BRX_PESUDO_NOISESTATE_A 0xffff2194#define BRX_PESUDO_NOISESTATE_B 0xffff00002195#define BRX_PESUDO_NOISESTATE_C 0xffff2196#define BRX_PESUDO_NOISESTATE_D 0xffff00002197 2198#define BZEBRA1_HSSIENABLE 0x82199#define BZEBRA1_TRXCONTROL 0xc002200#define BZEBRA1_TRXGAINSETTING 0x07f2201#define BZEBRA1_RXCOUNTER 0xc002202#define BZEBRA1_TXCHANGEPUMP 0x382203#define BZEBRA1_RXCHANGEPUMP 0x72204#define BZEBRA1_CHANNEL_NUM 0xf802205#define BZEBRA1_TXLPFBW 0x4002206#define BZEBRA1_RXLPFBW 0x6002207 2208#define BRTL8256REG_MODE_CTRL1 0x1002209#define BRTL8256REG_MODE_CTRL0 0x402210#define BRTL8256REG_TXLPFBW 0x182211#define BRTL8256REG_RXLPFBW 0x6002212 2213#define BRTL8258_TXLPFBW 0xc2214#define BRTL8258_RXLPFBW 0xc002215#define BRTL8258_RSSILPFBW 0xc02216 2217#define BBYTE0 0x12218#define BBYTE1 0x22219#define BBYTE2 0x42220#define BBYTE3 0x82221#define BWORD0 0x32222#define BWORD1 0xc2223#define BWORD 0xf2224 2225#define MASKBYTE0 0xff2226#define MASKBYTE1 0xff002227#define MASKBYTE2 0xff00002228#define MASKBYTE3 0xff0000002229#define MASKHWORD 0xffff00002230#define MASKLWORD 0x0000ffff2231#define MASKDWORD 0xffffffff2232#define MASK12BITS 0xfff2233#define MASKH4BITS 0xf00000002234#define MASKOFDM_D 0xffc000002235#define MASKCCK 0x3f3f3f3f2236 2237#define MASK4BITS 0x0f2238#define MASK20BITS 0xfffff2239#define RFREG_OFFSET_MASK 0xfffff2240 2241#define BENABLE 0x12242#define BDISABLE 0x02243 2244#define LEFT_ANTENNA 0x02245#define RIGHT_ANTENNA 0x12246 2247#define TCHECK_TXSTATUS 5002248#define TUPDATE_RXCOUNTER 1002249 2250#define REG_UN_used_register 0x01bf2251 2252/* WOL bit information */2253#define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0)2254#define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1)2255#define HAL92C_WOL_DISASSOC_EVENT BIT(2)2256#define HAL92C_WOL_DEAUTH_EVENT BIT(3)2257#define HAL92C_WOL_FW_DISCONNECT_EVENT BIT(4)2258 2259#define WOL_REASON_PTK_UPDATE BIT(0)2260#define WOL_REASON_GTK_UPDATE BIT(1)2261#define WOL_REASON_DISASSOC BIT(2)2262#define WOL_REASON_DEAUTH BIT(3)2263#define WOL_REASON_FW_DISCONNECT BIT(4)2264 2265/* 2 EFUSE_TEST (For RTL8723 partially) */2266#define EFUSE_SEL(x) (((x) & 0x3) << 8)2267#define EFUSE_SEL_MASK 0x3002268#define EFUSE_WIFI_SEL_0 0x02269 2270#define WL_HWPDN_EN BIT(0) /* Enable GPIO[9] as WiFi HW PDn source*/2271#define WL_HWPDN_SL BIT(1) /* WiFi HW PDn polarity control*/2272 2273#endif2274