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1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright(c) 2009-2010 Realtek Corporation.*/3 4#ifndef __RTL8821AE_DM_H__5#define __RTL8821AE_DM_H__6 7#define MAIN_ANT 08#define AUX_ANT 19#define MAIN_ANT_CG_TRX 110#define AUX_ANT_CG_TRX 011#define MAIN_ANT_CGCS_RX 012#define AUX_ANT_CGCS_RX 113 14#define TXSCALE_TABLE_SIZE 3715 16/*RF REG LIST*/17#define DM_REG_RF_MODE_11N 0x0018#define DM_REG_RF_0B_11N 0x0B19#define DM_REG_CHNBW_11N 0x1820#define DM_REG_T_METER_11N 0x2421#define DM_REG_RF_25_11N 0x2522#define DM_REG_RF_26_11N 0x2623#define DM_REG_RF_27_11N 0x2724#define DM_REG_RF_2B_11N 0x2B25#define DM_REG_RF_2C_11N 0x2C26#define DM_REG_RXRF_A3_11N 0x3C27#define DM_REG_T_METER_92D_11N 0x4228#define DM_REG_T_METER_88E_11N 0x4229 30/*BB REG LIST*/31/*PAGE 8 */32#define DM_REG_BB_CTRL_11N 0x80033#define DM_REG_RF_PIN_11N 0x80434#define DM_REG_PSD_CTRL_11N 0x80835#define DM_REG_TX_ANT_CTRL_11N 0x80C36#define DM_REG_BB_PWR_SAV5_11N 0x81837#define DM_REG_CCK_RPT_FORMAT_11N 0x82438#define DM_REG_RX_DEFUALT_A_11N 0x85839#define DM_REG_RX_DEFUALT_B_11N 0x85A40#define DM_REG_BB_PWR_SAV3_11N 0x85C41#define DM_REG_ANTSEL_CTRL_11N 0x86042#define DM_REG_RX_ANT_CTRL_11N 0x86443#define DM_REG_PIN_CTRL_11N 0x87044#define DM_REG_BB_PWR_SAV1_11N 0x87445#define DM_REG_ANTSEL_PATH_11N 0x87846#define DM_REG_BB_3WIRE_11N 0x88C47#define DM_REG_SC_CNT_11N 0x8C448#define DM_REG_PSD_DATA_11N 0x8B449/*PAGE 9*/50#define DM_REG_ANT_MAPPING1_11N 0x91451#define DM_REG_ANT_MAPPING2_11N 0x91852/*PAGE A*/53#define DM_REG_CCK_ANTDIV_PARA1_11N 0xA0054#define DM_REG_CCK_CCA_11N 0xA0A55#define DM_REG_CCK_CCA_11AC 0xA0A56#define DM_REG_CCK_ANTDIV_PARA2_11N 0xA0C57#define DM_REG_CCK_ANTDIV_PARA3_11N 0xA1058#define DM_REG_CCK_ANTDIV_PARA4_11N 0xA1459#define DM_REG_CCK_FILTER_PARA1_11N 0xA2260#define DM_REG_CCK_FILTER_PARA2_11N 0xA2361#define DM_REG_CCK_FILTER_PARA3_11N 0xA2462#define DM_REG_CCK_FILTER_PARA4_11N 0xA2563#define DM_REG_CCK_FILTER_PARA5_11N 0xA2664#define DM_REG_CCK_FILTER_PARA6_11N 0xA2765#define DM_REG_CCK_FILTER_PARA7_11N 0xA2866#define DM_REG_CCK_FILTER_PARA8_11N 0xA2967#define DM_REG_CCK_FA_RST_11N 0xA2C68#define DM_REG_CCK_FA_MSB_11N 0xA5869#define DM_REG_CCK_FA_LSB_11N 0xA5C70#define DM_REG_CCK_CCA_CNT_11N 0xA6071#define DM_REG_BB_PWR_SAV4_11N 0xA7472/*PAGE B */73#define DM_REG_LNA_SWITCH_11N 0XB2C74#define DM_REG_PATH_SWITCH_11N 0XB3075#define DM_REG_RSSI_CTRL_11N 0XB3876#define DM_REG_CONFIG_ANTA_11N 0XB6877#define DM_REG_RSSI_BT_11N 0XB9C78/*PAGE C */79#define DM_REG_OFDM_FA_HOLDC_11N 0xC0080#define DM_REG_RX_PATH_11N 0xC0481#define DM_REG_TRMUX_11N 0xC0882#define DM_REG_OFDM_FA_RSTC_11N 0xC0C83#define DM_REG_RXIQI_MATRIX_11N 0xC1484#define DM_REG_TXIQK_MATRIX_LSB1_11N 0xC4C85#define DM_REG_IGI_A_11N 0xC5086#define DM_REG_IGI_A_11AC 0xC5087#define DM_REG_ANTDIV_PARA2_11N 0xC5488#define DM_REG_IGI_B_11N 0xC5889#define DM_REG_IGI_B_11AC 0xE5090#define DM_REG_ANTDIV_PARA3_11N 0xC5C91#define DM_REG_BB_PWR_SAV2_11N 0xC7092#define DM_REG_RX_OFF_11N 0xC7C93#define DM_REG_TXIQK_MATRIXA_11N 0xC8094#define DM_REG_TXIQK_MATRIXB_11N 0xC8895#define DM_REG_TXIQK_MATRIXA_LSB2_11N 0xC9496#define DM_REG_TXIQK_MATRIXB_LSB2_11N 0xC9C97#define DM_REG_RXIQK_MATRIX_LSB_11N 0xCA098#define DM_REG_ANTDIV_PARA1_11N 0xCA499#define DM_REG_OFDM_FA_TYPE1_11N 0xCF0100/*PAGE D */101#define DM_REG_OFDM_FA_RSTD_11N 0xD00102#define DM_REG_OFDM_FA_TYPE2_11N 0xDA0103#define DM_REG_OFDM_FA_TYPE3_11N 0xDA4104#define DM_REG_OFDM_FA_TYPE4_11N 0xDA8105/*PAGE E */106#define DM_REG_TXAGC_A_6_18_11N 0xE00107#define DM_REG_TXAGC_A_24_54_11N 0xE04108#define DM_REG_TXAGC_A_1_MCS32_11N 0xE08109#define DM_REG_TXAGC_A_MCS0_3_11N 0xE10110#define DM_REG_TXAGC_A_MCS4_7_11N 0xE14111#define DM_REG_TXAGC_A_MCS8_11_11N 0xE18112#define DM_REG_TXAGC_A_MCS12_15_11N 0xE1C113#define DM_REG_FPGA0_IQK_11N 0xE28114#define DM_REG_TXIQK_TONE_A_11N 0xE30115#define DM_REG_RXIQK_TONE_A_11N 0xE34116#define DM_REG_TXIQK_PI_A_11N 0xE38117#define DM_REG_RXIQK_PI_A_11N 0xE3C118#define DM_REG_TXIQK_11N 0xE40119#define DM_REG_RXIQK_11N 0xE44120#define DM_REG_IQK_AGC_PTS_11N 0xE48121#define DM_REG_IQK_AGC_RSP_11N 0xE4C122#define DM_REG_BLUETOOTH_11N 0xE6C123#define DM_REG_RX_WAIT_CCA_11N 0xE70124#define DM_REG_TX_CCK_RFON_11N 0xE74125#define DM_REG_TX_CCK_BBON_11N 0xE78126#define DM_REG_OFDM_RFON_11N 0xE7C127#define DM_REG_OFDM_BBON_11N 0xE80128#define DM_REG_TX2RX_11N 0xE84129#define DM_REG_TX2TX_11N 0xE88130#define DM_REG_RX_CCK_11N 0xE8C131#define DM_REG_RX_OFDM_11N 0xED0132#define DM_REG_RX_WAIT_RIFS_11N 0xED4133#define DM_REG_RX2RX_11N 0xED8134#define DM_REG_STANDBY_11N 0xEDC135#define DM_REG_SLEEP_11N 0xEE0136#define DM_REG_PMPD_ANAEN_11N 0xEEC137 138/*MAC REG LIST*/139#define DM_REG_BB_RST_11N 0x02140#define DM_REG_ANTSEL_PIN_11N 0x4C141#define DM_REG_EARLY_MODE_11N 0x4D0142#define DM_REG_RSSI_MONITOR_11N 0x4FE143#define DM_REG_EDCA_VO_11N 0x500144#define DM_REG_EDCA_VI_11N 0x504145#define DM_REG_EDCA_BE_11N 0x508146#define DM_REG_EDCA_BK_11N 0x50C147#define DM_REG_TXPAUSE_11N 0x522148#define DM_REG_RESP_TX_11N 0x6D8149#define DM_REG_ANT_TRAIN_PARA1_11N 0x7b0150#define DM_REG_ANT_TRAIN_PARA2_11N 0x7b4151 152/*DIG Related*/153#define DM_BIT_IGI_11N 0x0000007F154#define DM_BIT_IGI_11AC 0xFFFFFFFF155 156#define HAL_DM_DIG_DISABLE BIT(0)157#define HAL_DM_HIPWR_DISABLE BIT(1)158 159#define OFDM_TABLE_LENGTH 43160#define CCK_TABLE_LENGTH 33161 162#define OFDM_TABLE_SIZE 37163#define CCK_TABLE_SIZE 33164 165#define BW_AUTO_SWITCH_HIGH_LOW 25166#define BW_AUTO_SWITCH_LOW_HIGH 30167 168#define DM_DIG_FA_UPPER 0x3e169#define DM_DIG_FA_LOWER 0x1e170#define DM_DIG_FA_TH0 200171#define DM_DIG_FA_TH1 0x300172#define DM_DIG_FA_TH2 0x400173 174#define RXPATHSELECTION_SS_TH_LOW 30175#define RXPATHSELECTION_DIFF_TH 18176 177#define DM_RATR_STA_INIT 0178#define DM_RATR_STA_HIGH 1179#define DM_RATR_STA_MIDDLE 2180#define DM_RATR_STA_LOW 3181 182#define CTS2SELF_THVAL 30183#define REGC38_TH 20184 185#define WAIOTTHVAL 25186 187#define TXHIGHPWRLEVEL_NORMAL 0188#define TXHIGHPWRLEVEL_LEVEL1 1189#define TXHIGHPWRLEVEL_LEVEL2 2190#define TXHIGHPWRLEVEL_BT1 3191#define TXHIGHPWRLEVEL_BT2 4192 193#define DM_TYPE_BYFW 0194#define DM_TYPE_BYDRIVER 1195 196#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74197#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67198#define TXPWRTRACK_MAX_IDX 6199 200/* Dynamic ATC switch */201#define ATC_STATUS_OFF 0x0 /* enable */202#define ATC_STATUS_ON 0x1 /* disable */203#define CFO_THRESHOLD_XTAL 10 /* kHz */204#define CFO_THRESHOLD_ATC 80 /* kHz */205 206#define AVG_THERMAL_NUM_8812A 4207#define TXPWR_TRACK_TABLE_SIZE 30208#define MAX_PATH_NUM_8812A 2209#define MAX_PATH_NUM_8821A 1210 211enum FAT_STATE {212 FAT_NORMAL_STATE = 0,213 FAT_TRAINING_STATE = 1,214};215 216enum tag_dynamic_init_gain_operation_type_definition {217 DIG_TYPE_THRESH_HIGH = 0,218 DIG_TYPE_THRESH_LOW = 1,219 DIG_TYPE_BACKOFF = 2,220 DIG_TYPE_RX_GAIN_MIN = 3,221 DIG_TYPE_RX_GAIN_MAX = 4,222 DIG_TYPE_ENABLE = 5,223 DIG_TYPE_DISABLE = 6,224 DIG_OP_TYPE_MAX225};226 227enum dm_1r_cca_e {228 CCA_1R = 0,229 CCA_2R = 1,230 CCA_MAX = 2,231};232 233enum dm_rf_e {234 RF_SAVE = 0,235 RF_NORMAL = 1,236 RF_MAX = 2,237};238 239enum dm_sw_ant_switch_e {240 ANS_ANTENNA_B = 1,241 ANS_ANTENNA_A = 2,242 ANS_ANTENNA_MAX = 3,243};244 245enum pwr_track_control_method {246 BBSWING,247 TXAGC,248 MIX_MODE249};250 251#define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1)252#define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1)253#define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)254#define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1)255#define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1)256#define GET_UNDECORATED_AVERAGE_RSSI(_priv) \257 ((((struct rtl_priv *)(_priv))->mac80211.opmode == \258 NL80211_IFTYPE_ADHOC) ? \259 (((struct rtl_priv *)(_priv))->dm.entry_min_undec_sm_pwdb) : \260 (((struct rtl_priv *)(_priv))->dm.undec_sm_pwdb))261 262void rtl8821ae_dm_set_tx_ant_by_tx_info(struct ieee80211_hw *hw,263 u8 *pdesc, u32 mac_id);264void rtl8821ae_dm_ant_sel_statistics(struct ieee80211_hw *hw,265 u8 antsel_tr_mux, u32 mac_id,266 u32 rx_pwdb_all);267void rtl8821ae_dm_fast_antenna_training_callback(unsigned long data);268void rtl8821ae_dm_init(struct ieee80211_hw *hw);269void rtl8821ae_dm_watchdog(struct ieee80211_hw *hw);270void rtl8821ae_dm_write_dig(struct ieee80211_hw *hw, u8 current_igi);271void rtl8821ae_dm_init_edca_turbo(struct ieee80211_hw *hw);272void rtl8821ae_dm_check_txpower_tracking_thermalmeter(struct ieee80211_hw *hw);273void rtl8821ae_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);274void rtl8821ae_dm_txpower_track_adjust(struct ieee80211_hw *hw,275 u8 type, u8 *pdirection,276 u32 *poutwrite_val);277void rtl8821ae_dm_clear_txpower_tracking_state(struct ieee80211_hw *hw);278void rtl8821ae_dm_write_cck_cca_thres(struct ieee80211_hw *hw, u8 current_cca);279void rtl8821ae_dm_initialize_txpower_tracking_thermalmeter(struct ieee80211_hw *hw);280void rtl8812ae_dm_txpwr_track_set_pwr(struct ieee80211_hw *hw,281 enum pwr_track_control_method method,282 u8 rf_path,283 u8 channel_mapped_index);284void rtl8821ae_dm_txpwr_track_set_pwr(struct ieee80211_hw *hw,285 enum pwr_track_control_method method,286 u8 rf_path, u8 channel_mapped_index);287 288void rtl8821ae_dm_update_init_rate(struct ieee80211_hw *hw, u8 rate);289u8 rtl8821ae_hw_rate_to_mrate(struct ieee80211_hw *hw, u8 rate);290void rtl8812ae_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw);291void rtl8821ae_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw *hw);292 293#endif294