2445 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/* Copyright(c) 2009-2010 Realtek Corporation.*/3 4#ifndef __RTL8821AE_REG_H__5#define __RTL8821AE_REG_H__6 7#define TXPKT_BUF_SELECT 0x698#define RXPKT_BUF_SELECT 0xA59#define DISABLE_TRXPKT_BUF_ACCESS 0x010 11#define REG_SYS_ISO_CTRL 0x000012#define REG_SYS_FUNC_EN 0x000213#define REG_APS_FSMCO 0x000414#define REG_SYS_CLKR 0x000815#define REG_9346CR 0x000A16#define REG_EE_VPD 0x000C17#define REG_AFE_MISC 0x001018#define REG_SPS0_CTRL 0x001119#define REG_SPS_OCP_CFG 0x001820#define REG_RSV_CTRL 0x001C21#define REG_RF_CTRL 0x001F22#define REG_LDOA15_CTRL 0x002023#define REG_LDOV12D_CTRL 0x002124#define REG_LDOHCI12_CTRL 0x002225#define REG_LPLDO_CTRL 0x002326#define REG_AFE_XTAL_CTRL 0x002427 /* 1.5v for 8188EE test chip, 1.4v for MP chip */28#define REG_AFE_LDO_CTRL 0x002729#define REG_AFE_PLL_CTRL 0x002830#define REG_MAC_PHY_CTRL 0x002c31#define REG_EFUSE_CTRL 0x003032#define REG_EFUSE_TEST 0x003433#define REG_PWR_DATA 0x003834#define REG_CAL_TIMER 0x003C35#define REG_ACLK_MON 0x003E36#define REG_GPIO_MUXCFG 0x004037#define REG_GPIO_IO_SEL 0x004238#define REG_MAC_PINMUX_CFG 0x004339#define REG_GPIO_PIN_CTRL 0x004440#define REG_GPIO_INTM 0x004841#define REG_LEDCFG0 0x004C42#define REG_LEDCFG1 0x004D43#define REG_LEDCFG2 0x004E44#define REG_LEDCFG3 0x004F45#define REG_FSIMR 0x005046#define REG_FSISR 0x005447#define REG_HSIMR 0x005848#define REG_HSISR 0x005c49#define REG_GPIO_PIN_CTRL_2 0x006050#define REG_GPIO_IO_SEL_2 0x006251#define REG_MULTI_FUNC_CTRL 0x006852#define REG_GPIO_OUTPUT 0x006c53#define REG_OPT_CTRL 0x007454#define REG_AFE_XTAL_CTRL_EXT 0x007855#define REG_XCK_OUT_CTRL 0x007c56#define REG_MCUFWDL 0x008057#define REG_WOL_EVENT 0x008158#define REG_MCUTSTCFG 0x008459 60#define REG_HIMR 0x00B061#define REG_HISR 0x00B462#define REG_HIMRE 0x00B863#define REG_HISRE 0x00BC64 65#define REG_PMC_DBG_CTRL2 0x00CC66 67#define REG_EFUSE_ACCESS 0x00CF68 69#define REG_BIST_SCAN 0x00D070#define REG_BIST_RPT 0x00D471#define REG_BIST_ROM_RPT 0x00D872#define REG_USB_SIE_INTF 0x00E073#define REG_PCIE_MIO_INTF 0x00E474#define REG_PCIE_MIO_INTD 0x00E875#define REG_HPON_FSM 0x00EC76#define REG_SYS_CFG 0x00F077#define REG_GPIO_OUTSTS 0x00F478#define REG_MAC_PHY_CTRL_NORMAL 0x00F879#define REG_SYS_CFG1 0x00FC80#define REG_ROM_VERSION 0x00FD81 82#define REG_CR 0x010083#define REG_PBP 0x010484#define REG_PKT_BUFF_ACCESS_CTRL 0x010685#define REG_TRXDMA_CTRL 0x010C86#define REG_TRXFF_BNDY 0x011487#define REG_TRXFF_STATUS 0x011888#define REG_RXFF_PTR 0x011C89 90#define REG_CPWM 0x012F91#define REG_FWIMR 0x013092#define REG_FWISR 0x013493#define REG_FTISR 0x013C94#define REG_PKTBUF_DBG_CTRL 0x014095#define REG_PKTBUF_DBG_DATA_L 0x014496#define REG_PKTBUF_DBG_DATA_H 0x014897#define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2)98 99#define REG_TC0_CTRL 0x0150100#define REG_TC1_CTRL 0x0154101#define REG_TC2_CTRL 0x0158102#define REG_TC3_CTRL 0x015C103#define REG_TC4_CTRL 0x0160104#define REG_TCUNIT_BASE 0x0164105#define REG_MBIST_START 0x0174106#define REG_MBIST_DONE 0x0178107#define REG_MBIST_FAIL 0x017C108#define REG_32K_CTRL 0x0194109#define REG_C2HEVT_MSG_NORMAL 0x01A0110#define REG_C2HEVT_CLEAR 0x01AF111#define REG_C2HEVT_MSG_TEST 0x01B8112#define REG_MCUTST_1 0x01c0113#define REG_MCUTST_WOWLAN 0x01C7114#define REG_FMETHR 0x01C8115#define REG_HMETFR 0x01CC116#define REG_HMEBOX_0 0x01D0117#define REG_HMEBOX_1 0x01D4118#define REG_HMEBOX_2 0x01D8119#define REG_HMEBOX_3 0x01DC120 121#define REG_LLT_INIT 0x01E0122#define REG_BB_ACCEESS_CTRL 0x01E8123#define REG_BB_ACCESS_DATA 0x01EC124 125#define REG_HMEBOX_EXT_0 0x01F0126#define REG_HMEBOX_EXT_1 0x01F4127#define REG_HMEBOX_EXT_2 0x01F8128#define REG_HMEBOX_EXT_3 0x01FC129 130#define REG_RQPN 0x0200131#define REG_FIFOPAGE 0x0204132#define REG_TDECTRL 0x0208133#define REG_TXDMA_OFFSET_CHK 0x020C134#define REG_TXDMA_STATUS 0x0210135#define REG_RQPN_NPQ 0x0214136 137#define REG_RXDMA_AGG_PG_TH 0x0280138 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */139#define REG_FW_UPD_RDPTR 0x0284140 /* Control the RX DMA.*/141#define REG_RXDMA_CONTROL 0x0286142/* The number of packets in RXPKTBUF. */143#define REG_RXPKT_NUM 0x0287144 145#define REG_PCIE_CTRL_REG 0x0300146#define REG_INT_MIG 0x0304147#define REG_BCNQ_DESA 0x0308148#define REG_HQ_DESA 0x0310149#define REG_MGQ_DESA 0x0318150#define REG_VOQ_DESA 0x0320151#define REG_VIQ_DESA 0x0328152#define REG_BEQ_DESA 0x0330153#define REG_BKQ_DESA 0x0338154#define REG_RX_DESA 0x0340155 156#define REG_DBI_WDATA 0x0348157#define REG_DBI_RDATA 0x034C158#define REG_DBI_CTRL 0x0350159#define REG_DBI_ADDR 0x0350160#define REG_DBI_FLAG 0x0352161#define REG_MDIO_WDATA 0x0354162#define REG_MDIO_RDATA 0x0356163#define REG_MDIO_CTL 0x0358164#define REG_DBG_SEL 0x0360165#define REG_PCIE_HRPWM 0x0361166#define REG_PCIE_HCPWM 0x0363167#define REG_UART_CTRL 0x0364168#define REG_WATCH_DOG 0x0368169#define REG_UART_TX_DESA 0x0370170#define REG_UART_RX_DESA 0x0378171 172#define REG_HDAQ_DESA_NODEF 0x0000173#define REG_CMDQ_DESA_NODEF 0x0000174 175#define REG_VOQ_INFORMATION 0x0400176#define REG_VIQ_INFORMATION 0x0404177#define REG_BEQ_INFORMATION 0x0408178#define REG_BKQ_INFORMATION 0x040C179#define REG_MGQ_INFORMATION 0x0410180#define REG_HGQ_INFORMATION 0x0414181#define REG_BCNQ_INFORMATION 0x0418182#define REG_TXPKT_EMPTY 0x041A183 184#define REG_CPU_MGQ_INFORMATION 0x041C185#define REG_FWHW_TXQ_CTRL 0x0420186#define REG_HWSEQ_CTRL 0x0423187#define REG_TXPKTBUF_BCNQ_BDNY 0x0424188#define REG_TXPKTBUF_MGQ_BDNY 0x0425189#define REG_MULTI_BCNQ_EN 0x0426190#define REG_MULTI_BCNQ_OFFSET 0x0427191#define REG_SPEC_SIFS 0x0428192#define REG_RL 0x042A193#define REG_DARFRC 0x0430194#define REG_RARFRC 0x0438195#define REG_RRSR 0x0440196#define REG_ARFR0 0x0444197#define REG_ARFR1 0x044C198#define REG_CCK_CHECK 0x0454199#define REG_AMPDU_MAX_TIME 0x0456200#define REG_AGGLEN_LMT 0x0458201#define REG_AMPDU_MIN_SPACE 0x045C202#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D203#define REG_FAST_EDCA_CTRL 0x0460204#define REG_RD_RESP_PKT_TH 0x0463205#define REG_INIRTS_RATE_SEL 0x0480206#define REG_INIDATA_RATE_SEL 0x0484207#define REG_ARFR2 0x048C208#define REG_ARFR3 0x0494209#define REG_POWER_STATUS 0x04A4210#define REG_POWER_STAGE1 0x04B4211#define REG_POWER_STAGE2 0x04B8212#define REG_PKT_LIFE_TIME 0x04C0213#define REG_STBC_SETTING 0x04C4214#define REG_HT_SINGLE_AMPDU 0x04C7215#define REG_PROT_MODE_CTRL 0x04C8216#define REG_MAX_AGGR_NUM 0x04CA217#define REG_BAR_MODE_CTRL 0x04CC218#define REG_RA_TRY_RATE_AGG_LMT 0x04CF219#define REG_EARLY_MODE_CONTROL 0x04D0220#define REG_NQOS_SEQ 0x04DC221#define REG_QOS_SEQ 0x04DE222#define REG_NEED_CPU_HANDLE 0x04E0223#define REG_PKT_LOSE_RPT 0x04E1224#define REG_PTCL_ERR_STATUS 0x04E2225#define REG_TX_RPT_CTRL 0x04EC226#define REG_TX_RPT_TIME 0x04F0227#define REG_DUMMY 0x04FC228 229#define REG_EDCA_VO_PARAM 0x0500230#define REG_EDCA_VI_PARAM 0x0504231#define REG_EDCA_BE_PARAM 0x0508232#define REG_EDCA_BK_PARAM 0x050C233#define REG_BCNTCFG 0x0510234#define REG_PIFS 0x0512235#define REG_RDG_PIFS 0x0513236#define REG_SIFS_CTX 0x0514237#define REG_SIFS_TRX 0x0516238#define REG_AGGR_BREAK_TIME 0x051A239#define REG_SLOT 0x051B240#define REG_TX_PTCL_CTRL 0x0520241#define REG_TXPAUSE 0x0522242#define REG_DIS_TXREQ_CLR 0x0523243#define REG_RD_CTRL 0x0524244#define REG_TBTT_PROHIBIT 0x0540245#define REG_RD_NAV_NXT 0x0544246#define REG_NAV_PROT_LEN 0x0546247#define REG_BCN_CTRL 0x0550248#define REG_MBID_NUM 0x0552249#define REG_DUAL_TSF_RST 0x0553250#define REG_BCN_INTERVAL 0x0554251#define REG_MBSSID_BCN_SPACE 0x0554252#define REG_DRVERLYINT 0x0558253#define REG_BCNDMATIM 0x0559254#define REG_ATIMWND 0x055A255#define REG_USTIME_TSF 0x055C256#define REG_BCN_MAX_ERR 0x055D257#define REG_RXTSF_OFFSET_CCK 0x055E258#define REG_RXTSF_OFFSET_OFDM 0x055F259#define REG_TSFTR 0x0560260#define REG_INIT_TSFTR 0x0564261#define REG_SECONDARY_CCA_CTRL 0x0577262#define REG_PSTIMER 0x0580263#define REG_TIMER0 0x0584264#define REG_TIMER1 0x0588265#define REG_ACMHWCTRL 0x05C0266#define REG_ACMRSTCTRL 0x05C1267#define REG_ACMAVG 0x05C2268#define REG_VO_ADMTIME 0x05C4269#define REG_VI_ADMTIME 0x05C6270#define REG_BE_ADMTIME 0x05C8271#define REG_EDCA_RANDOM_GEN 0x05CC272#define REG_NOA_DESC_SEL 0x05CF273#define REG_NOA_DESC_DURATION 0x05E0274#define REG_NOA_DESC_INTERVAL 0x05E4275#define REG_NOA_DESC_START 0x05E8276#define REG_NOA_DESC_COUNT 0x05EC277#define REG_SCH_TXCMD 0x05F8278 279#define REG_APSD_CTRL 0x0600280#define REG_BWOPMODE 0x0603281#define REG_TCR 0x0604282#define REG_RCR 0x0608283#define REG_RX_PKT_LIMIT 0x060C284#define REG_RX_DLK_TIME 0x060D285#define REG_RX_DRVINFO_SZ 0x060F286 287#define REG_MACID 0x0610288#define REG_BSSID 0x0618289#define REG_MAR 0x0620290#define REG_MBIDCAMCFG 0x0628291 292#define REG_USTIME_EDCA 0x0638293#define REG_MAC_SPEC_SIFS 0x063A294#define REG_RESP_SIFS_CCK 0x063C295#define REG_RESP_SIFS_OFDM 0x063E296#define REG_ACKTO 0x0640297#define REG_CTS2TO 0x0641298#define REG_EIFS 0x0642299 300#define REG_NAV_CTRL 0x0650301#define REG_NAV_UPPER 0x0652302#define REG_BACAMCMD 0x0654303#define REG_BACAMCONTENT 0x0658304#define REG_LBDLY 0x0660305#define REG_FWDLY 0x0661306#define REG_RXERR_RPT 0x0664307#define REG_TRXPTCL_CTL 0x0668308 309#define REG_CAMCMD 0x0670310#define REG_CAMWRITE 0x0674311#define REG_CAMREAD 0x0678312#define REG_CAMDBG 0x067C313#define REG_SECCFG 0x0680314 315#define REG_WOW_CTRL 0x0690316#define REG_PSSTATUS 0x0691317#define REG_PS_RX_INFO 0x0692318#define REG_UAPSD_TID 0x0693319#define REG_LPNAV_CTRL 0x0694320#define REG_WKFMCAM_NUM 0x0698321#define REG_WKFMCAM_RWD 0x069C322#define REG_RXFLTMAP0 0x06A0323#define REG_RXFLTMAP1 0x06A2324#define REG_RXFLTMAP2 0x06A4325#define REG_BCN_PSR_RPT 0x06A8326#define REG_CALB32K_CTRL 0x06AC327#define REG_PKT_MON_CTRL 0x06B4328#define REG_BT_COEX_TABLE 0x06C0329#define REG_WMAC_RESP_TXINFO 0x06D8330 331#define REG_USB_INFO 0xFE17332#define REG_USB_SPECIAL_OPTION 0xFE55333#define REG_USB_DMA_AGG_TO 0xFE5B334#define REG_USB_AGG_TO 0xFE5C335#define REG_USB_AGG_TH 0xFE5D336 337#define REG_TEST_USB_TXQS 0xFE48338#define REG_TEST_SIE_VID 0xFE60339#define REG_TEST_SIE_PID 0xFE62340#define REG_TEST_SIE_OPTIONAL 0xFE64341#define REG_TEST_SIE_CHIRP_K 0xFE65342#define REG_TEST_SIE_PHY 0xFE66343#define REG_TEST_SIE_MAC_ADDR 0xFE70344#define REG_TEST_SIE_STRING 0xFE80345 346#define REG_NORMAL_SIE_VID 0xFE60347#define REG_NORMAL_SIE_PID 0xFE62348#define REG_NORMAL_SIE_OPTIONAL 0xFE64349#define REG_NORMAL_SIE_EP 0xFE65350#define REG_NORMAL_SIE_PHY 0xFE68351#define REG_NORMAL_SIE_MAC_ADDR 0xFE70352#define REG_NORMAL_SIE_STRING 0xFE80353 354#define CR9346 REG_9346CR355#define MSR (REG_CR + 2)356#define ISR REG_HISR357#define TSFR REG_TSFTR358 359#define MACIDR0 REG_MACID360#define MACIDR4 (REG_MACID + 4)361 362#define PBP REG_PBP363 364#define IDR0 MACIDR0365#define IDR4 MACIDR4366 367#define UNUSED_REGISTER 0x1BF368#define DCAM UNUSED_REGISTER369#define PSR UNUSED_REGISTER370#define BBADDR UNUSED_REGISTER371#define PHYDATAR UNUSED_REGISTER372 373#define INVALID_BBRF_VALUE 0x12345678374 375#define MAX_MSS_DENSITY_2T 0x13376#define MAX_MSS_DENSITY_1T 0x0A377 378#define CMDEEPROM_EN BIT(5)379#define CMDEEPROM_SEL BIT(4)380#define CMD9346CR_9356SEL BIT(4)381#define AUTOLOAD_EEPROM (CMDEEPROM_EN|CMDEEPROM_SEL)382#define AUTOLOAD_EFUSE CMDEEPROM_EN383 384#define GPIOSEL_GPIO 0385#define GPIOSEL_ENBT BIT(5)386 387#define GPIO_IN REG_GPIO_PIN_CTRL388#define GPIO_OUT (REG_GPIO_PIN_CTRL+1)389#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2)390#define GPIO_MOD (REG_GPIO_PIN_CTRL+3)391 392/* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */393#define HSIMR_GPIO12_0_INT_EN BIT(0)394#define HSIMR_SPS_OCP_INT_EN BIT(5)395#define HSIMR_RON_INT_EN BIT(6)396#define HSIMR_PDN_INT_EN BIT(7)397#define HSIMR_GPIO9_INT_EN BIT(25)398 399/* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */400#define HSISR_GPIO12_0_INT BIT(0)401#define HSISR_SPS_OCP_INT BIT(5)402#define HSISR_RON_INT_EN BIT(6)403#define HSISR_PDNINT BIT(7)404#define HSISR_GPIO9_INT BIT(25)405 406#define MSR_NOLINK 0x00407#define MSR_ADHOC 0x01408#define MSR_INFRA 0x02409#define MSR_AP 0x03410#define MSR_MASK 0x03411 412#define RRSR_RSC_OFFSET 21413#define RRSR_SHORT_OFFSET 23414#define RRSR_RSC_BW_40M 0x600000415#define RRSR_RSC_UPSUBCHNL 0x400000416#define RRSR_RSC_LOWSUBCHNL 0x200000417#define RRSR_SHORT 0x800000418#define RRSR_1M BIT(0)419#define RRSR_2M BIT(1)420#define RRSR_5_5M BIT(2)421#define RRSR_11M BIT(3)422#define RRSR_6M BIT(4)423#define RRSR_9M BIT(5)424#define RRSR_12M BIT(6)425#define RRSR_18M BIT(7)426#define RRSR_24M BIT(8)427#define RRSR_36M BIT(9)428#define RRSR_48M BIT(10)429#define RRSR_54M BIT(11)430#define RRSR_MCS0 BIT(12)431#define RRSR_MCS1 BIT(13)432#define RRSR_MCS2 BIT(14)433#define RRSR_MCS3 BIT(15)434#define RRSR_MCS4 BIT(16)435#define RRSR_MCS5 BIT(17)436#define RRSR_MCS6 BIT(18)437#define RRSR_MCS7 BIT(19)438#define BRSR_ACKSHORTPMB BIT(23)439 440#define RATR_1M 0x00000001441#define RATR_2M 0x00000002442#define RATR_55M 0x00000004443#define RATR_11M 0x00000008444#define RATR_6M 0x00000010445#define RATR_9M 0x00000020446#define RATR_12M 0x00000040447#define RATR_18M 0x00000080448#define RATR_24M 0x00000100449#define RATR_36M 0x00000200450#define RATR_48M 0x00000400451#define RATR_54M 0x00000800452#define RATR_MCS0 0x00001000453#define RATR_MCS1 0x00002000454#define RATR_MCS2 0x00004000455#define RATR_MCS3 0x00008000456#define RATR_MCS4 0x00010000457#define RATR_MCS5 0x00020000458#define RATR_MCS6 0x00040000459#define RATR_MCS7 0x00080000460#define RATR_MCS8 0x00100000461#define RATR_MCS9 0x00200000462#define RATR_MCS10 0x00400000463#define RATR_MCS11 0x00800000464#define RATR_MCS12 0x01000000465#define RATR_MCS13 0x02000000466#define RATR_MCS14 0x04000000467#define RATR_MCS15 0x08000000468 469#define RATE_1M BIT(0)470#define RATE_2M BIT(1)471#define RATE_5_5M BIT(2)472#define RATE_11M BIT(3)473#define RATE_6M BIT(4)474#define RATE_9M BIT(5)475#define RATE_12M BIT(6)476#define RATE_18M BIT(7)477#define RATE_24M BIT(8)478#define RATE_36M BIT(9)479#define RATE_48M BIT(10)480#define RATE_54M BIT(11)481#define RATE_MCS0 BIT(12)482#define RATE_MCS1 BIT(13)483#define RATE_MCS2 BIT(14)484#define RATE_MCS3 BIT(15)485#define RATE_MCS4 BIT(16)486#define RATE_MCS5 BIT(17)487#define RATE_MCS6 BIT(18)488#define RATE_MCS7 BIT(19)489#define RATE_MCS8 BIT(20)490#define RATE_MCS9 BIT(21)491#define RATE_MCS10 BIT(22)492#define RATE_MCS11 BIT(23)493#define RATE_MCS12 BIT(24)494#define RATE_MCS13 BIT(25)495#define RATE_MCS14 BIT(26)496#define RATE_MCS15 BIT(27)497 498#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M)499#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M |\500 RATR_24M | RATR_36M | RATR_48M | RATR_54M)501#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 |\502 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 |\503 RATR_MCS6 | RATR_MCS7)504#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 |\505 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 |\506 RATR_MCS14 | RATR_MCS15)507 508#define BW_OPMODE_20MHZ BIT(2)509#define BW_OPMODE_5G BIT(1)510#define BW_OPMODE_11J BIT(0)511 512#define CAM_VALID BIT(15)513#define CAM_NOTVALID 0x0000514#define CAM_USEDK BIT(5)515 516#define CAM_NONE 0x0517#define CAM_WEP40 0x01518#define CAM_TKIP 0x02519#define CAM_AES 0x04520#define CAM_WEP104 0x05521 522#define TOTAL_CAM_ENTRY 32523#define HALF_CAM_ENTRY 16524 525#define CAM_WRITE BIT(16)526#define CAM_READ 0x00000000527#define CAM_POLLINIG BIT(31)528 529#define SCR_USEDK 0x01530#define SCR_TXSEC_ENABLE 0x02531#define SCR_RXSEC_ENABLE 0x04532 533#define WOW_PMEN BIT(0)534#define WOW_WOMEN BIT(1)535#define WOW_MAGIC BIT(2)536#define WOW_UWF BIT(3)537 538/*********************************************539* 8188 IMR/ISR bits540**********************************************/541#define IMR_DISABLED 0x0542/* IMR DW0(0x0060-0063) Bit 0-31 */543/* TXRPT interrupt when CCX bit of the packet is set */544#define IMR_TXCCK BIT(30)545/* Power Save Time Out Interrupt */546#define IMR_PSTIMEOUT BIT(29)547/* When GTIMER4 expires, this bit is set to 1 */548#define IMR_GTINT4 BIT(28)549/* When GTIMER3 expires, this bit is set to 1 */550#define IMR_GTINT3 BIT(27)551/* Transmit Beacon0 Error */552#define IMR_TBDER BIT(26)553/* Transmit Beacon0 OK */554#define IMR_TBDOK BIT(25)555/* TSF Timer BIT32 toggle indication interrupt */556#define IMR_TSF_BIT32_TOGGLE BIT(24)557/* Beacon DMA Interrupt 0 */558#define IMR_BCNDMAINT0 BIT(20)559/* Beacon Queue DMA OK0 */560#define IMR_BCNDOK0 BIT(16)561/* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */562#define IMR_HSISR_IND_ON_INT BIT(15)563/* Beacon DMA Interrupt Extension for Win7 */564#define IMR_BCNDMAINT_E BIT(14)565/* CTWidnow End or ATIM Window End */566#define IMR_ATIMEND BIT(12)567/* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1)*/568#define IMR_HISR1_IND_INT BIT(11)569/* CPU to Host Command INT Status, Write 1 clear */570#define IMR_C2HCMD BIT(10)571/* CPU power Mode exchange INT Status, Write 1 clear */572#define IMR_CPWM2 BIT(9)573/* CPU power Mode exchange INT Status, Write 1 clear */574#define IMR_CPWM BIT(8)575/* High Queue DMA OK */576#define IMR_HIGHDOK BIT(7)577/* Management Queue DMA OK */578#define IMR_MGNTDOK BIT(6)579/* AC_BK DMA OK */580#define IMR_BKDOK BIT(5)581/* AC_BE DMA OK */582#define IMR_BEDOK BIT(4)583/* AC_VI DMA OK */584#define IMR_VIDOK BIT(3)585/* AC_VO DMA OK */586#define IMR_VODOK BIT(2)587/* Rx Descriptor Unavailable */588#define IMR_RDU BIT(1)589#define IMR_ROK BIT(0) /* Receive DMA OK */590 591/* IMR DW1(0x00B4-00B7) Bit 0-31 */592/* Beacon DMA Interrupt 7 */593#define IMR_BCNDMAINT7 BIT(27)594/* Beacon DMA Interrupt 6 */595#define IMR_BCNDMAINT6 BIT(26)596/* Beacon DMA Interrupt 5 */597#define IMR_BCNDMAINT5 BIT(25)598/* Beacon DMA Interrupt 4 */599#define IMR_BCNDMAINT4 BIT(24)600/* Beacon DMA Interrupt 3 */601#define IMR_BCNDMAINT3 BIT(23)602/* Beacon DMA Interrupt 2 */603#define IMR_BCNDMAINT2 BIT(22)604/* Beacon DMA Interrupt 1 */605#define IMR_BCNDMAINT1 BIT(21)606/* Beacon Queue DMA OK Interrup 7 */607#define IMR_BCNDOK7 BIT(20)608/* Beacon Queue DMA OK Interrup 6 */609#define IMR_BCNDOK6 BIT(19)610/* Beacon Queue DMA OK Interrup 5 */611#define IMR_BCNDOK5 BIT(18)612/* Beacon Queue DMA OK Interrup 4 */613#define IMR_BCNDOK4 BIT(17)614/* Beacon Queue DMA OK Interrup 3 */615#define IMR_BCNDOK3 BIT(16)616/* Beacon Queue DMA OK Interrup 2 */617#define IMR_BCNDOK2 BIT(15)618/* Beacon Queue DMA OK Interrup 1 */619#define IMR_BCNDOK1 BIT(14)620/* ATIM Window End Extension for Win7 */621#define IMR_ATIMEND_E BIT(13)622/* Tx Error Flag Interrupt Status, write 1 clear. */623#define IMR_TXERR BIT(11)624/* Rx Error Flag INT Status, Write 1 clear */625#define IMR_RXERR BIT(10)626/* Transmit FIFO Overflow */627#define IMR_TXFOVW BIT(9)628/* Receive FIFO Overflow */629#define IMR_RXFOVW BIT(8)630 631#define HWSET_MAX_SIZE 512632#define EFUSE_MAX_SECTION 64633#define EFUSE_REAL_CONTENT_LEN 256634/* PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte.*/635#define EFUSE_OOB_PROTECT_BYTES 18636 637#define EEPROM_DEFAULT_TSSI 0x0638#define EEPROM_DEFAULT_TXPOWERDIFF 0x0639#define EEPROM_DEFAULT_CRYSTALCAP 0x5640#define EEPROM_DEFAULT_BOARDTYPE 0x02641#define EEPROM_DEFAULT_TXPOWER 0x1010642#define EEPROM_DEFAULT_HT2T_TXPWR 0x10643 644#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3645#define EEPROM_DEFAULT_THERMALMETER 0x18646#define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0647#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5648#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22649#define EEPROM_DEFAULT_HT40_2SDIFF 0x0650#define EEPROM_DEFAULT_HT20_DIFF 2651#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3652#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0653#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0654 655#define RF_OPTION1 0x79656#define RF_OPTION2 0x7A657#define RF_OPTION3 0x7B658#define RF_OPTION4 0xC3659 660#define EEPROM_DEFAULT_PID 0x1234661#define EEPROM_DEFAULT_VID 0x5678662#define EEPROM_DEFAULT_CUSTOMERID 0xAB663#define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD664#define EEPROM_DEFAULT_VERSION 0665 666#define EEPROM_CHANNEL_PLAN_FCC 0x0667#define EEPROM_CHANNEL_PLAN_IC 0x1668#define EEPROM_CHANNEL_PLAN_ETSI 0x2669#define EEPROM_CHANNEL_PLAN_SPAIN 0x3670#define EEPROM_CHANNEL_PLAN_FRANCE 0x4671#define EEPROM_CHANNEL_PLAN_MKK 0x5672#define EEPROM_CHANNEL_PLAN_MKK1 0x6673#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7674#define EEPROM_CHANNEL_PLAN_TELEC 0x8675#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9676#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA677#define EEPROM_CHANNEL_PLAN_NCC 0XB678#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80679 680#define EEPROM_CID_DEFAULT 0x0681#define EEPROM_CID_TOSHIBA 0x4682#define EEPROM_CID_CCX 0x10683#define EEPROM_CID_QMI 0x0D684#define EEPROM_CID_WHQL 0xFE685 686#define RTL_EEPROM_ID 0x8129687 688#define EEPROM_HPON 0x02689#define EEPROM_CLK 0x06690#define EEPROM_TESTR 0x08691 692#define EEPROM_TXPOWERCCK 0x10693#define EEPROM_TXPOWERHT40_1S 0x16694#define EEPROM_TXPOWERHT20DIFF 0x1B695#define EEPROM_TXPOWER_OFDMDIFF 0x1B696 697#define EEPROM_TX_PWR_INX 0x10698 699#define EEPROM_CHANNELPLAN 0XB8700#define EEPROM_XTAL_8821AE 0XB9701#define EEPROM_THERMAL_METER 0XBA702#define EEPROM_IQK_LCK_88E 0XBB703 704#define EEPROM_RF_BOARD_OPTION 0xC1705#define EEPROM_RF_FEATURE_OPTION_88E 0xC2706#define EEPROM_RF_BT_SETTING 0xC3707#define EEPROM_VERSION 0xC4708#define EEPROM_CUSTOMER_ID 0xC5709#define EEPROM_RF_ANTENNA_OPT_88E 0xC9710#define EEPROM_RFE_OPTION 0xCA711 712#define EEPROM_MAC_ADDR 0xD0713#define EEPROM_VID 0xD6714#define EEPROM_DID 0xD8715#define EEPROM_SVID 0xDA716#define EEPROM_SMID 0xDC717 718#define STOPBECON BIT(6)719#define STOPHIGHT BIT(5)720#define STOPMGT BIT(4)721#define STOPVO BIT(3)722#define STOPVI BIT(2)723#define STOPBE BIT(1)724#define STOPBK BIT(0)725 726#define RCR_APPFCS BIT(31)727#define RCR_APP_MIC BIT(30)728#define RCR_APP_ICV BIT(29)729#define RCR_APP_PHYST_RXFF BIT(28)730#define RCR_APP_BA_SSN BIT(27)731#define RCR_NONQOS_VHT BIT(26)732#define RCR_ENMBID BIT(24)733#define RCR_LSIGEN BIT(23)734#define RCR_MFBEN BIT(22)735#define RCR_HTC_LOC_CTRL BIT(14)736#define RCR_AMF BIT(13)737#define RCR_ACF BIT(12)738#define RCR_ADF BIT(11)739#define RCR_AICV BIT(9)740#define RCR_ACRC32 BIT(8)741#define RCR_CBSSID_BCN BIT(7)742#define RCR_CBSSID_DATA BIT(6)743#define RCR_CBSSID RCR_CBSSID_DATA744#define RCR_APWRMGT BIT(5)745#define RCR_ADD3 BIT(4)746#define RCR_AB BIT(3)747#define RCR_AM BIT(2)748#define RCR_APM BIT(1)749#define RCR_AAP BIT(0)750#define RCR_MXDMA_OFFSET 8751#define RCR_FIFO_OFFSET 13752 753#define RSV_CTRL 0x001C754#define RD_CTRL 0x0524755 756#define REG_USB_INFO 0xFE17757#define REG_USB_SPECIAL_OPTION 0xFE55758#define REG_USB_DMA_AGG_TO 0xFE5B759#define REG_USB_AGG_TO 0xFE5C760#define REG_USB_AGG_TH 0xFE5D761 762#define REG_USB_VID 0xFE60763#define REG_USB_PID 0xFE62764#define REG_USB_OPTIONAL 0xFE64765#define REG_USB_CHIRP_K 0xFE65766#define REG_USB_PHY 0xFE66767#define REG_USB_MAC_ADDR 0xFE70768#define REG_USB_HRPWM 0xFE58769#define REG_USB_HCPWM 0xFE57770 771#define SW18_FPWM BIT(3)772 773#define ISO_MD2PP BIT(0)774#define ISO_UA2USB BIT(1)775#define ISO_UD2CORE BIT(2)776#define ISO_PA2PCIE BIT(3)777#define ISO_PD2CORE BIT(4)778#define ISO_IP2MAC BIT(5)779#define ISO_DIOP BIT(6)780#define ISO_DIOE BIT(7)781#define ISO_EB2CORE BIT(8)782#define ISO_DIOR BIT(9)783 784#define PWC_EV25V BIT(14)785#define PWC_EV12V BIT(15)786 787#define FEN_BBRSTB BIT(0)788#define FEN_BB_GLB_RSTN BIT(1)789#define FEN_USBA BIT(2)790#define FEN_UPLL BIT(3)791#define FEN_USBD BIT(4)792#define FEN_DIO_PCIE BIT(5)793#define FEN_PCIEA BIT(6)794#define FEN_PPLL BIT(7)795#define FEN_PCIED BIT(8)796#define FEN_DIOE BIT(9)797#define FEN_CPUEN BIT(10)798#define FEN_DCORE BIT(11)799#define FEN_ELDR BIT(12)800#define FEN_DIO_RF BIT(13)801#define FEN_HWPDN BIT(14)802#define FEN_MREGEN BIT(15)803 804#define PFM_LDALL BIT(0)805#define PFM_ALDN BIT(1)806#define PFM_LDKP BIT(2)807#define PFM_WOWL BIT(3)808#define ENPDN BIT(4)809#define PDN_PL BIT(5)810#define APFM_ONMAC BIT(8)811#define APFM_OFF BIT(9)812#define APFM_RSM BIT(10)813#define AFSM_HSUS BIT(11)814#define AFSM_PCIE BIT(12)815#define APDM_MAC BIT(13)816#define APDM_HOST BIT(14)817#define APDM_HPDN BIT(15)818#define RDY_MACON BIT(16)819#define SUS_HOST BIT(17)820#define ROP_ALD BIT(20)821#define ROP_PWR BIT(21)822#define ROP_SPS BIT(22)823#define SOP_MRST BIT(25)824#define SOP_FUSE BIT(26)825#define SOP_ABG BIT(27)826#define SOP_AMB BIT(28)827#define SOP_RCK BIT(29)828#define SOP_A8M BIT(30)829#define XOP_BTCK BIT(31)830 831#define ANAD16V_EN BIT(0)832#define ANA8M BIT(1)833#define MACSLP BIT(4)834#define LOADER_CLK_EN BIT(5)835#define _80M_SSC_DIS BIT(7)836#define _80M_SSC_EN_HO BIT(8)837#define PHY_SSC_RSTB BIT(9)838#define SEC_CLK_EN BIT(10)839#define MAC_CLK_EN BIT(11)840#define SYS_CLK_EN BIT(12)841#define RING_CLK_EN BIT(13)842 843#define BOOT_FROM_EEPROM BIT(4)844#define EEPROM_EN BIT(5)845 846#define AFE_BGEN BIT(0)847#define AFE_MBEN BIT(1)848#define MAC_ID_EN BIT(7)849 850#define WLOCK_ALL BIT(0)851#define WLOCK_00 BIT(1)852#define WLOCK_04 BIT(2)853#define WLOCK_08 BIT(3)854#define WLOCK_40 BIT(4)855#define R_DIS_PRST_0 BIT(5)856#define R_DIS_PRST_1 BIT(6)857#define LOCK_ALL_EN BIT(7)858 859#define RF_EN BIT(0)860#define RF_RSTB BIT(1)861#define RF_SDMRSTB BIT(2)862 863#define LDA15_EN BIT(0)864#define LDA15_STBY BIT(1)865#define LDA15_OBUF BIT(2)866#define LDA15_REG_VOS BIT(3)867#define _LDA15_VOADJ(x) (((x) & 0x7) << 4)868 869#define LDV12_EN BIT(0)870#define LDV12_SDBY BIT(1)871#define LPLDO_HSM BIT(2)872#define LPLDO_LSM_DIS BIT(3)873#define _LDV12_VADJ(x) (((x) & 0xF) << 4)874 875#define XTAL_EN BIT(0)876#define XTAL_BSEL BIT(1)877#define _XTAL_BOSC(x) (((x) & 0x3) << 2)878#define _XTAL_CADJ(x) (((x) & 0xF) << 4)879#define XTAL_GATE_USB BIT(8)880#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9)881#define XTAL_GATE_AFE BIT(11)882#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12)883#define XTAL_RF_GATE BIT(14)884#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15)885#define XTAL_GATE_DIG BIT(17)886#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18)887#define XTAL_BT_GATE BIT(20)888#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21)889#define _XTAL_GPIO(x) (((x) & 0x7) << 23)890 891#define CKDLY_AFE BIT(26)892#define CKDLY_USB BIT(27)893#define CKDLY_DIG BIT(28)894#define CKDLY_BT BIT(29)895 896#define APLL_EN BIT(0)897#define APLL_320_EN BIT(1)898#define APLL_FREF_SEL BIT(2)899#define APLL_EDGE_SEL BIT(3)900#define APLL_WDOGB BIT(4)901#define APLL_LPFEN BIT(5)902 903#define APLL_REF_CLK_13MHZ 0x1904#define APLL_REF_CLK_19_2MHZ 0x2905#define APLL_REF_CLK_20MHZ 0x3906#define APLL_REF_CLK_25MHZ 0x4907#define APLL_REF_CLK_26MHZ 0x5908#define APLL_REF_CLK_38_4MHZ 0x6909#define APLL_REF_CLK_40MHZ 0x7910 911#define APLL_320EN BIT(14)912#define APLL_80EN BIT(15)913#define APLL_1MEN BIT(24)914 915#define ALD_EN BIT(18)916#define EF_PD BIT(19)917#define EF_FLAG BIT(31)918 919#define EF_TRPT BIT(7)920#define LDOE25_EN BIT(31)921 922#define RSM_EN BIT(0)923#define TIMER_EN BIT(4)924 925#define TRSW0EN BIT(2)926#define TRSW1EN BIT(3)927#define EROM_EN BIT(4)928#define ENBT BIT(5)929#define ENUART BIT(8)930#define UART_910 BIT(9)931#define ENPMAC BIT(10)932#define SIC_SWRST BIT(11)933#define ENSIC BIT(12)934#define SIC_23 BIT(13)935#define ENHDP BIT(14)936#define SIC_LBK BIT(15)937 938#define LED0PL BIT(4)939#define LED1PL BIT(12)940#define LED0DIS BIT(7)941 942#define MCUFWDL_EN BIT(0)943#define MCUFWDL_RDY BIT(1)944#define FWDL_CHKSUM_RPT BIT(2)945#define MACINI_RDY BIT(3)946#define BBINI_RDY BIT(4)947#define RFINI_RDY BIT(5)948#define WINTINI_RDY BIT(6)949#define CPRST BIT(23)950 951#define XCLK_VLD BIT(0)952#define ACLK_VLD BIT(1)953#define UCLK_VLD BIT(2)954#define PCLK_VLD BIT(3)955#define PCIRSTB BIT(4)956#define V15_VLD BIT(5)957#define TRP_B15V_EN BIT(7)958#define SIC_IDLE BIT(8)959#define BD_MAC2 BIT(9)960#define BD_MAC1 BIT(10)961#define IC_MACPHY_MODE BIT(11)962#define VENDOR_ID BIT(19)963#define PAD_HWPD_IDN BIT(22)964#define TRP_VAUX_EN BIT(23)965#define TRP_BT_EN BIT(24)966#define BD_PKG_SEL BIT(25)967#define BD_HCI_SEL BIT(26)968#define TYPE_ID BIT(27)969 970#define CHIP_VER_RTL_MASK 0xF000971#define CHIP_VER_RTL_SHIFT 12972 973#define REG_LBMODE (REG_CR + 3)974 975#define HCI_TXDMA_EN BIT(0)976#define HCI_RXDMA_EN BIT(1)977#define TXDMA_EN BIT(2)978#define RXDMA_EN BIT(3)979#define PROTOCOL_EN BIT(4)980#define SCHEDULE_EN BIT(5)981#define MACTXEN BIT(6)982#define MACRXEN BIT(7)983#define ENSWBCN BIT(8)984#define ENSEC BIT(9)985 986#define _NETTYPE(x) (((x) & 0x3) << 16)987#define MASK_NETTYPE 0x30000988#define NT_NO_LINK 0x0989#define NT_LINK_AD_HOC 0x1990#define NT_LINK_AP 0x2991#define NT_AS_AP 0x3992 993#define _LBMODE(x) (((x) & 0xF) << 24)994#define MASK_LBMODE 0xF000000995#define LOOPBACK_NORMAL 0x0996#define LOOPBACK_IMMEDIATELY 0XB997#define LOOPBACK_MAC_DELAY 0x3998#define LOOPBACK_PHY 0x1999#define LOOPBACK_DMA 0x71000 1001#define GET_RX_PAGE_SIZE(value) ((value) & 0xF)1002#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)1003#define _PSRX_MASK 0xF1004#define _PSTX_MASK 0xF01005#define _PSRX(x) (x)1006#define _PSTX(x) ((x) << 4)1007 1008#define PBP_64 0x01009#define PBP_128 0x11010#define PBP_256 0x21011#define PBP_512 0x31012#define PBP_1024 0x41013 1014#define RXDMA_ARBBW_EN BIT(0)1015#define RXSHFT_EN BIT(1)1016#define RXDMA_AGG_EN BIT(2)1017#define QS_VO_QUEUE BIT(8)1018#define QS_VI_QUEUE BIT(9)1019#define QS_BE_QUEUE BIT(10)1020#define QS_BK_QUEUE BIT(11)1021#define QS_MANAGER_QUEUE BIT(12)1022#define QS_HIGH_QUEUE BIT(13)1023 1024#define HQSEL_VOQ BIT(0)1025#define HQSEL_VIQ BIT(1)1026#define HQSEL_BEQ BIT(2)1027#define HQSEL_BKQ BIT(3)1028#define HQSEL_MGTQ BIT(4)1029#define HQSEL_HIQ BIT(5)1030 1031#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14)1032#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12)1033#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10)1034#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8)1035#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6)1036#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4)1037 1038#define QUEUE_LOW 11039#define QUEUE_NORMAL 21040#define QUEUE_HIGH 31041 1042#define _LLT_NO_ACTIVE 0x01043#define _LLT_WRITE_ACCESS 0x11044#define _LLT_READ_ACCESS 0x21045 1046#define _LLT_INIT_DATA(x) ((x) & 0xFF)1047#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)1048#define _LLT_OP(x) (((x) & 0x3) << 30)1049#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)1050 1051#define BB_WRITE_READ_MASK (BIT(31) | BIT(30))1052#define BB_WRITE_EN BIT(30)1053#define BB_READ_EN BIT(31)1054 1055#define _HPQ(x) ((x) & 0xFF)1056#define _LPQ(x) (((x) & 0xFF) << 8)1057#define _PUBQ(x) (((x) & 0xFF) << 16)1058#define _NPQ(x) ((x) & 0xFF)1059 1060#define HPQ_PUBLIC_DIS BIT(24)1061#define LPQ_PUBLIC_DIS BIT(25)1062#define LD_RQPN BIT(31)1063 1064#define BCN_VALID BIT(16)1065#define BCN_HEAD(x) (((x) & 0xFF) << 8)1066#define BCN_HEAD_MASK 0xFF001067 1068#define BLK_DESC_NUM_SHIFT 41069#define BLK_DESC_NUM_MASK 0xF1070 1071#define DROP_DATA_EN BIT(9)1072 1073#define EN_AMPDU_RTY_NEW BIT(7)1074 1075#define _INIRTSMCS_SEL(x) ((x) & 0x3F)1076 1077#define _SPEC_SIFS_CCK(x) ((x) & 0xFF)1078#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)1079 1080#define RATE_REG_BITMAP_ALL 0xFFFFF1081 1082#define _RRSC_BITMAP(x) ((x) & 0xFFFFF)1083 1084#define _RRSR_RSC(x) (((x) & 0x3) << 21)1085#define RRSR_RSC_RESERVED 0x01086#define RRSR_RSC_UPPER_SUBCHANNEL 0x11087#define RRSR_RSC_LOWER_SUBCHANNEL 0x21088#define RRSR_RSC_DUPLICATE_MODE 0x31089 1090#define USE_SHORT_G1 BIT(20)1091 1092#define _AGGLMT_MCS0(x) ((x) & 0xF)1093#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4)1094#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8)1095#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12)1096#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16)1097#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20)1098#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24)1099#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28)1100 1101#define RETRY_LIMIT_SHORT_SHIFT 81102#define RETRY_LIMIT_LONG_SHIFT 01103 1104#define _DARF_RC1(x) ((x) & 0x1F)1105#define _DARF_RC2(x) (((x) & 0x1F) << 8)1106#define _DARF_RC3(x) (((x) & 0x1F) << 16)1107#define _DARF_RC4(x) (((x) & 0x1F) << 24)1108#define _DARF_RC5(x) ((x) & 0x1F)1109#define _DARF_RC6(x) (((x) & 0x1F) << 8)1110#define _DARF_RC7(x) (((x) & 0x1F) << 16)1111#define _DARF_RC8(x) (((x) & 0x1F) << 24)1112 1113#define _RARF_RC1(x) ((x) & 0x1F)1114#define _RARF_RC2(x) (((x) & 0x1F) << 8)1115#define _RARF_RC3(x) (((x) & 0x1F) << 16)1116#define _RARF_RC4(x) (((x) & 0x1F) << 24)1117#define _RARF_RC5(x) ((x) & 0x1F)1118#define _RARF_RC6(x) (((x) & 0x1F) << 8)1119#define _RARF_RC7(x) (((x) & 0x1F) << 16)1120#define _RARF_RC8(x) (((x) & 0x1F) << 24)1121 1122#define AC_PARAM_TXOP_LIMIT_OFFSET 161123#define AC_PARAM_ECW_MAX_OFFSET 121124#define AC_PARAM_ECW_MIN_OFFSET 81125#define AC_PARAM_AIFS_OFFSET 01126 1127#define _AIFS(x) (x)1128#define _ECW_MAX_MIN(x) ((x) << 8)1129#define _TXOP_LIMIT(x) ((x) << 16)1130 1131#define _BCNIFS(x) ((x) & 0xFF)1132#define _BCNECW(x) ((((x) & 0xF)) << 8)1133 1134#define _LRL(x) ((x) & 0x3F)1135#define _SRL(x) (((x) & 0x3F) << 8)1136 1137#define _SIFS_CCK_CTX(x) ((x) & 0xFF)1138#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8)1139 1140#define _SIFS_OFDM_CTX(x) ((x) & 0xFF)1141#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8)1142 1143#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8)1144 1145#define DIS_EDCA_CNT_DWN BIT(11)1146 1147#define EN_MBSSID BIT(1)1148#define EN_TXBCN_RPT BIT(2)1149#define EN_BCN_FUNCTION BIT(3)1150 1151#define TSFTR_RST BIT(0)1152#define TSFTR1_RST BIT(1)1153 1154#define STOP_BCNQ BIT(6)1155 1156#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4)1157#define DIS_TSF_UDT0_TEST_CHIP BIT(5)1158 1159#define ACMHW_HWEN BIT(0)1160#define ACMHW_BEQEN BIT(1)1161#define ACMHW_VIQEN BIT(2)1162#define ACMHW_VOQEN BIT(3)1163#define ACMHW_BEQSTATUS BIT(4)1164#define ACMHW_VIQSTATUS BIT(5)1165#define ACMHW_VOQSTATUS BIT(6)1166 1167#define APSDOFF BIT(6)1168#define APSDOFF_STATUS BIT(7)1169 1170#define BW_20MHZ BIT(2)1171 1172#define RATE_BITMAP_ALL 0xFFFFF1173 1174#define RATE_RRSR_CCK_ONLY_1M 0xFFFF11175 1176#define TSFRST BIT(0)1177#define DIS_GCLK BIT(1)1178#define PAD_SEL BIT(2)1179#define PWR_ST BIT(6)1180#define PWRBIT_OW_EN BIT(7)1181#define ACRC BIT(8)1182#define CFENDFORM BIT(9)1183#define ICV BIT(10)1184 1185#define AAP BIT(0)1186#define APM BIT(1)1187#define AM BIT(2)1188#define AB BIT(3)1189#define ADD3 BIT(4)1190#define APWRMGT BIT(5)1191#define CBSSID BIT(6)1192#define CBSSID_DATA BIT(6)1193#define CBSSID_BCN BIT(7)1194#define ACRC32 BIT(8)1195#define AICV BIT(9)1196#define ADF BIT(11)1197#define ACF BIT(12)1198#define AMF BIT(13)1199#define HTC_LOC_CTRL BIT(14)1200#define UC_DATA_EN BIT(16)1201#define BM_DATA_EN BIT(17)1202#define MFBEN BIT(22)1203#define LSIGEN BIT(23)1204#define ENMBID BIT(24)1205#define APP_BASSN BIT(27)1206#define APP_PHYSTS BIT(28)1207#define APP_ICV BIT(29)1208#define APP_MIC BIT(30)1209#define APP_FCS BIT(31)1210 1211#define _MIN_SPACE(x) ((x) & 0x7)1212#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3)1213 1214#define RXERR_TYPE_OFDM_PPDU 01215#define RXERR_TYPE_OFDM_FALSE_ALARM 11216#define RXERR_TYPE_OFDM_MPDU_OK 21217#define RXERR_TYPE_OFDM_MPDU_FAIL 31218#define RXERR_TYPE_CCK_PPDU 41219#define RXERR_TYPE_CCK_FALSE_ALARM 51220#define RXERR_TYPE_CCK_MPDU_OK 61221#define RXERR_TYPE_CCK_MPDU_FAIL 71222#define RXERR_TYPE_HT_PPDU 81223#define RXERR_TYPE_HT_FALSE_ALARM 91224#define RXERR_TYPE_HT_MPDU_TOTAL 101225#define RXERR_TYPE_HT_MPDU_OK 111226#define RXERR_TYPE_HT_MPDU_FAIL 121227#define RXERR_TYPE_RX_FULL_DROP 151228 1229#define RXERR_COUNTER_MASK 0xFFFFF1230#define RXERR_RPT_RST BIT(27)1231#define _RXERR_RPT_SEL(type) ((type) << 28)1232 1233#define SCR_TXUSEDK BIT(0)1234#define SCR_RXUSEDK BIT(1)1235#define SCR_TXENCENABLE BIT(2)1236#define SCR_RXDECENABLE BIT(3)1237#define SCR_SKBYA2 BIT(4)1238#define SCR_NOSKMC BIT(5)1239#define SCR_TXBCUSEDK BIT(6)1240#define SCR_RXBCUSEDK BIT(7)1241 1242#define XCLK_VLD BIT(0)1243#define ACLK_VLD BIT(1)1244#define UCLK_VLD BIT(2)1245#define PCLK_VLD BIT(3)1246#define PCIRSTB BIT(4)1247#define V15_VLD BIT(5)1248#define TRP_B15V_EN BIT(7)1249#define SIC_IDLE BIT(8)1250#define BD_MAC2 BIT(9)1251#define BD_MAC1 BIT(10)1252#define IC_MACPHY_MODE BIT(11)1253#define BT_FUNC BIT(16)1254#define VENDOR_ID BIT(19)1255#define PAD_HWPD_IDN BIT(22)1256#define TRP_VAUX_EN BIT(23)1257#define TRP_BT_EN BIT(24)1258#define BD_PKG_SEL BIT(25)1259#define BD_HCI_SEL BIT(26)1260#define TYPE_ID BIT(27)1261 1262#define USB_IS_HIGH_SPEED 01263#define USB_IS_FULL_SPEED 11264#define USB_SPEED_MASK BIT(5)1265 1266#define USB_NORMAL_SIE_EP_MASK 0xF1267#define USB_NORMAL_SIE_EP_SHIFT 41268 1269#define USB_TEST_EP_MASK 0x301270#define USB_TEST_EP_SHIFT 41271 1272#define USB_AGG_EN BIT(3)1273 1274#define MAC_ADDR_LEN 61275#define LAST_ENTRY_OF_TX_PKT_BUFFER 2551276 1277#define POLLING_LLT_THRESHOLD 201278#define POLLING_READY_TIMEOUT_COUNT 30001279 1280#define MAX_MSS_DENSITY_2T 0x131281#define MAX_MSS_DENSITY_1T 0x0A1282 1283#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))1284#define EPROM_CMD_CONFIG 0x31285#define EPROM_CMD_LOAD 11286 1287#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE1288 1289#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2)1290 1291#define RA_LSSIWRITE_8821A 0xc901292#define RB_LSSIWRITE_8821A 0xe901293 1294#define RA_PIREAD_8821A 0xd041295#define RB_PIREAD_8821A 0xd441296#define RA_SIREAD_8821A 0xd081297#define RB_SIREAD_8821A 0xd481298 1299#define RPMAC_RESET 0x1001300#define RPMAC_TXSTART 0x1041301#define RPMAC_TXLEGACYSIG 0x1081302#define RPMAC_TXHTSIG1 0x10c1303#define RPMAC_TXHTSIG2 0x1101304#define RPMAC_PHYDEBUG 0x1141305#define RPMAC_TXPACKETNUM 0x1181306#define RPMAC_TXIDLE 0x11c1307#define RPMAC_TXMACHEADER0 0x1201308#define RPMAC_TXMACHEADER1 0x1241309#define RPMAC_TXMACHEADER2 0x1281310#define RPMAC_TXMACHEADER3 0x12c1311#define RPMAC_TXMACHEADER4 0x1301312#define RPMAC_TXMACHEADER5 0x1341313#define RPMAC_TXDADATYPE 0x1381314#define RPMAC_TXRANDOMSEED 0x13c1315#define RPMAC_CCKPLCPPREAMBLE 0x1401316#define RPMAC_CCKPLCPHEADER 0x1441317#define RPMAC_CCKCRC16 0x1481318#define RPMAC_OFDMRXCRC32OK 0x1701319#define RPMAC_OFDMRXCRC32ER 0x1741320#define RPMAC_OFDMRXPARITYER 0x1781321#define RPMAC_OFDMRXCRC8ER 0x17c1322#define RPMAC_CCKCRXRC16ER 0x1801323#define RPMAC_CCKCRXRC32ER 0x1841324#define RPMAC_CCKCRXRC32OK 0x1881325#define RPMAC_TXSTATUS 0x18c1326 1327#define RFPGA0_RFMOD 0x8001328 1329#define RFPGA0_TXINFO 0x8041330#define RFPGA0_PSDFUNCTION 0x8081331 1332#define RFPGA0_TXGAINSTAGE 0x80c1333 1334#define RFPGA0_RFTIMING1 0x8101335#define RFPGA0_RFTIMING2 0x8141336 1337#define RFPGA0_XA_HSSIPARAMETER1 0x8201338#define RFPGA0_XA_HSSIPARAMETER2 0x8241339#define RFPGA0_XB_HSSIPARAMETER1 0x8281340#define RFPGA0_XB_HSSIPARAMETER2 0x82c1341#define RCCAONSEC 0x8381342 1343#define RFPGA0_XA_LSSIPARAMETER 0x8401344#define RFPGA0_XB_LSSIPARAMETER 0x8441345#define RL1PEAKTH 0x8481346 1347#define RFPGA0_RFWAKEUPPARAMETER 0x8501348#define RFPGA0_RFSLEEPUPPARAMETER 0x8541349 1350#define RFPGA0_XAB_SWITCHCONTROL 0x8581351#define RFPGA0_XCD_SWITCHCONTROL 0x85c1352 1353#define RFPGA0_XA_RFINTERFACEOE 0x8601354#define RFC_AREA 0x8601355#define RFPGA0_XB_RFINTERFACEOE 0x8641356 1357#define RFPGA0_XAB_RFINTERFACESW 0x8701358#define RFPGA0_XCD_RFINTERFACESW 0x8741359 1360#define RFPGA0_XAB_RFPARAMETER 0x8781361#define RFPGA0_XCD_RFPARAMETER 0x87c1362 1363#define RFPGA0_ANALOGPARAMETER1 0x8801364#define RFPGA0_ANALOGPARAMETER2 0x8841365#define RFPGA0_ANALOGPARAMETER3 0x8881366#define RFPGA0_ANALOGPARAMETER4 0x88c1367 1368#define RFPGA0_XA_LSSIREADBACK 0x8a01369#define RFPGA0_XB_LSSIREADBACK 0x8a41370#define RFPGA0_XC_LSSIREADBACK 0x8a81371#define RRFMOD 0x8ac1372#define RHSSIREAD_8821AE 0x8b01373 1374#define RFPGA0_PSDREPORT 0x8b41375#define TRANSCEIVEA_HSPI_READBACK 0x8b81376#define TRANSCEIVEB_HSPI_READBACK 0x8bc1377#define RADC_BUF_CLK 0x8c41378#define RFPGA0_XAB_RFINTERFACERB 0x8e01379#define RFPGA0_XCD_RFINTERFACERB 0x8e41380 1381#define RFPGA1_RFMOD 0x9001382 1383#define RFPGA1_TXBLOCK 0x9041384#define RFPGA1_DEBUGSELECT 0x9081385#define RFPGA1_TXINFO 0x90c1386 1387#define RCCK_SYSTEM 0xa001388#define BCCK_SYSTEM 0x101389 1390#define RCCK0_AFESETTING 0xa041391#define RCCK0_CCA 0xa081392 1393#define RCCK0_RXAGC1 0xa0c1394#define RCCK0_RXAGC2 0xa101395 1396#define RCCK0_RXHP 0xa141397 1398#define RCCK0_DSPPARAMETER1 0xa181399#define RCCK0_DSPPARAMETER2 0xa1c1400 1401#define RCCK0_TXFILTER1 0xa201402#define RCCK0_TXFILTER2 0xa241403#define RCCK0_DEBUGPORT 0xa281404#define RCCK0_FALSEALARMREPORT 0xa2c1405#define RCCK0_TRSSIREPORT 0xa501406#define RCCK0_RXREPORT 0xa541407#define RCCK0_FACOUNTERLOWER 0xa5c1408#define RCCK0_FACOUNTERUPPER 0xa581409#define RCCK0_CCA_CNT 0xa601410 1411/* PageB(0XB00) */1412#define RPDP_ANTA 0xb001413#define RPDP_ANTA_4 0xb041414#define RPDP_ANTA_8 0xb081415#define RPDP_ANTA_C 0xb0c1416#define RPDP_ANTA_10 0xb101417#define RPDP_ANTA_14 0xb141418#define RPDP_ANTA_18 0xb181419#define RPDP_ANTA_1C 0xb1c1420#define RPDP_ANTA_20 0xb201421#define RPDP_ANTA_24 0xb241422 1423#define RCONFIG_PMPD_ANTA 0xb281424#define RCONFIG_RAM64x16 0xb2c1425 1426#define RBNDA 0xb301427#define RHSSIPAR 0xb341428 1429#define RCONFIG_ANTA 0xb681430#define RCONFIG_ANTB 0xb6c1431 1432#define RPDP_ANTB 0xb701433#define RPDP_ANTB_4 0xb741434#define RPDP_ANTB_8 0xb781435#define RPDP_ANTB_C 0xb7c1436#define RPDP_ANTB_10 0xb801437#define RPDP_ANTB_14 0xb841438#define RPDP_ANTB_18 0xb881439#define RPDP_ANTB_1C 0xb8c1440#define RPDP_ANTB_20 0xb901441#define RPDP_ANTB_24 0xb941442 1443#define RCONFIG_PMPD_ANTB 0xb981444 1445#define RBNDB 0xba01446 1447#define RAPK 0xbd81448#define RPM_RX0_ANTA 0xbdc1449#define RPM_RX1_ANTA 0xbe01450#define RPM_RX2_ANTA 0xbe41451#define RPM_RX3_ANTA 0xbe81452#define RPM_RX0_ANTB 0xbec1453#define RPM_RX1_ANTB 0xbf01454#define RPM_RX2_ANTB 0xbf41455#define RPM_RX3_ANTB 0xbf81456 1457/*RSSI Dump*/1458#define RA_RSSI_DUMP 0XBF01459#define RB_RSSI_DUMP 0XBF11460#define RS1_RX_EVM_DUMP 0XBF41461#define RS2_RX_EVM_DUMP 0XBF51462#define RA_RX_SNR_DUMP 0XBF61463#define RB_RX_SNR_DUMP 0XBF71464#define RA_CFO_SHORT_DUMP 0XBF81465#define RB_CFO_SHORT_DUMP 0XBFA1466#define RA_CFO_LONG_DUMP 0XBEC1467#define RB_CFO_LONG_DUMP 0XBEE1468 1469/*Page C*/1470#define ROFDM0_LSTF 0xc001471 1472#define ROFDM0_TRXPATHENABLE 0xc041473#define ROFDM0_TRMUXPAR 0xc081474#define ROFDM0_TRSWISOLATION 0xc0c1475 1476#define ROFDM0_XARXAFE 0xc101477#define ROFDM0_XARXIQIMBALANCE 0xc141478#define ROFDM0_XBRXAFE 0xc181479#define ROFDM0_XBRXIQIMBALANCE 0xc1c1480#define ROFDM0_XCRXAFE 0xc201481#define ROFDM0_XCRXIQIMBANLANCE 0xc241482#define ROFDM0_XDRXAFE 0xc281483#define ROFDM0_XDRXIQIMBALANCE 0xc2c1484 1485#define ROFDM0_RXDETECTOR1 0xc301486#define ROFDM0_RXDETECTOR2 0xc341487#define ROFDM0_RXDETECTOR3 0xc381488#define ROFDM0_RXDETECTOR4 0xc3c1489 1490#define ROFDM0_RXDSP 0xc401491#define ROFDM0_CFOANDDAGC 0xc441492#define ROFDM0_CCADROPTHRESHOLD 0xc481493#define ROFDM0_ECCATHRESHOLD 0xc4c1494 1495#define ROFDM0_XAAGCCORE1 0xc501496#define ROFDM0_XAAGCCORE2 0xc541497#define ROFDM0_XBAGCCORE1 0xc581498#define ROFDM0_XBAGCCORE2 0xc5c1499#define ROFDM0_XCAGCCORE1 0xc601500#define ROFDM0_XCAGCCORE2 0xc641501#define ROFDM0_XDAGCCORE1 0xc681502#define ROFDM0_XDAGCCORE2 0xc6c1503 1504#define ROFDM0_AGCPARAMETER1 0xc701505#define ROFDM0_AGCPARAMETER2 0xc741506#define ROFDM0_AGCRSSITABLE 0xc781507#define ROFDM0_HTSTFAGC 0xc7c1508 1509#define ROFDM0_XATXIQIMBALANCE 0xc801510#define ROFDM0_XATXAFE 0xc841511#define ROFDM0_XBTXIQIMBALANCE 0xc881512#define ROFDM0_XBTXAFE 0xc8c1513#define ROFDM0_XCTXIQIMBALANCE 0xc901514#define ROFDM0_XCTXAFE 0xc941515#define ROFDM0_XDTXIQIMBALANCE 0xc981516#define ROFDM0_XDTXAFE 0xc9c1517 1518#define ROFDM0_RXIQEXTANTA 0xca01519#define ROFDM0_TXCOEFF1 0xca41520#define ROFDM0_TXCOEFF2 0xca81521#define ROFDM0_TXCOEFF3 0xcac1522#define ROFDM0_TXCOEFF4 0xcb01523#define ROFDM0_TXCOEFF5 0xcb41524#define ROFDM0_TXCOEFF6 0xcb81525 1526/*Path_A RFE cotrol */1527#define RA_RFE_CTRL_8812 0xcb81528/*Path_B RFE control*/1529#define RB_RFE_CTRL_8812 0xeb81530 1531#define ROFDM0_RXHPPARAMETER 0xce01532#define ROFDM0_TXPSEUDONOISEWGT 0xce41533#define ROFDM0_FRAMESYNC 0xcf01534#define ROFDM0_DFSREPORT 0xcf41535 1536#define ROFDM1_LSTF 0xd001537#define ROFDM1_TRXPATHENABLE 0xd041538 1539#define ROFDM1_CF0 0xd081540#define ROFDM1_CSI1 0xd101541#define ROFDM1_SBD 0xd141542#define ROFDM1_CSI2 0xd181543#define ROFDM1_CFOTRACKING 0xd2c1544#define ROFDM1_TRXMESAURE1 0xd341545#define ROFDM1_INTFDET 0xd3c1546#define ROFDM1_PSEUDONOISESTATEAB 0xd501547#define ROFDM1_PSEUDONOISESTATECD 0xd541548#define ROFDM1_RXPSEUDONOISEWGT 0xd581549 1550#define ROFDM_PHYCOUNTER1 0xda01551#define ROFDM_PHYCOUNTER2 0xda41552#define ROFDM_PHYCOUNTER3 0xda81553 1554#define ROFDM_SHORTCFOAB 0xdac1555#define ROFDM_SHORTCFOCD 0xdb01556#define ROFDM_LONGCFOAB 0xdb41557#define ROFDM_LONGCFOCD 0xdb81558#define ROFDM_TAILCF0AB 0xdbc1559#define ROFDM_TAILCF0CD 0xdc01560#define ROFDM_PWMEASURE1 0xdc41561#define ROFDM_PWMEASURE2 0xdc81562#define ROFDM_BWREPORT 0xdcc1563#define ROFDM_AGCREPORT 0xdd01564#define ROFDM_RXSNR 0xdd41565#define ROFDM_RXEVMCSI 0xdd81566#define ROFDM_SIGREPORT 0xddc1567 1568#define RTXAGC_A_CCK11_CCK1 0xc201569#define RTXAGC_A_OFDM18_OFDM6 0xc241570#define RTXAGC_A_OFDM54_OFDM24 0xc281571#define RTXAGC_A_MCS03_MCS00 0xc2c1572#define RTXAGC_A_MCS07_MCS04 0xc301573#define RTXAGC_A_MCS11_MCS08 0xc341574#define RTXAGC_A_MCS15_MCS12 0xc381575#define RTXAGC_A_NSS1INDEX3_NSS1INDEX0 0xc3c1576#define RTXAGC_A_NSS1INDEX7_NSS1INDEX4 0xc401577#define RTXAGC_A_NSS2INDEX1_NSS1INDEX8 0xc441578#define RTXAGC_A_NSS2INDEX5_NSS2INDEX2 0xc481579#define RTXAGC_A_NSS2INDEX9_NSS2INDEX6 0xc4c1580#define RTXAGC_B_CCK11_CCK1 0xe201581#define RTXAGC_B_OFDM18_OFDM6 0xe241582#define RTXAGC_B_OFDM54_OFDM24 0xe281583#define RTXAGC_B_MCS03_MCS00 0xe2c1584#define RTXAGC_B_MCS07_MCS04 0xe301585#define RTXAGC_B_MCS11_MCS08 0xe341586#define RTXAGC_B_MCS15_MCS12 0xe381587#define RTXAGC_B_NSS1INDEX3_NSS1INDEX0 0xe3c1588#define RTXAGC_B_NSS1INDEX7_NSS1INDEX4 0xe401589#define RTXAGC_B_NSS2INDEX1_NSS1INDEX8 0xe441590#define RTXAGC_B_NSS2INDEX5_NSS2INDEX2 0xe481591#define RTXAGC_B_NSS2INDEX9_NSS2INDEX6 0xe4c1592 1593#define RA_TXPWRTRAING 0xc541594#define RB_TXPWRTRAING 0xe541595 1596#define RFPGA0_IQK 0xe281597#define RTX_IQK_TONE_A 0xe301598#define RRX_IQK_TONE_A 0xe341599#define RTX_IQK_PI_A 0xe381600#define RRX_IQK_PI_A 0xe3c1601 1602#define RTX_IQK 0xe401603#define RRX_IQK 0xe441604#define RIQK_AGC_PTS 0xe481605#define RIQK_AGC_RSP 0xe4c1606#define RTX_IQK_TONE_B 0xe501607#define RRX_IQK_TONE_B 0xe541608#define RTX_IQK_PI_B 0xe581609#define RRX_IQK_PI_B 0xe5c1610#define RIQK_AGC_CONT 0xe601611 1612#define RBLUE_TOOTH 0xe6c1613#define RRX_WAIT_CCA 0xe701614#define RTX_CCK_RFON 0xe741615#define RTX_CCK_BBON 0xe781616#define RTX_OFDM_RFON 0xe7c1617#define RTX_OFDM_BBON 0xe801618#define RTX_TO_RX 0xe841619#define RTX_TO_TX 0xe881620#define RRX_CCK 0xe8c1621 1622#define RTX_POWER_BEFORE_IQK_A 0xe941623#define RTX_POWER_AFTER_IQK_A 0xe9c1624 1625#define RRX_POWER_BEFORE_IQK_A 0xea01626#define RRX_POWER_BEFORE_IQK_A_2 0xea41627#define RRX_POWER_AFTER_IQK_A 0xea81628#define RRX_POWER_AFTER_IQK_A_2 0xeac1629 1630#define RTX_POWER_BEFORE_IQK_B 0xeb41631#define RTX_POWER_AFTER_IQK_B 0xebc1632 1633#define RRX_POER_BEFORE_IQK_B 0xec01634#define RRX_POER_BEFORE_IQK_B_2 0xec41635#define RRX_POWER_AFTER_IQK_B 0xec81636#define RRX_POWER_AFTER_IQK_B_2 0xecc1637 1638#define RRX_OFDM 0xed01639#define RRX_WAIT_RIFS 0xed41640#define RRX_TO_RX 0xed81641#define RSTANDBY 0xedc1642#define RSLEEP 0xee01643#define RPMPD_ANAEN 0xeec1644 1645#define RZEBRA1_HSSIENABLE 0x01646#define RZEBRA1_TRXENABLE1 0x11647#define RZEBRA1_TRXENABLE2 0x21648#define RZEBRA1_AGC 0x41649#define RZEBRA1_CHARGEPUMP 0x51650#define RZEBRA1_CHANNEL 0x71651 1652#define RZEBRA1_TXGAIN 0x81653#define RZEBRA1_TXLPF 0x91654#define RZEBRA1_RXLPF 0xb1655#define RZEBRA1_RXHPFCORNER 0xc1656 1657#define RGLOBALCTRL 01658#define RRTL8256_TXLPF 191659#define RRTL8256_RXLPF 111660#define RRTL8258_TXLPF 0x111661#define RRTL8258_RXLPF 0x131662#define RRTL8258_RSSILPF 0xa1663 1664#define RF_AC 0x001665 1666#define RF_IQADJ_G1 0x011667#define RF_IQADJ_G2 0x021668#define RF_POW_TRSW 0x051669 1670#define RF_GAIN_RX 0x061671#define RF_GAIN_TX 0x071672 1673#define RF_TXM_IDAC 0x081674#define RF_BS_IQGEN 0x0F1675 1676#define RF_MODE1 0x101677#define RF_MODE2 0x111678 1679#define RF_RX_AGC_HP 0x121680#define RF_TX_AGC 0x131681#define RF_BIAS 0x141682#define RF_IPA 0x151683#define RF_POW_ABILITY 0x171684#define RF_MODE_AG 0x181685#define RRFCHANNEL 0x181686#define RF_CHNLBW 0x181687#define RF_TOP 0x191688 1689#define RF_RX_G1 0x1A1690#define RF_RX_G2 0x1B1691 1692#define RF_RX_BB2 0x1C1693#define RF_RX_BB1 0x1D1694 1695#define RF_RCK1 0x1E1696#define RF_RCK2 0x1F1697 1698#define RF_TX_G1 0x201699#define RF_TX_G2 0x211700#define RF_TX_G3 0x221701 1702#define RF_TX_BB1 0x231703#define RF_T_METER 0x241704#define RF_T_METER_88E 0x421705#define RF_T_METER_8812A 0x421706 1707#define RF_SYN_G1 0x251708#define RF_SYN_G2 0x261709#define RF_SYN_G3 0x271710#define RF_SYN_G4 0x281711#define RF_SYN_G5 0x291712#define RF_SYN_G6 0x2A1713#define RF_SYN_G7 0x2B1714#define RF_SYN_G8 0x2C1715 1716#define RF_RCK_OS 0x301717#define RF_TXPA_G1 0x311718#define RF_TXPA_G2 0x321719#define RF_TXPA_G3 0x331720 1721#define RF_TX_BIAS_A 0x351722#define RF_TX_BIAS_D 0x361723#define RF_LOBF_9 0x381724#define RF_RXRF_A3 0x3C1725#define RF_TRSW 0x3F1726 1727#define RF_TXRF_A2 0x411728#define RF_TXPA_G4 0x461729#define RF_TXPA_A4 0x4B1730 1731#define RF_APK 0x631732 1733#define RF_WE_LUT 0xEF1734 1735#define BBBRESETB 0x1001736#define BGLOBALRESETB 0x2001737#define BOFDMTXSTART 0x41738#define BCCKTXSTART 0x81739#define BCRC32DEBUG 0x1001740#define BPMACLOOPBACK 0x101741#define BTXLSIG 0xffffff1742#define BOFDMTXRATE 0xf1743#define BOFDMTXRESERVED 0x101744#define BOFDMTXLENGTH 0x1ffe01745#define BOFDMTXPARITY 0x200001746#define BTXHTSIG1 0xffffff1747#define BTXHTMCSRATE 0x7f1748#define BTXHTBW 0x801749#define BTXHTLENGTH 0xffff001750#define BTXHTSIG2 0xffffff1751#define BTXHTSMOOTHING 0x11752#define BTXHTSOUNDING 0x21753#define BTXHTRESERVED 0x41754#define BTXHTAGGREATION 0x81755#define BTXHTSTBC 0x301756#define BTXHTADVANCECODING 0x401757#define BTXHTSHORTGI 0x801758#define BTXHTNUMBERHT_LTF 0x3001759#define BTXHTCRC8 0x3fc001760#define BCOUNTERRESET 0x100001761#define BNUMOFOFDMTX 0xffff1762#define BNUMOFCCKTX 0xffff00001763#define BTXIDLEINTERVAL 0xffff1764#define BOFDMSERVICE 0xffff00001765#define BTXMACHEADER 0xffffffff1766#define BTXDATAINIT 0xff1767#define BTXHTMODE 0x1001768#define BTXDATATYPE 0x300001769#define BTXRANDOMSEED 0xffffffff1770#define BCCKTXPREAMBLE 0x11771#define BCCKTXSFD 0xffff00001772#define BCCKTXSIG 0xff1773#define BCCKTXSERVICE 0xff001774#define BCCKLENGTHEXT 0x80001775#define BCCKTXLENGHT 0xffff00001776#define BCCKTXCRC16 0xffff1777#define BCCKTXSTATUS 0x11778#define BOFDMTXSTATUS 0x21779#define IS_BB_REG_OFFSET_92S(__offset) \1780 ((__offset >= 0x800) && (__offset <= 0xfff))1781 1782#define BRFMOD 0x11783#define BJAPANMODE 0x21784#define BCCKTXSC 0x301785/* Block & Path enable*/1786#define ROFDMCCKEN 0x8081787#define BCCKEN 0x100000001788#define BOFDMEN 0x200000001789/* Rx antenna*/1790#define RRXPATH 0x8081791#define BRXPATH 0xff1792/* Tx antenna*/1793#define RTXPATH 0x80c1794#define BTXPATH 0x0fffffff1795/* for cck rx path selection*/1796#define RCCK_RX 0xa041797#define BCCK_RX 0x0c0000001798/* Use LSIG for VHT length*/1799#define RVHTLEN_USE_LSIG 0x8c31800 1801#define BOFDMRXADCPHASE 0x100001802#define BOFDMTXDACPHASE 0x400001803#define BXATXAGC 0x3f1804 1805#define BXBTXAGC 0xf001806#define BXCTXAGC 0xf0001807#define BXDTXAGC 0xf00001808 1809#define BPASTART 0xf00000001810#define BTRSTART 0x00f000001811#define BRFSTART 0x0000f0001812#define BBBSTART 0x000000f01813#define BBBCCKSTART 0x0000000f1814#define BPAEND 0xf1815#define BTREND 0x0f0000001816#define BRFEND 0x000f00001817#define BCCAMASK 0x000000f01818#define BR2RCCAMASK 0x00000f001819#define BHSSI_R2TDELAY 0xf80000001820#define BHSSI_T2RDELAY 0xf800001821#define BCONTXHSSI 0x4001822#define BIGFROMCCK 0x2001823#define BAGCADDRESS 0x3f1824#define BRXHPTX 0x70001825#define BRXHP2RX 0x380001826#define BRXHPCCKINI 0xc00001827#define BAGCTXCODE 0xc000001828#define BAGCRXCODE 0x3000001829 1830#define B3WIREDATALENGTH 0x8001831#define B3WIREADDREAALENGTH 0x4001832 1833#define B3WIRERFPOWERDOWN 0x11834#define B5GPAPEPOLARITY 0x400000001835#define B2GPAPEPOLARITY 0x800000001836#define BRFSW_TXDEFAULTANT 0x31837#define BRFSW_TXOPTIONANT 0x301838#define BRFSW_RXDEFAULTANT 0x3001839#define BRFSW_RXOPTIONANT 0x30001840#define BRFSI_3WIREDATA 0x11841#define BRFSI_3WIRECLOCK 0x21842#define BRFSI_3WIRELOAD 0x41843#define BRFSI_3WIRERW 0x81844#define BRFSI_3WIRE 0xf1845 1846#define BRFSI_RFENV 0x101847 1848#define BRFSI_TRSW 0x201849#define BRFSI_TRSWB 0x401850#define BRFSI_ANTSW 0x1001851#define BRFSI_ANTSWB 0x2001852#define BRFSI_PAPE 0x4001853#define BRFSI_PAPE5G 0x8001854#define BBANDSELECT 0x11855#define BHTSIG2_GI 0x801856#define BHTSIG2_SMOOTHING 0x011857#define BHTSIG2_SOUNDING 0x021858#define BHTSIG2_AGGREATON 0x081859#define BHTSIG2_STBC 0x301860#define BHTSIG2_ADVCODING 0x401861#define BHTSIG2_NUMOFHTLTF 0x3001862#define BHTSIG2_CRC8 0x3fc1863#define BHTSIG1_MCS 0x7f1864#define BHTSIG1_BANDWIDTH 0x801865#define BHTSIG1_HTLENGTH 0xffff1866#define BLSIG_RATE 0xf1867#define BLSIG_RESERVED 0x101868#define BLSIG_LENGTH 0x1fffe1869#define BLSIG_PARITY 0x201870#define BCCKRXPHASE 0x41871 1872#define BLSSIREADADDRESS 0x7f8000001873#define BLSSIREADEDGE 0x800000001874 1875#define BLSSIREADBACKDATA 0xfffff1876 1877#define BLSSIREADOKFLAG 0x10001878#define BCCKSAMPLERATE 0x81879#define BREGULATOR0STANDBY 0x11880#define BREGULATORPLLSTANDBY 0x21881#define BREGULATOR1STANDBY 0x41882#define BPLLPOWERUP 0x81883#define BDPLLPOWERUP 0x101884#define BDA10POWERUP 0x201885#define BAD7POWERUP 0x2001886#define BDA6POWERUP 0x20001887#define BXTALPOWERUP 0x40001888#define B40MDCLKPOWERUP 0x80001889#define BDA6DEBUGMODE 0x200001890#define BDA6SWING 0x3800001891 1892#define BADCLKPHASE 0x40000001893#define B80MCLKDELAY 0x180000001894#define BAFEWATCHDOGENABLE 0x200000001895 1896#define BXTALCAP01 0xc00000001897#define BXTALCAP23 0x31898#define BXTALCAP92X 0x0f0000001899#define BXTALCAP 0x0f0000001900 1901#define BINTDIFCLKENABLE 0x4001902#define BEXTSIGCLKENABLE 0x8001903#define BBANDGAP_MBIAS_POWERUP 0x100001904#define BAD11SH_GAIN 0xc00001905#define BAD11NPUT_RANGE 0x7000001906#define BAD110P_CURRENT 0x38000001907#define BLPATH_LOOPBACK 0x40000001908#define BQPATH_LOOPBACK 0x80000001909#define BAFE_LOOPBACK 0x100000001910#define BDA10_SWING 0x7e01911#define BDA10_REVERSE 0x8001912#define BDA_CLK_SOURCE 0x10001913#define BDA7INPUT_RANGE 0x60001914#define BDA7_GAIN 0x380001915#define BDA7OUTPUT_CM_MODE 0x400001916#define BDA7INPUT_CM_MODE 0x3800001917#define BDA7CURRENT 0xc000001918#define BREGULATOR_ADJUST 0x70000001919#define BAD11POWERUP_ATTX 0x11920#define BDA10PS_ATTX 0x101921#define BAD11POWERUP_ATRX 0x1001922#define BDA10PS_ATRX 0x10001923#define BCCKRX_AGC_FORMAT 0x2001924#define BPSDFFT_SAMPLE_POINT 0xc0001925#define BPSD_AVERAGE_NUM 0x30001926#define BIQPATH_CONTROL 0xc001927#define BPSD_FREQ 0x3ff1928#define BPSD_ANTENNA_PATH 0x301929#define BPSD_IQ_SWITCH 0x401930#define BPSD_RX_TRIGGER 0x4000001931#define BPSD_TX_TRIGGER 0x800000001932#define BPSD_SINE_TONE_SCALE 0x7f0000001933#define BPSD_REPORT 0xffff1934 1935#define BOFDM_TXSC 0x300000001936#define BCCK_TXON 0x11937#define BOFDM_TXON 0x21938#define BDEBUG_PAGE 0xfff1939#define BDEBUG_ITEM 0xff1940#define BANTL 0x101941#define BANT_NONHT 0x1001942#define BANT_HT1 0x10001943#define BANT_HT2 0x100001944#define BANT_HT1S1 0x1000001945#define BANT_NONHTS1 0x10000001946 1947#define BCCK_BBMODE 0x31948#define BCCK_TXPOWERSAVING 0x801949#define BCCK_RXPOWERSAVING 0x401950 1951#define BCCK_SIDEBAND 0x101952 1953#define BCCK_SCRAMBLE 0x81954#define BCCK_ANTDIVERSITY 0x80001955#define BCCK_CARRIER_RECOVERY 0x40001956#define BCCK_TXRATE 0x30001957#define BCCK_DCCANCEL 0x08001958#define BCCK_ISICANCEL 0x04001959#define BCCK_MATCH_FILTER 0x02001960#define BCCK_EQUALIZER 0x01001961#define BCCK_PREAMBLE_DETECT 0x8000001962#define BCCK_FAST_FALSECCA 0x4000001963#define BCCK_CH_ESTSTART 0x3000001964#define BCCK_CCA_COUNT 0x0800001965#define BCCK_CS_LIM 0x0700001966#define BCCK_BIST_MODE 0x800000001967#define BCCK_CCAMASK 0x400000001968#define BCCK_TX_DAC_PHASE 0x41969#define BCCK_RX_ADC_PHASE 0x200000001970#define BCCKR_CP_MODE 0x01001971#define BCCK_TXDC_OFFSET 0xf01972#define BCCK_RXDC_OFFSET 0xf1973#define BCCK_CCA_MODE 0xc0001974#define BCCK_FALSECS_LIM 0x3f001975#define BCCK_CS_RATIO 0xc000001976#define BCCK_CORGBIT_SEL 0x3000001977#define BCCK_PD_LIM 0x0f00001978#define BCCK_NEWCCA 0x800000001979#define BCCK_RXHP_OF_IG 0x80001980#define BCCK_RXIG 0x7f001981#define BCCK_LNA_POLARITY 0x8000001982#define BCCK_RX1ST_BAIN 0x7f00001983#define BCCK_RF_EXTEND 0x200000001984#define BCCK_RXAGC_SATLEVEL 0x1f0000001985#define BCCK_RXAGC_SATCOUNT 0xe01986#define BCCKRXRFSETTLE 0x1f1987#define BCCK_FIXED_RXAGC 0x80001988#define BCCK_ANTENNA_POLARITY 0x20001989#define BCCK_TXFILTER_TYPE 0x0c001990#define BCCK_RXAGC_REPORTTYPE 0x03001991#define BCCK_RXDAGC_EN 0x800000001992#define BCCK_RXDAGC_PERIOD 0x200000001993#define BCCK_RXDAGC_SATLEVEL 0x1f0000001994#define BCCK_TIMING_RECOVERY 0x8000001995#define BCCK_TXC0 0x3f00001996#define BCCK_TXC1 0x3f0000001997#define BCCK_TXC2 0x3f1998#define BCCK_TXC3 0x3f001999#define BCCK_TXC4 0x3f00002000#define BCCK_TXC5 0x3f0000002001#define BCCK_TXC6 0x3f2002#define BCCK_TXC7 0x3f002003#define BCCK_DEBUGPORT 0xff00002004#define BCCK_DAC_DEBUG 0x0f0000002005#define BCCK_FALSEALARM_ENABLE 0x80002006#define BCCK_FALSEALARM_READ 0x40002007#define BCCK_TRSSI 0x7f2008#define BCCK_RXAGC_REPORT 0xfe2009#define BCCK_RXREPORT_ANTSEL 0x800000002010#define BCCK_RXREPORT_MFOFF 0x400000002011#define BCCK_RXREPORT_SQLOSS 0x200000002012#define BCCK_RXREPORT_PKTLOSS 0x100000002013#define BCCK_RXREPORT_LOCKEDBIT 0x080000002014#define BCCK_RXREPORT_RATEERROR 0x040000002015#define BCCK_RXREPORT_RXRATE 0x030000002016#define BCCK_RXFA_COUNTER_LOWER 0xff2017#define BCCK_RXFA_COUNTER_UPPER 0xff0000002018#define BCCK_RXHPAGC_START 0xe0002019#define BCCK_RXHPAGC_FINAL 0x1c002020#define BCCK_RXFALSEALARM_ENABLE 0x80002021#define BCCK_FACOUNTER_FREEZE 0x40002022#define BCCK_TXPATH_SEL 0x100000002023#define BCCK_DEFAULT_RXPATH 0xc0000002024#define BCCK_OPTION_RXPATH 0x30000002025 2026#define BNUM_OFSTF 0x32027#define BSHIFT_L 0xc02028#define BGI_TH 0xc2029#define BRXPATH_A 0x12030#define BRXPATH_B 0x22031#define BRXPATH_C 0x42032#define BRXPATH_D 0x82033#define BTXPATH_A 0x12034#define BTXPATH_B 0x22035#define BTXPATH_C 0x42036#define BTXPATH_D 0x82037#define BTRSSI_FREQ 0x2002038#define BADC_BACKOFF 0x30002039#define BDFIR_BACKOFF 0xc0002040#define BTRSSI_LATCH_PHASE 0x100002041#define BRX_LDC_OFFSET 0xff2042#define BRX_QDC_OFFSET 0xff002043#define BRX_DFIR_MODE 0x18000002044#define BRX_DCNF_TYPE 0xe0000002045#define BRXIQIMB_A 0x3ff2046#define BRXIQIMB_B 0xfc002047#define BRXIQIMB_C 0x3f00002048#define BRXIQIMB_D 0xffc000002049#define BDC_DC_NOTCH 0x600002050#define BRXNB_NOTCH 0x1f0000002051#define BPD_TH 0xf2052#define BPD_TH_OPT2 0xc0002053#define BPWED_TH 0x7002054#define BIFMF_WIN_L 0x8002055#define BPD_OPTION 0x10002056#define BMF_WIN_L 0xe0002057#define BBW_SEARCH_L 0x300002058#define BWIN_ENH_L 0xc00002059#define BBW_TH 0x7000002060#define BED_TH2 0x38000002061#define BBW_OPTION 0x40000002062#define BRADIO_TH 0x180000002063#define BWINDOW_L 0xe00000002064#define BSBD_OPTION 0x12065#define BFRAME_TH 0x1c2066#define BFS_OPTION 0x602067#define BDC_SLOPE_CHECK 0x802068#define BFGUARD_COUNTER_DC_L 0xe002069#define BFRAME_WEIGHT_SHORT 0x70002070#define BSUB_TUNE 0xe000002071#define BFRAME_DC_LENGTH 0xe0000002072#define BSBD_START_OFFSET 0x300000002073#define BFRAME_TH_2 0x72074#define BFRAME_GI2_TH 0x382075#define BGI2_SYNC_EN 0x402076#define BSARCH_SHORT_EARLY 0x3002077#define BSARCH_SHORT_LATE 0xc002078#define BSARCH_GI2_LATE 0x700002079#define BCFOANTSUM 0x12080#define BCFOACC 0x22081#define BCFOSTARTOFFSET 0xc2082#define BCFOLOOPBACK 0x702083#define BCFOSUMWEIGHT 0x802084#define BDAGCENABLE 0x100002085#define BTXIQIMB_A 0x3ff2086#define BTXIQIMB_b 0xfc002087#define BTXIQIMB_C 0x3f00002088#define BTXIQIMB_D 0xffc000002089#define BTXIDCOFFSET 0xff2090#define BTXIQDCOFFSET 0xff002091#define BTXDFIRMODE 0x100002092#define BTXPESUDO_NOISEON 0x40000002093#define BTXPESUDO_NOISE_A 0xff2094#define BTXPESUDO_NOISE_B 0xff002095#define BTXPESUDO_NOISE_C 0xff00002096#define BTXPESUDO_NOISE_D 0xff0000002097#define BCCA_DROPOPTION 0x200002098#define BCCA_DROPTHRES 0xfff000002099#define BEDCCA_H 0xf2100#define BEDCCA_L 0xf02101#define BLAMBDA_ED 0x3002102#define BRX_INITIALGAIN 0x7f2103#define BRX_ANTDIV_EN 0x802104#define BRX_AGC_ADDRESS_FOR_LNA 0x7f002105#define BRX_HIGHPOWER_FLOW 0x80002106#define BRX_AGC_FREEZE_THRES 0xc00002107#define BRX_FREEZESTEP_AGC1 0x3000002108#define BRX_FREEZESTEP_AGC2 0xc000002109#define BRX_FREEZESTEP_AGC3 0x30000002110#define BRX_FREEZESTEP_AGC0 0xc0000002111#define BRXRSSI_CMP_EN 0x100000002112#define BRXQUICK_AGCEN 0x200000002113#define BRXAGC_FREEZE_THRES_MODE 0x400000002114#define BRX_OVERFLOW_CHECKTYPE 0x800000002115#define BRX_AGCSHIFT 0x7f2116#define BTRSW_TRI_ONLY 0x802117#define BPOWER_THRES 0x3002118#define BRXAGC_EN 0x12119#define BRXAGC_TOGETHER_EN 0x22120#define BRXAGC_MIN 0x42121#define BRXHP_INI 0x72122#define BRXHP_TRLNA 0x702123#define BRXHP_RSSI 0x7002124#define BRXHP_BBP1 0x70002125#define BRXHP_BBP2 0x700002126#define BRXHP_BBP3 0x7000002127#define BRSSI_H 0x7f00002128#define BRSSI_GEN 0x7f0000002129#define BRXSETTLE_TRSW 0x72130#define BRXSETTLE_LNA 0x382131#define BRXSETTLE_RSSI 0x1c02132#define BRXSETTLE_BBP 0xe002133#define BRXSETTLE_RXHP 0x70002134#define BRXSETTLE_ANTSW_RSSI 0x380002135#define BRXSETTLE_ANTSW 0xc00002136#define BRXPROCESS_TIME_DAGC 0x3000002137#define BRXSETTLE_HSSI 0x4000002138#define BRXPROCESS_TIME_BBPPW 0x8000002139#define BRXANTENNA_POWER_SHIFT 0x30000002140#define BRSSI_TABLE_SELECT 0xc0000002141#define BRXHP_FINAL 0x70000002142#define BRXHPSETTLE_BBP 0x72143#define BRXHTSETTLE_HSSI 0x82144#define BRXHTSETTLE_RXHP 0x702145#define BRXHTSETTLE_BBPPW 0x802146#define BRXHTSETTLE_IDLE 0x3002147#define BRXHTSETTLE_RESERVED 0x1c002148#define BRXHT_RXHP_EN 0x80002149#define BRXAGC_FREEZE_THRES 0x300002150#define BRXAGC_TOGETHEREN 0x400002151#define BRXHTAGC_MIN 0x800002152#define BRXHTAGC_EN 0x1000002153#define BRXHTDAGC_EN 0x2000002154#define BRXHT_RXHP_BBP 0x1c000002155#define BRXHT_RXHP_FINAL 0xe00000002156#define BRXPW_RADIO_TH 0x32157#define BRXPW_RADIO_EN 0x42158#define BRXMF_HOLD 0x38002159#define BRXPD_DELAY_TH1 0x382160#define BRXPD_DELAY_TH2 0x1c02161#define BRXPD_DC_COUNT_MAX 0x6002162#define BRXPD_DELAY_TH 0x80002163#define BRXPROCESS_DELAY 0xf00002164#define BRXSEARCHRANGE_GI2_EARLY 0x7000002165#define BRXFRAME_FUARD_COUNTER_L 0x38000002166#define BRXSGI_GUARD_L 0xc0000002167#define BRXSGI_SEARCH_L 0x300000002168#define BRXSGI_TH 0xc00000002169#define BDFSCNT0 0xff2170#define BDFSCNT1 0xff002171#define BDFSFLAG 0xf00002172#define BMF_WEIGHT_SUM 0x3000002173#define BMINIDX_TH 0x7f0000002174#define BDAFORMAT 0x400002175#define BTXCH_EMU_ENABLE 0x010000002176#define BTRSW_ISOLATION_A 0x7f2177#define BTRSW_ISOLATION_B 0x7f002178#define BTRSW_ISOLATION_C 0x7f00002179#define BTRSW_ISOLATION_D 0x7f0000002180#define BEXT_LNA_GAIN 0x7c002181 2182#define BSTBC_EN 0x42183#define BANTENNA_MAPPING 0x102184#define BNSS 0x202185#define BCFO_ANTSUM_ID 0x2002186#define BPHY_COUNTER_RESET 0x80000002187#define BCFO_REPORT_GET 0x40000002188#define BOFDM_CONTINUE_TX 0x100000002189#define BOFDM_SINGLE_CARRIER 0x200000002190#define BOFDM_SINGLE_TONE 0x400000002191#define BHT_DETECT 0x1002192#define BCFOEN 0x100002193#define BCFOVALUE 0xfff000002194#define BSIGTONE_RE 0x3f2195#define BSIGTONE_IM 0x7f002196#define BCOUNTER_CCA 0xffff2197#define BCOUNTER_PARITYFAIL 0xffff00002198#define BCOUNTER_RATEILLEGAL 0xffff2199#define BCOUNTER_CRC8FAIL 0xffff00002200#define BCOUNTER_MCSNOSUPPORT 0xffff2201#define BCOUNTER_FASTSYNC 0xffff2202#define BSHORTCFO 0xfff2203#define BSHORTCFOT_LENGTH 122204#define BSHORTCFOF_LENGTH 112205#define BLONGCFO 0x7ff2206#define BLONGCFOT_LENGTH 112207#define BLONGCFOF_LENGTH 112208#define BTAILCFO 0x1fff2209#define BTAILCFOT_LENGTH 132210#define BTAILCFOF_LENGTH 122211#define BNOISE_EN_PWDB 0xffff2212#define BCC_POWER_DB 0xffff00002213#define BMOISE_PWDB 0xffff2214#define BPOWERMEAST_LENGTH 102215#define BPOWERMEASF_LENGTH 32216#define BRX_HT_BW 0x12217#define BRXSC 0x62218#define BRX_HT 0x82219#define BNB_INTF_DET_ON 0x12220#define BINTF_WIN_LEN_CFG 0x302221#define BNB_INTF_TH_CFG 0x1c02222#define BRFGAIN 0x3f2223#define BTABLESEL 0x402224#define BTRSW 0x802225#define BRXSNR_A 0xff2226#define BRXSNR_B 0xff002227#define BRXSNR_C 0xff00002228#define BRXSNR_D 0xff0000002229#define BSNR_EVMT_LENGTH 82230#define BSNR_EVMF_LENGTH 12231#define BCSI1ST 0xff2232#define BCSI2ND 0xff002233#define BRXEVM1ST 0xff00002234#define BRXEVM2ND 0xff0000002235#define BSIGEVM 0xff2236#define BPWDB 0xff002237#define BSGIEN 0x100002238 2239#define BSFACTOR_QMA1 0xf2240#define BSFACTOR_QMA2 0xf02241#define BSFACTOR_QMA3 0xf002242#define BSFACTOR_QMA4 0xf0002243#define BSFACTOR_QMA5 0xf00002244#define BSFACTOR_QMA6 0xf00002245#define BSFACTOR_QMA7 0xf000002246#define BSFACTOR_QMA8 0xf0000002247#define BSFACTOR_QMA9 0xf00000002248#define BCSI_SCHEME 0x1000002249 2250#define BNOISE_LVL_TOP_SET 0x32251#define BCHSMOOTH 0x42252#define BCHSMOOTH_CFG1 0x382253#define BCHSMOOTH_CFG2 0x1c02254#define BCHSMOOTH_CFG3 0xe002255#define BCHSMOOTH_CFG4 0x70002256#define BMRCMODE 0x8000002257#define BTHEVMCFG 0x70000002258 2259#define BLOOP_FIT_TYPE 0x12260#define BUPD_CFO 0x402261#define BUPD_CFO_OFFDATA 0x802262#define BADV_UPD_CFO 0x1002263#define BADV_TIME_CTRL 0x8002264#define BUPD_CLKO 0x10002265#define BFC 0x60002266#define BTRACKING_MODE 0x80002267#define BPHCMP_ENABLE 0x100002268#define BUPD_CLKO_LTF 0x200002269#define BCOM_CH_CFO 0x400002270#define BCSI_ESTI_MODE 0x800002271#define BADV_UPD_EQZ 0x1000002272#define BUCHCFG 0x70000002273#define BUPDEQZ 0x80000002274 2275#define BRX_PESUDO_NOISE_ON 0x200000002276#define BRX_PESUDO_NOISE_A 0xff2277#define BRX_PESUDO_NOISE_B 0xff002278#define BRX_PESUDO_NOISE_C 0xff00002279#define BRX_PESUDO_NOISE_D 0xff0000002280#define BRX_PESUDO_NOISESTATE_A 0xffff2281#define BRX_PESUDO_NOISESTATE_B 0xffff00002282#define BRX_PESUDO_NOISESTATE_C 0xffff2283#define BRX_PESUDO_NOISESTATE_D 0xffff00002284 2285#define BZEBRA1_HSSIENABLE 0x82286#define BZEBRA1_TRXCONTROL 0xc002287#define BZEBRA1_TRXGAINSETTING 0x07f2288#define BZEBRA1_RXCOUNTER 0xc002289#define BZEBRA1_TXCHANGEPUMP 0x382290#define BZEBRA1_RXCHANGEPUMP 0x72291#define BZEBRA1_CHANNEL_NUM 0xf802292#define BZEBRA1_TXLPFBW 0x4002293#define BZEBRA1_RXLPFBW 0x6002294 2295#define BRTL8256REG_MODE_CTRL1 0x1002296#define BRTL8256REG_MODE_CTRL0 0x402297#define BRTL8256REG_TXLPFBW 0x182298#define BRTL8256REG_RXLPFBW 0x6002299 2300#define BRTL8258_TXLPFBW 0xc2301#define BRTL8258_RXLPFBW 0xc002302#define BRTL8258_RSSILPFBW 0xc02303 2304#define BBYTE0 0x12305#define BBYTE1 0x22306#define BBYTE2 0x42307#define BBYTE3 0x82308#define BWORD0 0x32309#define BWORD1 0xc2310#define BWORD 0xf2311 2312#define MASKBYTE0 0xff2313#define MASKBYTE1 0xff002314#define MASKBYTE2 0xff00002315#define MASKBYTE3 0xff0000002316#define MASKHWORD 0xffff00002317#define MASKLWORD 0x0000ffff2318#define MASKDWORD 0xffffffff2319#define MASK12BITS 0xfff2320#define MASKH4BITS 0xf00000002321#define MASKOFDM_D 0xffc000002322#define MASKCCK 0x3f3f3f3f2323 2324#define MASK4BITS 0x0f2325#define MASK20BITS 0xfffff2326#define RFREG_OFFSET_MASK 0xfffff2327 2328#define BENABLE 0x12329#define BDISABLE 0x02330 2331#define LEFT_ANTENNA 0x02332#define RIGHT_ANTENNA 0x12333 2334#define TCHECK_TXSTATUS 5002335#define TUPDATE_RXCOUNTER 1002336 2337#define REG_UN_used_register 0x01bf2338 2339/* Path_A RFE cotrol pinmux*/2340#define RA_RFE_PINMUX 0xcb02341/* Path_B RFE control pinmux*/2342#define RB_RFE_PINMUX 0xeb02343 2344#define RA_RFE_INV 0xcb42345#define RB_RFE_INV 0xeb42346 2347/* RXIQC */2348/*RxIQ imblance matrix coeff. A & B*/2349#define RA_RXIQC_AB 0xc102350/*RxIQ imblance matrix coeff. C & D*/2351#define RA_RXIQC_CD 0xc142352/* Pah_A TX scaling factor*/2353#define RA_TXSCALE 0xc1c2354/* Path_B TX scaling factor*/2355#define RB_TXSCALE 0xe1c2356/*RxIQ imblance matrix coeff. A & B*/2357#define RB_RXIQC_AB 0xe102358/*RxIQ imblance matrix coeff. C & D*/2359#define RB_RXIQC_CD 0xe142360/*bit mask for IQC matrix element A & C*/2361#define RXIQC_AC 0x02ff2362 /*bit mask for IQC matrix element A & C*/2363#define RXIQC_BD 0x02ff00002364 2365/* 2 EFUSE_TEST (For RTL8723 partially) */2366#define EFUSE_SEL(x) (((x) & 0x3) << 8)2367#define EFUSE_SEL_MASK 0x3002368#define EFUSE_WIFI_SEL_0 0x02369 2370/*REG_MULTI_FUNC_CTRL(For RTL8723 Only)*/2371/* Enable GPIO[9] as WiFi HW PDn source*/2372#define WL_HWPDN_EN BIT(0)2373/* WiFi HW PDn polarity control*/2374#define WL_HWPDN_SL BIT(1)2375/* WiFi function enable */2376#define WL_FUNC_EN BIT(2)2377/* Enable GPIO[9] as WiFi RF HW PDn source */2378#define WL_HWROF_EN BIT(3)2379/* Enable GPIO[11] as BT HW PDn source */2380#define BT_HWPDN_EN BIT(16)2381/* BT HW PDn polarity control */2382#define BT_HWPDN_SL BIT(17)2383/* BT function enable */2384#define BT_FUNC_EN BIT(18)2385/* Enable GPIO[11] as BT/GPS RF HW PDn source */2386#define BT_HWROF_EN BIT(19)2387/* Enable GPIO[10] as GPS HW PDn source */2388#define GPS_HWPDN_EN BIT(20)2389/* GPS HW PDn polarity control */2390#define GPS_HWPDN_SL BIT(21)2391/* GPS function enable */2392#define GPS_FUNC_EN BIT(22)2393 2394#define BMASKBYTE0 0xff2395#define BMASKBYTE1 0xff002396#define BMASKBYTE2 0xff00002397#define BMASKBYTE3 0xff0000002398#define BMASKHWORD 0xffff00002399#define BMASKLWORD 0x0000ffff2400#define BMASKDWORD 0xffffffff2401#define BMASK12BITS 0xfff2402#define BMASKH4BITS 0xf00000002403#define BMASKOFDM_D 0xffc000002404#define BMASKCCK 0x3f3f3f3f2405#define BMASKRFEINV 0x3ff000002406 2407#define BRFREGOFFSETMASK 0xfffff2408 2409#define ODM_REG_CCK_RPT_FORMAT_11AC 0x8042410#define ODM_REG_BB_RX_PATH_11AC 0x8082411/*PAGE 9*/2412#define ODM_REG_OFDM_FA_RST_11AC 0x9A42413/*PAGE A*/2414#define ODM_REG_CCK_CCA_11AC 0xA0A2415#define ODM_REG_CCK_FA_RST_11AC 0xA2C2416#define ODM_REG_CCK_FA_11AC 0xA5C2417/*PAGE C*/2418#define ODM_REG_IGI_A_11AC 0xC502419/*PAGE E*/2420#define ODM_REG_IGI_B_11AC 0xE502421/*PAGE F*/2422#define ODM_REG_OFDM_FA_11AC 0xF482423 2424/* 2 MAC REG LIST */2425 2426/* DIG Related */2427#define ODM_BIT_IGI_11AC 0xFFFFFFFF2428#define ODM_BIT_CCK_RPT_FORMAT_11AC BIT162429#define ODM_BIT_BB_RX_PATH_11AC 0xF2430 2431enum AGGRE_SIZE {2432 HT_AGG_SIZE_8K = 0,2433 HT_AGG_SIZE_16K = 1,2434 HT_AGG_SIZE_32K = 2,2435 HT_AGG_SIZE_64K = 3,2436 VHT_AGG_SIZE_128K = 4,2437 VHT_AGG_SIZE_256K = 5,2438 VHT_AGG_SIZE_512K = 6,2439 VHT_AGG_SIZE_1024K = 7,2440};2441 2442#define REG_AMPDU_MAX_LENGTH_8812 0x04582443 2444#endif2445