750 lines · c
1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */2/* Copyright(c) 2018-2019 Realtek Corporation3 */4 5#ifndef __RTW_REG_DEF_H__6#define __RTW_REG_DEF_H__7 8#define REG_SYS_FUNC_EN 0x00029#define BIT_FEN_EN_25_1 BIT(13)10#define BIT_FEN_ELDR BIT(12)11#define BIT_FEN_CPUEN BIT(2)12#define BIT_FEN_BB_GLB_RST BIT(1)13#define BIT_FEN_BB_RSTB BIT(0)14#define BIT_R_DIS_PRST BIT(6)15#define BIT_WLOCK_1C_B6 BIT(5)16#define REG_SYS_PW_CTRL 0x000417#define BIT_PFM_WOWL BIT(3)18#define BIT_APFM_OFFMAC BIT(9)19#define REG_SYS_CLK_CTRL 0x000820#define BIT_CPU_CLK_EN BIT(14)21 22#define REG_SYS_CLKR 0x000823#define BIT_ANA8M BIT(1)24#define BIT_WAKEPAD_EN BIT(3)25#define BIT_LOADER_CLK_EN BIT(5)26 27#define REG_RSV_CTRL 0x001C28#define DISABLE_PI 0x329#define ENABLE_PI 0x230#define BITS_RFC_DIRECT (BIT(31) | BIT(30))31#define BIT_WLMCU_IOIF BIT(0)32#define REG_RF_CTRL 0x001F33#define BIT_RF_SDM_RSTB BIT(2)34#define BIT_RF_RSTB BIT(1)35#define BIT_RF_EN BIT(0)36 37#define REG_AFE_CTRL1 0x002438#define BIT_MAC_CLK_SEL (BIT(20) | BIT(21))39#define REG_EFUSE_CTRL 0x003040#define BIT_EF_FLAG BIT(31)41#define BIT_SHIFT_EF_ADDR 842#define BIT_MASK_EF_ADDR 0x3ff43#define BIT_MASK_EF_DATA 0xff44#define BITS_EF_ADDR (BIT_MASK_EF_ADDR << BIT_SHIFT_EF_ADDR)45#define BITS_PLL 0xf046 47#define REG_AFE_XTAL_CTRL 0x2448#define REG_AFE_PLL_CTRL 0x2849#define REG_AFE_CTRL3 0x2c50#define BIT_MASK_XTAL 0x00FFF00051#define BIT_XTAL_GMP_BIT4 BIT(28)52 53#define REG_LDO_EFUSE_CTRL 0x003454#define BIT_MASK_EFUSE_BANK_SEL (BIT(8) | BIT(9))55 56#define BIT_LDO25_VOLTAGE_V25 0x0357#define BIT_MASK_LDO25_VOLTAGE GENMASK(6, 4)58#define BIT_SHIFT_LDO25_VOLTAGE 459#define BIT_LDO25_EN BIT(7)60 61#define REG_GPIO_MUXCFG 0x004062#define BIT_FSPI_EN BIT(19)63#define BIT_EN_SIC BIT(12)64 65#define BIT_PO_BT_PTA_PINS BIT(9)66#define BIT_BT_PTA_EN BIT(5)67#define BIT_WLRFE_4_5_EN BIT(2)68 69#define REG_LED_CFG 0x004C70#define BIT_LNAON_SEL_EN BIT(26)71#define BIT_PAPE_SEL_EN BIT(25)72#define BIT_DPDT_WL_SEL BIT(24)73#define BIT_DPDT_SEL_EN BIT(23)74#define REG_LEDCFG2 0x004E75#define REG_PAD_CTRL1 0x006476#define BIT_BT_BTG_SEL BIT(31)77#define BIT_PAPE_WLBT_SEL BIT(29)78#define BIT_LNAON_WLBT_SEL BIT(28)79#define BIT_BTGP_JTAG_EN BIT(24)80#define BIT_BTGP_SPI_EN BIT(20)81#define BIT_LED1DIS BIT(15)82#define BIT_SW_DPDT_SEL_DATA BIT(0)83#define REG_WL_BT_PWR_CTRL 0x006884#define BIT_BT_FUNC_EN BIT(18)85#define BIT_BT_DIG_CLK_EN BIT(8)86#define REG_SYS_SDIO_CTRL 0x007087#define BIT_DBG_GNT_WL_BT BIT(27)88#define BIT_LTE_MUX_CTRL_PATH BIT(26)89#define REG_HCI_OPT_CTRL 0x007490#define BIT_USB_SUS_DIS BIT(8)91#define BIT_SDIO_PAD_E5 BIT(18)92 93#define REG_AFE_CTRL_4 0x007894#define BIT_CK320M_AFE_EN BIT(4)95#define BIT_EN_SYN BIT(15)96 97#define REG_LDO_SWR_CTRL 0x007C98#define LDO_SEL 0xC399#define SPS_SEL 0x83100#define BIT_XTA1 BIT(29)101#define BIT_XTA0 BIT(28)102 103#define REG_MCUFW_CTRL 0x0080104#define BIT_ANA_PORT_EN BIT(22)105#define BIT_MAC_PORT_EN BIT(21)106#define BIT_BOOT_FSPI_EN BIT(20)107#define BIT_ROM_DLEN BIT(19)108#define BIT_ROM_PGE GENMASK(18, 16) /* legacy only */109#define BIT_SHIFT_ROM_PGE 16110#define BIT_FW_INIT_RDY BIT(15)111#define BIT_FW_DW_RDY BIT(14)112#define BIT_RPWM_TOGGLE BIT(7)113#define BIT_RAM_DL_SEL BIT(7) /* legacy only */114#define BIT_DMEM_CHKSUM_OK BIT(6)115#define BIT_WINTINI_RDY BIT(6) /* legacy only */116#define BIT_DMEM_DW_OK BIT(5)117#define BIT_IMEM_CHKSUM_OK BIT(4)118#define BIT_IMEM_DW_OK BIT(3)119#define BIT_IMEM_BOOT_LOAD_CHECKSUM_OK BIT(2)120#define BIT_FWDL_CHK_RPT BIT(2) /* legacy only */121#define BIT_MCUFWDL_RDY BIT(1) /* legacy only */122#define BIT_MCUFWDL_EN BIT(0)123#define BIT_CHECK_SUM_OK (BIT(4) | BIT(6))124#define FW_READY (BIT_FW_INIT_RDY | BIT_FW_DW_RDY | \125 BIT_IMEM_DW_OK | BIT_DMEM_DW_OK | \126 BIT_CHECK_SUM_OK)127#define FW_READY_LEGACY (BIT_MCUFWDL_RDY | BIT_FWDL_CHK_RPT | \128 BIT_WINTINI_RDY | BIT_RAM_DL_SEL)129#define FW_READY_MASK 0xffff130 131#define REG_MCU_TST_CFG 0x84132#define VAL_FW_TRIGGER 0x1133 134#define REG_PMC_DBG_CTRL1 0xa8135#define BITS_PMC_BT_IQK_STS GENMASK(22, 21)136 137#define REG_PAD_CTRL2 0x00C4138#define BIT_RSM_EN_V1 BIT(16)139#define BIT_NO_PDN_CHIPOFF_V1 BIT(17)140#define BIT_MASK_USB23_SW_MODE_V1 GENMASK(19, 18)141#define BIT_USB3_USB2_TRANSITION BIT(20)142#define BIT_USB_MODE_U2 1143#define BIT_USB_MODE_U3 2144 145#define REG_EFUSE_ACCESS 0x00CF146#define EFUSE_ACCESS_ON 0x69147#define EFUSE_ACCESS_OFF 0x00148 149#define REG_WLRF1 0x00EC150#define REG_WIFI_BT_INFO 0x00AA151#define BIT_BT_INT_EN BIT(15)152#define REG_SYS_CFG1 0x00F0153#define BIT_RTL_ID BIT(23)154#define BIT_LDO BIT(24)155#define BIT_RF_TYPE_ID BIT(27)156#define BIT_SHIFT_VENDOR_ID 16157#define BIT_MASK_VENDOR_ID 0xf158#define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID)159#define BITS_VENDOR_ID (BIT_MASK_VENDOR_ID << BIT_SHIFT_VENDOR_ID)160#define BIT_CLEAR_VENDOR_ID(x) ((x) & (~BITS_VENDOR_ID))161#define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID)162#define BIT_SHIFT_CHIP_VER 12163#define BIT_MASK_CHIP_VER 0xf164#define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER)165#define BITS_CHIP_VER (BIT_MASK_CHIP_VER << BIT_SHIFT_CHIP_VER)166#define BIT_CLEAR_CHIP_VER(x) ((x) & (~BITS_CHIP_VER))167#define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER)168#define REG_SYS_STATUS1 0x00F4169#define REG_SYS_STATUS2 0x00F8170#define REG_SYS_CFG2 0x00FC171#define REG_WLRF1 0x00EC172#define BIT_WLRF1_BBRF_EN (BIT(24) | BIT(25) | BIT(26))173#define REG_CR 0x0100174#define BIT_32K_CAL_TMR_EN BIT(10)175#define BIT_MAC_SEC_EN BIT(9)176#define BIT_ENSWBCN BIT(8)177#define BIT_MACRXEN BIT(7)178#define BIT_MACTXEN BIT(6)179#define BIT_SCHEDULE_EN BIT(5)180#define BIT_PROTOCOL_EN BIT(4)181#define BIT_RXDMA_EN BIT(3)182#define BIT_TXDMA_EN BIT(2)183#define BIT_HCI_RXDMA_EN BIT(1)184#define BIT_HCI_TXDMA_EN BIT(0)185#define MAC_TRX_ENABLE (BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN | \186 BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN | \187 BIT_MACTXEN | BIT_MACRXEN)188#define BIT_SHIFT_TXDMA_VOQ_MAP 4189#define BIT_MASK_TXDMA_VOQ_MAP 0x3190#define BIT_TXDMA_VOQ_MAP(x) \191 (((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP)192#define BIT_SHIFT_TXDMA_VIQ_MAP 6193#define BIT_MASK_TXDMA_VIQ_MAP 0x3194#define BIT_TXDMA_VIQ_MAP(x) \195 (((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP)196#define REG_TXDMA_PQ_MAP 0x010C197#define BIT_RXDMA_ARBBW_EN BIT(0)198#define BIT_RXSHFT_EN BIT(1)199#define BIT_RXDMA_AGG_EN BIT(2)200#define BIT_TXDMA_BW_EN BIT(3)201#define BIT_SHIFT_TXDMA_BEQ_MAP 8202#define BIT_MASK_TXDMA_BEQ_MAP 0x3203#define BIT_TXDMA_BEQ_MAP(x) \204 (((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP)205#define BIT_SHIFT_TXDMA_BKQ_MAP 10206#define BIT_MASK_TXDMA_BKQ_MAP 0x3207#define BIT_TXDMA_BKQ_MAP(x) \208 (((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP)209#define BIT_SHIFT_TXDMA_MGQ_MAP 12210#define BIT_MASK_TXDMA_MGQ_MAP 0x3211#define BIT_TXDMA_MGQ_MAP(x) \212 (((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP)213#define BIT_SHIFT_TXDMA_HIQ_MAP 14214#define BIT_MASK_TXDMA_HIQ_MAP 0x3215#define BIT_TXDMA_HIQ_MAP(x) \216 (((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP)217#define BIT_SHIFT_TXSC_40M 4218#define BIT_MASK_TXSC_40M 0xf219#define BIT_TXSC_40M(x) \220 (((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M)221#define BIT_SHIFT_TXSC_20M 0222#define BIT_MASK_TXSC_20M 0xf223#define BIT_TXSC_20M(x) \224 (((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M)225#define BIT_SHIFT_MAC_CLK_SEL 20226#define MAC_CLK_HW_DEF_80M 0227#define MAC_CLK_HW_DEF_40M 1228#define MAC_CLK_HW_DEF_20M 2229#define MAC_CLK_SPEED 80230 231#define REG_CR 0x0100232#define REG_TRXFF_BNDY 0x0114233#define REG_RXFF_BNDY 0x011C234#define REG_FE1IMR 0x0120235#define BIT_FS_RXDONE BIT(16)236#define REG_CPWM 0x012C237#define REG_FWIMR 0x0130238#define BIT_FS_H2CCMD_INT_EN BIT(4)239#define BIT_FS_HRCV_INT_EN BIT(5)240#define REG_FWISR 0x0134241#define BIT_FS_H2CCMD_INT BIT(4)242#define BIT_FS_HRCV_INT BIT(5)243#define REG_PKTBUF_DBG_CTRL 0x0140244#define REG_C2HEVT 0x01A0245#define REG_MCUTST_1 0x01C0246#define REG_MCUTST_II 0x01C4247#define REG_WOWLAN_WAKE_REASON 0x01C7248#define REG_HMETFR 0x01CC249#define BIT_INT_BOX0 BIT(0)250#define BIT_INT_BOX1 BIT(1)251#define BIT_INT_BOX2 BIT(2)252#define BIT_INT_BOX3 BIT(3)253#define BIT_INT_BOX_ALL (BIT_INT_BOX0 | BIT_INT_BOX1 | BIT_INT_BOX2 | \254 BIT_INT_BOX3)255#define REG_HMEBOX0 0x01D0256#define REG_HMEBOX1 0x01D4257#define REG_HMEBOX2 0x01D8258#define REG_HMEBOX3 0x01DC259#define REG_HMEBOX0_EX 0x01F0260#define REG_HMEBOX1_EX 0x01F4261#define REG_HMEBOX2_EX 0x01F8262#define REG_HMEBOX3_EX 0x01FC263 264#define REG_RQPN 0x0200265#define BIT_MASK_HPQ 0xff266#define BIT_SHIFT_HPQ 0267#define BIT_RQPN_HPQ(x) (((x) & BIT_MASK_HPQ) << BIT_SHIFT_HPQ)268#define BIT_MASK_LPQ 0xff269#define BIT_SHIFT_LPQ 8270#define BIT_RQPN_LPQ(x) (((x) & BIT_MASK_LPQ) << BIT_SHIFT_LPQ)271#define BIT_MASK_PUBQ 0xff272#define BIT_SHIFT_PUBQ 16273#define BIT_RQPN_PUBQ(x) (((x) & BIT_MASK_PUBQ) << BIT_SHIFT_PUBQ)274#define BIT_RQPN_HLP(h, l, p) (BIT_LD_RQPN | BIT_RQPN_HPQ(h) | \275 BIT_RQPN_LPQ(l) | BIT_RQPN_PUBQ(p))276 277#define REG_FIFOPAGE_CTRL_2 0x0204278#define BIT_BCN_VALID_V1 BIT(15)279#define BIT_MASK_BCN_HEAD_1_V1 0xfff280#define REG_AUTO_LLT_V1 0x0208281#define BIT_AUTO_INIT_LLT_V1 BIT(0)282#define BIT_MASK_BLK_DESC_NUM GENMASK(7, 4)283#define REG_DWBCN0_CTRL 0x0208284#define BIT_BCN_VALID BIT(16)285#define REG_TXDMA_OFFSET_CHK 0x020C286#define BIT_DROP_DATA_EN BIT(9)287#define REG_TXDMA_STATUS 0x0210288#define BTI_PAGE_OVF BIT(2)289 290#define REG_RQPN_NPQ 0x0214291#define BIT_MASK_NPQ 0xff292#define BIT_SHIFT_NPQ 0293#define BIT_MASK_EPQ 0xff294#define BIT_SHIFT_EPQ 16295#define BIT_RQPN_NPQ(x) (((x) & BIT_MASK_NPQ) << BIT_SHIFT_NPQ)296#define BIT_RQPN_EPQ(x) (((x) & BIT_MASK_EPQ) << BIT_SHIFT_EPQ)297#define BIT_RQPN_NE(n, e) (BIT_RQPN_NPQ(n) | BIT_RQPN_EPQ(e))298 299#define REG_AUTO_LLT 0x0224300#define BIT_AUTO_INIT_LLT BIT(16)301#define REG_RQPN_CTRL_1 0x0228302#define REG_RQPN_CTRL_2 0x022C303#define BIT_LD_RQPN BIT(31)304#define REG_FIFOPAGE_INFO_1 0x0230305#define REG_FIFOPAGE_INFO_2 0x0234306#define REG_FIFOPAGE_INFO_3 0x0238307#define REG_FIFOPAGE_INFO_4 0x023C308#define REG_FIFOPAGE_INFO_5 0x0240309#define REG_H2C_HEAD 0x0244310#define REG_H2C_TAIL 0x0248311#define REG_H2C_READ_ADDR 0x024C312#define REG_H2C_INFO 0x0254313#define REG_RXDMA_AGG_PG_TH 0x0280314#define BIT_RXDMA_AGG_PG_TH GENMASK(7, 0)315#define BIT_DMA_AGG_TO_V1 GENMASK(15, 8)316#define BIT_EN_PRE_CALC BIT(29)317#define REG_RXPKT_NUM 0x0284318#define BIT_RXDMA_REQ BIT(19)319#define BIT_RW_RELEASE BIT(18)320#define BIT_RXDMA_IDLE BIT(17)321#define REG_RXDMA_STATUS 0x0288322#define REG_RXDMA_DPR 0x028C323#define REG_RXDMA_MODE 0x0290324#define BIT_DMA_MODE BIT(1)325#define BIT_DMA_BURST_CNT GENMASK(3, 2)326#define BIT_DMA_BURST_SIZE GENMASK(5, 4)327#define BIT_DMA_BURST_SIZE_64 2328#define BIT_DMA_BURST_SIZE_512 1329#define BIT_DMA_BURST_SIZE_1024 0330 331#define REG_RXPKTNUM 0x02B0332 333#define REG_INT_MIG 0x0304334#define REG_HCI_MIX_CFG 0x03FC335#define BIT_PCIE_EMAC_PDN_AUX_TO_FAST_CLK BIT(26)336 337#define REG_BCNQ_INFO 0x0418338#define BIT_MGQ_CPU_EMPTY BIT(24)339#define REG_FWHW_TXQ_CTRL 0x0420340#define BIT_EN_BCNQ_DL BIT(22)341#define BIT_EN_WR_FREE_TAIL BIT(20)342#define REG_HWSEQ_CTRL 0x0423343 344#define REG_BCNQ_BDNY_V1 0x0424345#define REG_BCNQ_BDNY 0x0424346#define REG_MGQ_BDNY 0x0425347#define REG_LIFETIME_EN 0x0426348#define BIT_BA_PARSER_EN BIT(5)349#define REG_SPEC_SIFS 0x0428350#define REG_RETRY_LIMIT 0x042a351#define REG_DARFRC 0x0430352#define REG_DARFRCH 0x0434353#define REG_RARFRCH 0x043C354#define REG_RRSR 0x0440355#define BITS_RRSR_RSC GENMASK(22, 21)356#define REG_ARFR0 0x0444357#define REG_ARFRH0 0x0448358#define REG_ARFR1_V1 0x044C359#define REG_ARFRH1_V1 0x0450360#define REG_CCK_CHECK 0x0454361#define BIT_CHECK_CCK_EN BIT(7)362#define REG_AMPDU_MAX_TIME_V1 0x0455363#define REG_BCNQ1_BDNY_V1 0x0456364#define REG_AMPDU_MAX_TIME 0x0456365#define REG_WMAC_LBK_BF_HD 0x045D366#define REG_TX_HANG_CTRL 0x045E367#define BIT_EN_GNT_BT_AWAKE BIT(3)368#define BIT_EN_EOF_V1 BIT(2)369#define REG_DATA_SC 0x0483370#define REG_ARFR2_V1 0x048C371#define REG_ARFRH2_V1 0x0490372#define REG_ARFR3_V1 0x0494373#define BIT_EXC_CODE GENMASK(6, 2)374#define REG_ARFRH3_V1 0x0498375#define REG_ARFR4 0x049C376#define BIT_WL_RFK BIT(0)377#define REG_ARFRH4 0x04A0378#define REG_ARFR5 0x04A4379#define REG_ARFRH5 0x04A8380#define REG_SW_AMPDU_BURST_MODE_CTRL 0x04BC381#define BIT_PRE_TX_CMD BIT(6)382#define REG_QUEUE_CTRL 0x04C6383#define BIT_PTA_WL_TX_EN BIT(4)384#define BIT_PTA_EDCCA_EN BIT(5)385#define REG_SINGLE_AMPDU_CTRL 0x04C7386#define BIT_EN_SINGLE_APMDU BIT(7)387#define REG_PROT_MODE_CTRL 0x04C8388#define REG_MAX_AGGR_NUM 0x04CA389#define REG_BAR_MODE_CTRL 0x04CC390#define REG_PRECNT_CTRL 0x04E5391#define BIT_BTCCA_CTRL (BIT(0) | BIT(1))392#define BIT_EN_PRECNT BIT(11)393#define REG_DUMMY_PAGE4_V1 0x04FC394 395#define REG_EDCA_VO_PARAM 0x0500396#define REG_EDCA_VI_PARAM 0x0504397#define REG_EDCA_BE_PARAM 0x0508398#define REG_EDCA_BK_PARAM 0x050C399#define BIT_MASK_TXOP_LMT GENMASK(26, 16)400#define BIT_MASK_CWMAX GENMASK(15, 12)401#define BIT_MASK_CWMIN GENMASK(11, 8)402#define BIT_MASK_AIFS GENMASK(7, 0)403#define REG_PIFS 0x0512404#define REG_SIFS 0x0514405#define BIT_SHIFT_SIFS_OFDM_CTX 8406#define BIT_SHIFT_SIFS_CCK_TRX 16407#define BIT_SHIFT_SIFS_OFDM_TRX 24408#define REG_AGGR_BREAK_TIME 0x051A409#define REG_SLOT 0x051B410#define REG_TX_PTCL_CTRL 0x0520411#define BIT_DIS_EDCCA BIT(15)412#define BIT_SIFS_BK_EN BIT(12)413#define REG_TXPAUSE 0x0522414#define BIT_AC_QUEUE GENMASK(7, 0)415#define BIT_HIGH_QUEUE BIT(5)416#define REG_RD_CTRL 0x0524417#define BIT_EDCCA_MSK_CNTDOWN_EN BIT(11)418#define BIT_DIS_TXOP_CFE BIT(10)419#define BIT_DIS_LSIG_CFE BIT(9)420#define BIT_DIS_STBC_CFE BIT(8)421#define REG_TBTT_PROHIBIT 0x0540422#define BIT_SHIFT_TBTT_HOLD_TIME_AP 8423#define REG_RD_NAV_NXT 0x0544424#define REG_NAV_PROT_LEN 0x0546425#define REG_BCN_CTRL 0x0550426#define BIT_DIS_TSF_UDT BIT(4)427#define BIT_EN_BCN_FUNCTION BIT(3)428#define BIT_EN_TXBCN_RPT BIT(2)429#define REG_BCN_CTRL_CLINT0 0x0551430#define REG_DRVERLYINT 0x0558431#define REG_BCNDMATIM 0x0559432#define REG_ATIMWND 0x055A433#define REG_USTIME_TSF 0x055C434#define REG_BCN_MAX_ERR 0x055D435#define REG_RXTSF_OFFSET_CCK 0x055E436#define REG_MISC_CTRL 0x0577437#define BIT_EN_FREE_CNT BIT(3)438#define BIT_DIS_SECOND_CCA (BIT(0) | BIT(1))439#define REG_HIQ_NO_LMT_EN 0x5A7440#define REG_DTIM_COUNTER_ROOT 0x5A8441#define BIT_HIQ_NO_LMT_EN_ROOT BIT(0)442#define REG_TIMER0_SRC_SEL 0x05B4443#define BIT_TSFT_SEL_TIMER0 (BIT(4) | BIT(5) | BIT(6))444 445#define REG_TCR 0x0604446#define BIT_PWRMGT_HWDATA_EN BIT(7)447#define BIT_TCR_UPDATE_TIMIE BIT(5)448#define BIT_TCR_UPDATE_HGQMD BIT(4)449#define REG_RCR 0x0608450#define BIT_APP_FCS BIT(31)451#define BIT_APP_MIC BIT(30)452#define BIT_APP_ICV BIT(29)453#define BIT_APP_PHYSTS BIT(28)454#define BIT_APP_BASSN BIT(27)455#define BIT_VHT_DACK BIT(26)456#define BIT_TCPOFLD_EN BIT(25)457#define BIT_ENMBID BIT(24)458#define BIT_LSIGEN BIT(23)459#define BIT_MFBEN BIT(22)460#define BIT_DISCHKPPDLLEN BIT(21)461#define BIT_PKTCTL_DLEN BIT(20)462#define BIT_DISGCLK BIT(19)463#define BIT_TIM_PARSER_EN BIT(18)464#define BIT_BC_MD_EN BIT(17)465#define BIT_UC_MD_EN BIT(16)466#define BIT_RXSK_PERPKT BIT(15)467#define BIT_HTC_LOC_CTRL BIT(14)468#define BIT_RPFM_CAM_ENABLE BIT(12)469#define BIT_TA_BCN BIT(11)470#define BIT_RCR_ADF BIT(11)471#define BIT_DISDECMYPKT BIT(10)472#define BIT_AICV BIT(9)473#define BIT_ACRC32 BIT(8)474#define BIT_CBSSID_BCN BIT(7)475#define BIT_CBSSID_DATA BIT(6)476#define BIT_APWRMGT BIT(5)477#define BIT_ADD3 BIT(4)478#define BIT_AB BIT(3)479#define BIT_AM BIT(2)480#define BIT_APM BIT(1)481#define BIT_AAP BIT(0)482#define REG_RX_PKT_LIMIT 0x060C483#define REG_RX_DRVINFO_SZ 0x060F484#define BIT_APP_PHYSTS BIT(28)485#define REG_MAR 0x0620486#define REG_USTIME_EDCA 0x0638487#define REG_ACKTO_CCK 0x0639488#define REG_MAC_SPEC_SIFS 0x063A489#define REG_RESP_SIFS_CCK 0x063C490#define REG_RESP_SIFS_OFDM 0x063E491#define REG_ACKTO 0x0640492#define REG_EIFS 0x0642493#define REG_NAV_CTRL 0x0650494#define REG_WMAC_TRXPTCL_CTL 0x0668495#define BIT_RFMOD (BIT(7) | BIT(8))496#define BIT_RFMOD_80M BIT(8)497#define BIT_RFMOD_40M BIT(7)498#define REG_WMAC_TRXPTCL_CTL_H 0x066C499#define REG_WKFMCAM_CMD 0x0698500#define BIT_WKFCAM_POLLING_V1 BIT(31)501#define BIT_WKFCAM_CLR_V1 BIT(30)502#define BIT_WKFCAM_WE BIT(16)503#define BIT_SHIFT_WKFCAM_ADDR_V2 8504#define BIT_MASK_WKFCAM_ADDR_V2 0xff505#define BIT_WKFCAM_ADDR_V2(x) \506 (((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2)507#define REG_WKFMCAM_RWD 0x069C508#define BIT_WKFMCAM_VALID BIT(31)509#define BIT_WKFMCAM_BC BIT(26)510#define BIT_WKFMCAM_MC BIT(25)511#define BIT_WKFMCAM_UC BIT(24)512 513#define REG_RXFLTMAP0 0x06A0514#define REG_RXFLTMAP1 0x06A2515#define REG_RXFLTMAP2 0x06A4516#define REG_RXFLTMAP4 0x068A517#define REG_BT_COEX_TABLE0 0x06C0518#define REG_BT_COEX_TABLE1 0x06C4519#define REG_BT_COEX_BRK_TABLE 0x06C8520#define REG_BT_COEX_TABLE_H 0x06CC521#define REG_BT_COEX_TABLE_H1 0x06CD522#define REG_BT_COEX_TABLE_H2 0x06CE523#define REG_BT_COEX_TABLE_H3 0x06CF524#define REG_BBPSF_CTRL 0x06DC525 526#define REG_BT_COEX_V2 0x0762527#define BIT_GNT_BT_POLARITY BIT(12)528#define BIT_LTE_COEX_EN BIT(7)529#define REG_BT_COEX_ENH_INTR_CTRL 0x76E530#define BIT_R_GRANTALL_WLMASK BIT(3)531#define BIT_STATIS_BT_EN BIT(2)532#define REG_BT_ACT_STATISTICS 0x0770533#define REG_BT_ACT_STATISTICS_1 0x0774534#define REG_BT_STAT_CTRL 0x0778535#define REG_BT_TDMA_TIME 0x0790536#define BIT_MASK_SAMPLE_RATE GENMASK(5, 0)537#define REG_LTR_IDLE_LATENCY 0x0798538#define REG_LTR_ACTIVE_LATENCY 0x079C539#define REG_LTR_CTRL_BASIC 0x07A4540#define REG_WMAC_OPTION_FUNCTION 0x07D0541#define REG_WMAC_OPTION_FUNCTION_1 0x07D4542 543#define REG_FPGA0_RFMOD 0x0800544#define BIT_CCKEN BIT(24)545#define BIT_OFDMEN BIT(25)546#define REG_RX_GAIN_EN 0x081c547 548#define REG_RFE_CTRL_E 0x0974549#define REG_2ND_CCA_CTRL 0x0976550 551#define REG_CCK0_FAREPORT 0xa2c552#define BIT_CCK0_2RX BIT(18)553#define BIT_CCK0_MRC BIT(22)554 555#define REG_DIS_DPD 0x0a70556#define DIS_DPD_MASK GENMASK(9, 0)557#define DIS_DPD_RATE6M BIT(0)558#define DIS_DPD_RATE9M BIT(1)559#define DIS_DPD_RATEMCS0 BIT(2)560#define DIS_DPD_RATEMCS1 BIT(3)561#define DIS_DPD_RATEMCS8 BIT(4)562#define DIS_DPD_RATEMCS9 BIT(5)563#define DIS_DPD_RATEVHT1SS_MCS0 BIT(6)564#define DIS_DPD_RATEVHT1SS_MCS1 BIT(7)565#define DIS_DPD_RATEVHT2SS_MCS0 BIT(8)566#define DIS_DPD_RATEVHT2SS_MCS1 BIT(9)567#define DIS_DPD_RATEALL GENMASK(9, 0)568 569#define REG_RFE_CTRL8 0x0cb4570#define BIT_MASK_RFE_SEL89 GENMASK(7, 0)571#define REG_RFE_INV8 0x0cbd572#define BIT_MASK_RFE_INV89 GENMASK(1, 0)573#define REG_RFE_INV16 0x0cbe574#define BIT_RFE_BUF_EN BIT(3)575 576#define REG_ANAPARSW_MAC_0 0x1010577#define BIT_CF_L_V2 GENMASK(29, 28)578 579#define REG_ANAPAR_XTAL_0 0x1040580#define BIT_XCAP_0 GENMASK(23, 10)581#define REG_CPU_DMEM_CON 0x1080582#define BIT_WL_PLATFORM_RST BIT(16)583#define BIT_WL_SECURITY_CLK BIT(15)584#define BIT_DDMA_EN BIT(8)585 586#define REG_SW_MDIO 0x10C0587 588#define REG_H2C_PKT_READADDR 0x10D0589#define REG_H2C_PKT_WRITEADDR 0x10D4590#define REG_FW_DBG6 0x10F8591#define REG_FW_DBG7 0x10FC592#define FW_KEY_MASK 0xffffff00593 594#define REG_CR_EXT 0x1100595 596#define REG_FT1IMR 0x1138597#define BIT_FS_H2C_CMD_OK_INT_EN BIT(25)598#define REG_FT1ISR 0x113c599#define BIT_FS_H2C_CMD_OK_INT BIT(25)600#define REG_DDMA_CH0SA 0x1200601#define REG_DDMA_CH0DA 0x1204602#define REG_DDMA_CH0CTRL 0x1208603#define BIT_DDMACH0_OWN BIT(31)604#define BIT_DDMACH0_CHKSUM_EN BIT(29)605#define BIT_DDMACH0_CHKSUM_STS BIT(27)606#define BIT_DDMACH0_DDMA_MODE BIT(26)607#define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25)608#define BIT_DDMACH0_CHKSUM_CONT BIT(24)609#define BIT_MASK_DDMACH0_DLEN 0x3ffff610 611#define REG_H2CQ_CSR 0x1330612#define BIT_H2CQ_FULL BIT(31)613#define REG_FAST_EDCA_VOVI_SETTING 0x1448614#define REG_FAST_EDCA_BEBK_SETTING 0x144C615 616#define REG_RXPSF_CTRL 0x1610617#define BIT_RXGCK_FIFOTHR_EN BIT(28)618 619#define BIT_SHIFT_RXGCK_VHT_FIFOTHR 26620#define BIT_MASK_RXGCK_VHT_FIFOTHR 0x3621#define BIT_RXGCK_VHT_FIFOTHR(x) \622 (((x) & BIT_MASK_RXGCK_VHT_FIFOTHR) << BIT_SHIFT_RXGCK_VHT_FIFOTHR)623#define BITS_RXGCK_VHT_FIFOTHR \624 (BIT_MASK_RXGCK_VHT_FIFOTHR << BIT_SHIFT_RXGCK_VHT_FIFOTHR)625 626#define BIT_SHIFT_RXGCK_HT_FIFOTHR 24627#define BIT_MASK_RXGCK_HT_FIFOTHR 0x3628#define BIT_RXGCK_HT_FIFOTHR(x) \629 (((x) & BIT_MASK_RXGCK_HT_FIFOTHR) << BIT_SHIFT_RXGCK_HT_FIFOTHR)630#define BITS_RXGCK_HT_FIFOTHR \631 (BIT_MASK_RXGCK_HT_FIFOTHR << BIT_SHIFT_RXGCK_HT_FIFOTHR)632 633#define BIT_SHIFT_RXGCK_OFDM_FIFOTHR 22634#define BIT_MASK_RXGCK_OFDM_FIFOTHR 0x3635#define BIT_RXGCK_OFDM_FIFOTHR(x) \636 (((x) & BIT_MASK_RXGCK_OFDM_FIFOTHR) << BIT_SHIFT_RXGCK_OFDM_FIFOTHR)637#define BITS_RXGCK_OFDM_FIFOTHR \638 (BIT_MASK_RXGCK_OFDM_FIFOTHR << BIT_SHIFT_RXGCK_OFDM_FIFOTHR)639 640#define BIT_SHIFT_RXGCK_CCK_FIFOTHR 20641#define BIT_MASK_RXGCK_CCK_FIFOTHR 0x3642#define BIT_RXGCK_CCK_FIFOTHR(x) \643 (((x) & BIT_MASK_RXGCK_CCK_FIFOTHR) << BIT_SHIFT_RXGCK_CCK_FIFOTHR)644#define BITS_RXGCK_CCK_FIFOTHR \645 (BIT_MASK_RXGCK_CCK_FIFOTHR << BIT_SHIFT_RXGCK_CCK_FIFOTHR)646 647#define BIT_RXGCK_OFDMCCA_EN BIT(16)648 649#define BIT_SHIFT_RXPSF_PKTLENTHR 13650#define BIT_MASK_RXPSF_PKTLENTHR 0x7651#define BIT_RXPSF_PKTLENTHR(x) \652 (((x) & BIT_MASK_RXPSF_PKTLENTHR) << BIT_SHIFT_RXPSF_PKTLENTHR)653#define BITS_RXPSF_PKTLENTHR \654 (BIT_MASK_RXPSF_PKTLENTHR << BIT_SHIFT_RXPSF_PKTLENTHR)655#define BIT_CLEAR_RXPSF_PKTLENTHR(x) ((x) & (~BITS_RXPSF_PKTLENTHR))656#define BIT_SET_RXPSF_PKTLENTHR(x, v) \657 (BIT_CLEAR_RXPSF_PKTLENTHR(x) | BIT_RXPSF_PKTLENTHR(v))658 659#define BIT_RXPSF_CTRLEN BIT(12)660#define BIT_RXPSF_VHTCHKEN BIT(11)661#define BIT_RXPSF_HTCHKEN BIT(10)662#define BIT_RXPSF_OFDMCHKEN BIT(9)663#define BIT_RXPSF_CCKCHKEN BIT(8)664#define BIT_RXPSF_OFDMRST BIT(7)665#define BIT_RXPSF_CCKRST BIT(6)666#define BIT_RXPSF_MHCHKEN BIT(5)667#define BIT_RXPSF_CONT_ERRCHKEN BIT(4)668#define BIT_RXPSF_ALL_ERRCHKEN BIT(3)669 670#define BIT_SHIFT_RXPSF_ERRTHR 0671#define BIT_MASK_RXPSF_ERRTHR 0x7672#define BIT_RXPSF_ERRTHR(x) \673 (((x) & BIT_MASK_RXPSF_ERRTHR) << BIT_SHIFT_RXPSF_ERRTHR)674#define BITS_RXPSF_ERRTHR (BIT_MASK_RXPSF_ERRTHR << BIT_SHIFT_RXPSF_ERRTHR)675#define BIT_CLEAR_RXPSF_ERRTHR(x) ((x) & (~BITS_RXPSF_ERRTHR))676#define BIT_GET_RXPSF_ERRTHR(x) \677 (((x) >> BIT_SHIFT_RXPSF_ERRTHR) & BIT_MASK_RXPSF_ERRTHR)678#define BIT_SET_RXPSF_ERRTHR(x, v) \679 (BIT_CLEAR_RXPSF_ERRTHR(x) | BIT_RXPSF_ERRTHR(v))680 681#define REG_RXPSF_TYPE_CTRL 0x1614682#define REG_GENERAL_OPTION 0x1664683#define BIT_DUMMY_FCS_READY_MASK_EN BIT(9)684 685#define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 0x1700686#define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 0x1704687#define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 0x1708688#define LTECOEX_READY BIT(29)689#define LTECOEX_ACCESS_CTRL REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1690#define LTECOEX_WRITE_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1691#define LTECOEX_READ_DATA REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1692 693#define REG_IGN_GNT_BT1 0x1860694 695#define REG_RFESEL_CTRL 0x1990696 697#define REG_NOMASK_TXBT 0x1ca7698#define REG_ANAPAR 0x1c30699#define BIT_ANAPAR_BTPS BIT(22)700#define REG_RSTB_SEL 0x1c38701#define BIT_DAC_OFF_ENABLE BIT(4)702#define BIT_PI_IGNORE_GNT_BT BIT(3)703#define BIT_NOMASK_TXBT_ENABLE BIT(3)704 705#define REG_HRCV_MSG 0x1cf706 707#define REG_EDCCA_REPORT 0x2d38708#define BIT_EDCCA_FLAG BIT(24)709 710#define REG_IGN_GNTBT4 0x4160711 712#define RF_MODE 0x00713#define RF_MODOPT 0x01714#define RF_WLINT 0x01715#define RF_WLSEL 0x02716#define RF_DTXLOK 0x08717#define RF_CFGCH 0x18718#define BIT_BAND GENMASK(18, 16)719#define RF_RCK 0x1d720#define RF_LUTWA 0x33721#define RF_LUTWD1 0x3e722#define RF_LUTWD0 0x3f723#define BIT_GAIN_EXT BIT(12)724#define BIT_DATA_L GENMASK(11, 0)725#define RF_T_METER 0x42726#define RF_BSPAD 0x54727#define RF_GAINTX 0x56728#define RF_TXATANK 0x64729#define RF_TRXIQ 0x66730#define RF_RXIQGEN 0x8d731#define RF_SYN_PFD 0xb0732#define RF_XTALX2 0xb8733#define RF_SYN_CTRL 0xbb734#define RF_MALSEL 0xbe735#define RF_SYN_AAC 0xc9736#define RF_AAC_CTRL 0xca737#define RF_FAST_LCK 0xcc738#define RF_RCKD 0xde739#define RF_TXADBG 0xde740#define RF_LUTDBG 0xdf741#define BIT_TXA_TANK BIT(4)742#define RF_LUTWE2 0xee743#define RF_LUTWE 0xef744 745#define LTE_COEX_CTRL 0x38746#define LTE_WL_TRX_CTRL 0xa0747#define LTE_BT_TRX_CTRL 0xa4748 749#endif750