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1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */2/* Copyright 2024 Fiona Klute3 *4 * Based on code originally in rtw8723d.[ch],5 * Copyright(c) 2018-2019 Realtek Corporation6 */7 8#ifndef __RTW8723X_H__9#define __RTW8723X_H__10 11#include "main.h"12#include "debug.h"13#include "phy.h"14#include "reg.h"15 16enum rtw8723x_path {17 PATH_S1,18 PATH_S0,19 PATH_NR,20};21 22enum rtw8723x_iqk_round {23 IQK_ROUND_0,24 IQK_ROUND_1,25 IQK_ROUND_2,26 IQK_ROUND_HYBRID,27 IQK_ROUND_SIZE,28 IQK_ROUND_INVALID = 0xff,29};30 31enum rtw8723x_iqk_result {32 IQK_S1_TX_X,33 IQK_S1_TX_Y,34 IQK_S1_RX_X,35 IQK_S1_RX_Y,36 IQK_S0_TX_X,37 IQK_S0_TX_Y,38 IQK_S0_RX_X,39 IQK_S0_RX_Y,40 IQK_NR,41 IQK_SX_NR = IQK_NR / PATH_NR,42};43 44struct rtw8723xe_efuse {45 u8 mac_addr[ETH_ALEN]; /* 0xd0 */46 u8 vendor_id[2];47 u8 device_id[2];48 u8 sub_vendor_id[2];49 u8 sub_device_id[2];50};51 52struct rtw8723xu_efuse {53 u8 res4[48]; /* 0xd0 */54 u8 vendor_id[2]; /* 0x100 */55 u8 product_id[2]; /* 0x102 */56 u8 usb_option; /* 0x104 */57 u8 res5[2]; /* 0x105 */58 u8 mac_addr[ETH_ALEN]; /* 0x107 */59};60 61struct rtw8723xs_efuse {62 u8 res4[0x4a]; /* 0xd0 */63 u8 mac_addr[ETH_ALEN]; /* 0x11a */64};65 66struct rtw8723x_efuse {67 __le16 rtl_id;68 u8 rsvd[2];69 u8 afe;70 u8 rsvd1[11];71 72 /* power index for four RF paths */73 struct rtw_txpwr_idx txpwr_idx_table[4];74 75 u8 channel_plan; /* 0xb8 */76 u8 xtal_k;77 u8 thermal_meter;78 u8 iqk_lck;79 u8 pa_type; /* 0xbc */80 u8 lna_type_2g[2]; /* 0xbd */81 u8 lna_type_5g[2];82 u8 rf_board_option;83 u8 rf_feature_option;84 u8 rf_bt_setting;85 u8 eeprom_version;86 u8 eeprom_customer_id;87 u8 tx_bb_swing_setting_2g;88 u8 res_c7;89 u8 tx_pwr_calibrate_rate;90 u8 rf_antenna_option; /* 0xc9 */91 u8 rfe_option;92 u8 country_code[2];93 u8 res[3];94 union {95 struct rtw8723xe_efuse e;96 struct rtw8723xu_efuse u;97 struct rtw8723xs_efuse s;98 };99};100 101#define RTW8723X_IQK_ADDA_REG_NUM 16102#define RTW8723X_IQK_MAC8_REG_NUM 3103#define RTW8723X_IQK_MAC32_REG_NUM 1104#define RTW8723X_IQK_BB_REG_NUM 9105 106struct rtw8723x_iqk_backup_regs {107 u32 adda[RTW8723X_IQK_ADDA_REG_NUM];108 u8 mac8[RTW8723X_IQK_MAC8_REG_NUM];109 u32 mac32[RTW8723X_IQK_MAC32_REG_NUM];110 u32 bb[RTW8723X_IQK_BB_REG_NUM];111 112 u32 lte_path;113 u32 lte_gnt;114 115 u32 bb_sel_btg;116 u8 btg_sel;117 118 u8 igia;119 u8 igib;120};121 122struct rtw8723x_common {123 /* registers that must be backed up before IQK and restored after */124 u32 iqk_adda_regs[RTW8723X_IQK_ADDA_REG_NUM];125 u32 iqk_mac8_regs[RTW8723X_IQK_MAC8_REG_NUM];126 u32 iqk_mac32_regs[RTW8723X_IQK_MAC32_REG_NUM];127 u32 iqk_bb_regs[RTW8723X_IQK_BB_REG_NUM];128 129 /* chip register definitions */130 struct rtw_ltecoex_addr ltecoex_addr;131 struct rtw_rf_sipi_addr rf_sipi_addr[2];132 struct rtw_hw_reg dig[2];133 struct rtw_hw_reg dig_cck[1];134 struct rtw_prioq_addrs prioq_addrs;135 136 /* common functions */137 void (*lck)(struct rtw_dev *rtwdev);138 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *log_map);139 int (*mac_init)(struct rtw_dev *rtwdev);140 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable);141 void (*set_tx_power_index)(struct rtw_dev *rtwdev);142 void (*efuse_grant)(struct rtw_dev *rtwdev, bool on);143 void (*false_alarm_statistics)(struct rtw_dev *rtwdev);144 void (*iqk_backup_regs)(struct rtw_dev *rtwdev,145 struct rtw8723x_iqk_backup_regs *backup);146 void (*iqk_restore_regs)(struct rtw_dev *rtwdev,147 const struct rtw8723x_iqk_backup_regs *backup);148 bool (*iqk_similarity_cmp)(struct rtw_dev *rtwdev, s32 result[][IQK_NR],149 u8 c1, u8 c2);150 u8 (*pwrtrack_get_limit_ofdm)(struct rtw_dev *rtwdev);151 void (*pwrtrack_set_xtal)(struct rtw_dev *rtwdev, u8 therm_path,152 u8 delta);153 void (*coex_cfg_init)(struct rtw_dev *rtwdev);154 void (*fill_txdesc_checksum)(struct rtw_dev *rtwdev,155 struct rtw_tx_pkt_info *pkt_info,156 u8 *txdesc);157 void (*debug_txpwr_limit)(struct rtw_dev *rtwdev,158 struct rtw_txpwr_idx *table,159 int tx_path_count);160};161 162extern const struct rtw8723x_common rtw8723x_common;163 164#define PATH_IQK_RETRY 2165#define MAX_TOLERANCE 5166#define IQK_TX_X_ERR 0x142167#define IQK_TX_Y_ERR 0x42168#define IQK_RX_X_ERR 0x132169#define IQK_RX_Y_ERR 0x36170#define IQK_RX_X_UPPER 0x11a171#define IQK_RX_X_LOWER 0xe6172#define IQK_RX_Y_LMT 0x1a173#define IQK_TX_OK BIT(0)174#define IQK_RX_OK BIT(1)175 176#define WLAN_TXQ_RPT_EN 0x1F177 178#define SPUR_THRES 0x16179#define DIS_3WIRE 0xccf000c0180#define EN_3WIRE 0xccc000c0181#define START_PSD 0x400000182#define FREQ_CH5 0xfccd183#define FREQ_CH6 0xfc4d184#define FREQ_CH7 0xffcd185#define FREQ_CH8 0xff4d186#define FREQ_CH13 0xfccd187#define FREQ_CH14 0xff9a188#define RFCFGCH_CHANNEL_MASK GENMASK(7, 0)189#define RFCFGCH_BW_MASK (BIT(11) | BIT(10))190#define RFCFGCH_BW_20M (BIT(11) | BIT(10))191#define RFCFGCH_BW_40M BIT(10)192#define BIT_MASK_RFMOD BIT(0)193#define BIT_LCK BIT(15)194 195#define REG_GPIO_INTM 0x0048196#define REG_BTG_SEL 0x0067197#define BIT_MASK_BTG_WL BIT(7)198#define REG_LTECOEX_PATH_CONTROL 0x0070199#define REG_LTECOEX_CTRL 0x07c0200#define REG_LTECOEX_WRITE_DATA 0x07c4201#define REG_LTECOEX_READ_DATA 0x07c8202#define REG_PSDFN 0x0808203#define REG_BB_PWR_SAV1_11N 0x0874204#define REG_ANA_PARAM1 0x0880205#define REG_ANALOG_P4 0x088c206#define REG_PSDRPT 0x08b4207#define REG_FPGA1_RFMOD 0x0900208#define REG_BB_SEL_BTG 0x0948209#define REG_BBRX_DFIR 0x0954210#define BIT_MASK_RXBB_DFIR GENMASK(27, 24)211#define BIT_RXBB_DFIR_EN BIT(19)212#define REG_CCK0_SYS 0x0a00213#define BIT_CCK_SIDE_BAND BIT(4)214#define REG_CCK_ANT_SEL_11N 0x0a04215#define REG_PWRTH 0x0a08216#define REG_CCK_FA_RST_11N 0x0a2c217#define BIT_MASK_CCK_CNT_KEEP BIT(12)218#define BIT_MASK_CCK_CNT_EN BIT(13)219#define BIT_MASK_CCK_CNT_KPEN (BIT_MASK_CCK_CNT_KEEP | BIT_MASK_CCK_CNT_EN)220#define BIT_MASK_CCK_FA_KEEP BIT(14)221#define BIT_MASK_CCK_FA_EN BIT(15)222#define BIT_MASK_CCK_FA_KPEN (BIT_MASK_CCK_FA_KEEP | BIT_MASK_CCK_FA_EN)223#define REG_CCK_FA_LSB_11N 0x0a5c224#define REG_CCK_FA_MSB_11N 0x0a58225#define REG_CCK_CCA_CNT_11N 0x0a60226#define BIT_MASK_CCK_FA_MSB GENMASK(7, 0)227#define BIT_MASK_CCK_FA_LSB GENMASK(15, 8)228#define REG_PWRTH2 0x0aa8229#define REG_CSRATIO 0x0aaa230#define REG_OFDM_FA_HOLDC_11N 0x0c00231#define BIT_MASK_OFDM_FA_KEEP BIT(31)232#define REG_BB_RX_PATH_11N 0x0c04233#define REG_TRMUX_11N 0x0c08234#define REG_OFDM_FA_RSTC_11N 0x0c0c235#define BIT_MASK_OFDM_FA_RST BIT(31)236#define REG_A_RXIQI 0x0c14237#define BIT_MASK_RXIQ_S1_X 0x000003FF238#define BIT_MASK_RXIQ_S1_Y1 0x0000FC00239#define BIT_SET_RXIQ_S1_Y1(y) ((y) & 0x3F)240#define REG_OFDM0_RXDSP 0x0c40241#define BIT_MASK_RXDSP GENMASK(28, 24)242#define BIT_EN_RXDSP BIT(9)243#define REG_OFDM_0_ECCA_THRESHOLD 0x0c4c244#define BIT_MASK_OFDM0_EXT_A BIT(31)245#define BIT_MASK_OFDM0_EXT_C BIT(29)246#define BIT_MASK_OFDM0_EXTS (BIT(31) | BIT(29) | BIT(28))247#define BIT_SET_OFDM0_EXTS(a, c, d) (((a) << 31) | ((c) << 29) | ((d) << 28))248#define BIT_MASK_OFDM0_EXTS_B (BIT(27) | BIT(25) | BIT(24))249#define BIT_SET_OFDM0_EXTS_B(a, c, d) (((a) << 27) | ((c) << 25) | ((d) << 24))250#define REG_OFDM0_XAAGC1 0x0c50251#define REG_OFDM0_XBAGC1 0x0c58252#define REG_AGCRSSI 0x0c78253#define REG_OFDM_0_XA_TX_IQ_IMBALANCE 0x0c80254#define REG_OFDM_0_XB_TX_IQ_IMBALANCE 0x0c88255#define BIT_MASK_TXIQ_ELM_A 0x03ff256#define BIT_SET_TXIQ_ELM_ACD(a, c, d) (((d) << 22) | (((c) & 0x3F) << 16) | \257 ((a) & 0x03ff))258#define BIT_MASK_TXIQ_ELM_C GENMASK(21, 16)259#define BIT_SET_TXIQ_ELM_C2(c) ((c) & 0x3F)260#define BIT_MASK_TXIQ_ELM_D GENMASK(31, 22)261#define REG_TXIQK_MATRIXA_LSB2_11N 0x0c94262#define BIT_SET_TXIQ_ELM_C1(c) (((c) & 0x000003C0) >> 6)263#define REG_RXIQK_MATRIX_LSB_11N 0x0ca0264#define BIT_MASK_RXIQ_S1_Y2 0xF0000000265#define BIT_SET_RXIQ_S1_Y2(y) (((y) >> 6) & 0xF)266#define REG_TXIQ_AB_S0 0x0cd0267#define BIT_MASK_TXIQ_A_S0 0x000007FE268#define BIT_MASK_TXIQ_A_EXT_S0 BIT(0)269#define BIT_MASK_TXIQ_B_S0 0x0007E000270#define REG_TXIQ_CD_S0 0x0cd4271#define BIT_MASK_TXIQ_C_S0 0x000007FE272#define BIT_MASK_TXIQ_C_EXT_S0 BIT(0)273#define BIT_MASK_TXIQ_D_S0 GENMASK(22, 13)274#define BIT_MASK_TXIQ_D_EXT_S0 BIT(12)275#define REG_RXIQ_AB_S0 0x0cd8276#define BIT_MASK_RXIQ_X_S0 0x000003FF277#define BIT_MASK_RXIQ_Y_S0 0x003FF000278#define REG_OFDM_FA_TYPE1_11N 0x0cf0279#define BIT_MASK_OFDM_FF_CNT GENMASK(15, 0)280#define BIT_MASK_OFDM_SF_CNT GENMASK(31, 16)281#define REG_OFDM_FA_RSTD_11N 0x0d00282#define BIT_MASK_OFDM_FA_RST1 BIT(27)283#define BIT_MASK_OFDM_FA_KEEP1 BIT(31)284#define REG_CTX 0x0d03285#define BIT_MASK_CTX_TYPE GENMASK(6, 4)286#define REG_OFDM1_CFOTRK 0x0d2c287#define BIT_EN_CFOTRK BIT(28)288#define REG_OFDM1_CSI1 0x0d40289#define REG_OFDM1_CSI2 0x0d44290#define REG_OFDM1_CSI3 0x0d48291#define REG_OFDM1_CSI4 0x0d4c292#define REG_OFDM_FA_TYPE2_11N 0x0da0293#define BIT_MASK_OFDM_CCA_CNT GENMASK(15, 0)294#define BIT_MASK_OFDM_PF_CNT GENMASK(31, 16)295#define REG_OFDM_FA_TYPE3_11N 0x0da4296#define BIT_MASK_OFDM_RI_CNT GENMASK(15, 0)297#define BIT_MASK_OFDM_CRC_CNT GENMASK(31, 16)298#define REG_OFDM_FA_TYPE4_11N 0x0da8299#define BIT_MASK_OFDM_MNS_CNT GENMASK(15, 0)300#define REG_FPGA0_IQK_11N 0x0e28301#define BIT_MASK_IQK_MOD 0xffffff00302#define EN_IQK 0x808000303#define RST_IQK 0x000000304#define REG_TXIQK_TONE_A_11N 0x0e30305#define REG_RXIQK_TONE_A_11N 0x0e34306#define REG_TXIQK_PI_A_11N 0x0e38307#define REG_RXIQK_PI_A_11N 0x0e3c308#define REG_TXIQK_11N 0x0e40309#define BIT_SET_TXIQK_11N(x, y) (0x80007C00 | ((x) << 16) | (y))310#define REG_RXIQK_11N 0x0e44311#define REG_IQK_AGC_PTS_11N 0x0e48312#define REG_IQK_AGC_RSP_11N 0x0e4c313#define REG_TX_IQK_TONE_B 0x0e50314#define REG_RX_IQK_TONE_B 0x0e54315#define REG_TXIQK_PI_B 0x0e58316#define REG_RXIQK_PI_B 0x0e5c317#define REG_IQK_RES_TX 0x0e94318#define BIT_MASK_RES_TX GENMASK(25, 16)319#define REG_IQK_RES_TY 0x0e9c320#define BIT_MASK_RES_TY GENMASK(25, 16)321#define REG_IQK_RES_RX 0x0ea4322#define BIT_MASK_RES_RX GENMASK(25, 16)323#define REG_IQK_RES_RY 0x0eac324#define BIT_IQK_TX_FAIL BIT(28)325#define BIT_IQK_RX_FAIL BIT(27)326#define BIT_IQK_DONE BIT(26)327#define BIT_MASK_RES_RY GENMASK(25, 16)328#define REG_PAGE_F_RST_11N 0x0f14329#define BIT_MASK_F_RST_ALL BIT(16)330#define REG_IGI_C_11N 0x0f84331#define REG_IGI_D_11N 0x0f88332#define REG_HT_CRC32_CNT_11N 0x0f90333#define BIT_MASK_HT_CRC_OK GENMASK(15, 0)334#define BIT_MASK_HT_CRC_ERR GENMASK(31, 16)335#define REG_OFDM_CRC32_CNT_11N 0x0f94336#define BIT_MASK_OFDM_LCRC_OK GENMASK(15, 0)337#define BIT_MASK_OFDM_LCRC_ERR GENMASK(31, 16)338#define REG_HT_CRC32_CNT_11N_AGG 0x0fb8339 340#define OFDM_SWING_A(swing) FIELD_GET(GENMASK(9, 0), swing)341#define OFDM_SWING_B(swing) FIELD_GET(GENMASK(15, 10), swing)342#define OFDM_SWING_C(swing) FIELD_GET(GENMASK(21, 16), swing)343#define OFDM_SWING_D(swing) FIELD_GET(GENMASK(31, 22), swing)344 345static inline s32 iqkxy_to_s32(s32 val)346{347 /* val is Q10.8 */348 return sign_extend32(val, 9);349}350 351static inline s32 iqk_mult(s32 x, s32 y, s32 *ext)352{353 /* x, y and return value are Q10.8 */354 s32 t;355 356 t = x * y;357 if (ext)358 *ext = (t >> 7) & 0x1; /* Q.16 --> Q.9; get LSB of Q.9 */359 360 return (t >> 8); /* Q.16 --> Q.8 */361}362 363static inline364void rtw8723x_debug_txpwr_limit(struct rtw_dev *rtwdev,365 struct rtw_txpwr_idx *table,366 int tx_path_count)367{368 rtw8723x_common.debug_txpwr_limit(rtwdev, table, tx_path_count);369}370 371static inline void rtw8723x_lck(struct rtw_dev *rtwdev)372{373 rtw8723x_common.lck(rtwdev);374}375 376static inline int rtw8723x_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)377{378 return rtw8723x_common.read_efuse(rtwdev, log_map);379}380 381static inline int rtw8723x_mac_init(struct rtw_dev *rtwdev)382{383 return rtw8723x_common.mac_init(rtwdev);384}385 386static inline void rtw8723x_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)387{388 rtw8723x_common.cfg_ldo25(rtwdev, enable);389}390 391static inline void rtw8723x_set_tx_power_index(struct rtw_dev *rtwdev)392{393 rtw8723x_common.set_tx_power_index(rtwdev);394}395 396static inline void rtw8723x_efuse_grant(struct rtw_dev *rtwdev, bool on)397{398 rtw8723x_common.efuse_grant(rtwdev, on);399}400 401static inline void rtw8723x_false_alarm_statistics(struct rtw_dev *rtwdev)402{403 rtw8723x_common.false_alarm_statistics(rtwdev);404}405 406static inline407void rtw8723x_iqk_backup_regs(struct rtw_dev *rtwdev,408 struct rtw8723x_iqk_backup_regs *backup)409{410 rtw8723x_common.iqk_backup_regs(rtwdev, backup);411}412 413static inline414void rtw8723x_iqk_restore_regs(struct rtw_dev *rtwdev,415 const struct rtw8723x_iqk_backup_regs *backup)416{417 rtw8723x_common.iqk_restore_regs(rtwdev, backup);418}419 420static inline421bool rtw8723x_iqk_similarity_cmp(struct rtw_dev *rtwdev, s32 result[][IQK_NR],422 u8 c1, u8 c2)423{424 return rtw8723x_common.iqk_similarity_cmp(rtwdev, result, c1, c2);425}426 427static inline u8 rtw8723x_pwrtrack_get_limit_ofdm(struct rtw_dev *rtwdev)428{429 return rtw8723x_common.pwrtrack_get_limit_ofdm(rtwdev);430}431 432static inline433void rtw8723x_pwrtrack_set_xtal(struct rtw_dev *rtwdev, u8 therm_path,434 u8 delta)435{436 rtw8723x_common.pwrtrack_set_xtal(rtwdev, therm_path, delta);437}438 439static inline void rtw8723x_coex_cfg_init(struct rtw_dev *rtwdev)440{441 rtw8723x_common.coex_cfg_init(rtwdev);442}443 444static inline445void rtw8723x_fill_txdesc_checksum(struct rtw_dev *rtwdev,446 struct rtw_tx_pkt_info *pkt_info,447 u8 *txdesc)448{449 rtw8723x_common.fill_txdesc_checksum(rtwdev, pkt_info, txdesc);450}451 452/* IQK helper functions, defined as inline so they can be shared453 * without needing an EXPORT_SYMBOL each.454 */455static inline void456rtw8723x_iqk_backup_path_ctrl(struct rtw_dev *rtwdev,457 struct rtw8723x_iqk_backup_regs *backup)458{459 backup->btg_sel = rtw_read8(rtwdev, REG_BTG_SEL);460 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] original 0x67 = 0x%x\n",461 backup->btg_sel);462}463 464static inline void rtw8723x_iqk_config_path_ctrl(struct rtw_dev *rtwdev)465{466 rtw_write32_mask(rtwdev, REG_PAD_CTRL1, BIT_BT_BTG_SEL, 0x1);467 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] set 0x67 = 0x%x\n",468 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));469}470 471static inline void472rtw8723x_iqk_restore_path_ctrl(struct rtw_dev *rtwdev,473 const struct rtw8723x_iqk_backup_regs *backup)474{475 rtw_write8(rtwdev, REG_BTG_SEL, backup->btg_sel);476 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] restore 0x67 = 0x%x\n",477 rtw_read32_mask(rtwdev, REG_PAD_CTRL1, MASKBYTE3));478}479 480static inline void481rtw8723x_iqk_backup_lte_path_gnt(struct rtw_dev *rtwdev,482 struct rtw8723x_iqk_backup_regs *backup)483{484 backup->lte_path = rtw_read32(rtwdev, REG_LTECOEX_PATH_CONTROL);485 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0x800f0038);486 mdelay(1);487 backup->lte_gnt = rtw_read32(rtwdev, REG_LTECOEX_READ_DATA);488 rtw_dbg(rtwdev, RTW_DBG_RFK, "[IQK] OriginalGNT = 0x%x\n",489 backup->lte_gnt);490}491 492static inline void493rtw8723x_iqk_config_lte_path_gnt(struct rtw_dev *rtwdev,494 u32 write_data)495{496 rtw_write32(rtwdev, REG_LTECOEX_WRITE_DATA, write_data);497 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc0020038);498 rtw_write32_mask(rtwdev, REG_LTECOEX_PATH_CONTROL,499 BIT_LTE_MUX_CTRL_PATH, 0x1);500}501 502static inline void503rtw8723x_iqk_restore_lte_path_gnt(struct rtw_dev *rtwdev,504 const struct rtw8723x_iqk_backup_regs *bak)505{506 rtw_write32(rtwdev, REG_LTECOEX_WRITE_DATA, bak->lte_gnt);507 rtw_write32(rtwdev, REG_LTECOEX_CTRL, 0xc00f0038);508 rtw_write32(rtwdev, REG_LTECOEX_PATH_CONTROL, bak->lte_path);509}510 511/* set all ADDA registers to the given value */512static inline void rtw8723x_iqk_path_adda_on(struct rtw_dev *rtwdev, u32 value)513{514 for (int i = 0; i < RTW8723X_IQK_ADDA_REG_NUM; i++)515 rtw_write32(rtwdev, rtw8723x_common.iqk_adda_regs[i], value);516}517 518#endif /* __RTW8723X_H__ */519