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1// SPDX-License-Identifier: GPL-2.02/*3 * STM32 Factory-programmed memory read access driver4 *5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com> for STMicroelectronics.7 */8 9#include <linux/arm-smccc.h>10#include <linux/io.h>11#include <linux/module.h>12#include <linux/nvmem-provider.h>13#include <linux/of.h>14#include <linux/platform_device.h>15#include <linux/property.h>16#include <linux/tee_drv.h>17 18#include "stm32-bsec-optee-ta.h"19 20/* BSEC secure service access from non-secure */21#define STM32_SMC_BSEC 0x8200100322#define STM32_SMC_READ_SHADOW 0x0123#define STM32_SMC_PROG_OTP 0x0224#define STM32_SMC_WRITE_SHADOW 0x0325#define STM32_SMC_READ_OTP 0x0426 27/* shadow registers offset */28#define STM32MP15_BSEC_DATA0 0x20029 30struct stm32_romem_cfg {31 int size;32 u8 lower;33 bool ta;34};35 36struct stm32_romem_priv {37 void __iomem *base;38 struct nvmem_config cfg;39 u8 lower;40 struct tee_context *ctx;41};42 43static int stm32_romem_read(void *context, unsigned int offset, void *buf,44 size_t bytes)45{46 struct stm32_romem_priv *priv = context;47 u8 *buf8 = buf;48 int i;49 50 for (i = offset; i < offset + bytes; i++)51 *buf8++ = readb_relaxed(priv->base + i);52 53 return 0;54}55 56static int stm32_bsec_smc(u8 op, u32 otp, u32 data, u32 *result)57{58#if IS_ENABLED(CONFIG_HAVE_ARM_SMCCC)59 struct arm_smccc_res res;60 61 arm_smccc_smc(STM32_SMC_BSEC, op, otp, data, 0, 0, 0, 0, &res);62 if (res.a0)63 return -EIO;64 65 if (result)66 *result = (u32)res.a1;67 68 return 0;69#else70 return -ENXIO;71#endif72}73 74static int stm32_bsec_read(void *context, unsigned int offset, void *buf,75 size_t bytes)76{77 struct stm32_romem_priv *priv = context;78 struct device *dev = priv->cfg.dev;79 u32 roffset, rbytes, val;80 u8 *buf8 = buf, *val8 = (u8 *)&val;81 int i, j = 0, ret, skip_bytes, size;82 83 /* Round unaligned access to 32-bits */84 roffset = rounddown(offset, 4);85 skip_bytes = offset & 0x3;86 rbytes = roundup(bytes + skip_bytes, 4);87 88 if (roffset + rbytes > priv->cfg.size)89 return -EINVAL;90 91 for (i = roffset; (i < roffset + rbytes); i += 4) {92 u32 otp = i >> 2;93 94 if (otp < priv->lower) {95 /* read lower data from shadow registers */96 val = readl_relaxed(97 priv->base + STM32MP15_BSEC_DATA0 + i);98 } else {99 ret = stm32_bsec_smc(STM32_SMC_READ_SHADOW, otp, 0,100 &val);101 if (ret) {102 dev_err(dev, "Can't read data%d (%d)\n", otp,103 ret);104 return ret;105 }106 }107 /* skip first bytes in case of unaligned read */108 if (skip_bytes)109 size = min(bytes, (size_t)(4 - skip_bytes));110 else111 size = min(bytes, (size_t)4);112 memcpy(&buf8[j], &val8[skip_bytes], size);113 bytes -= size;114 j += size;115 skip_bytes = 0;116 }117 118 return 0;119}120 121static int stm32_bsec_write(void *context, unsigned int offset, void *buf,122 size_t bytes)123{124 struct stm32_romem_priv *priv = context;125 struct device *dev = priv->cfg.dev;126 u32 *buf32 = buf;127 int ret, i;128 129 /* Allow only writing complete 32-bits aligned words */130 if ((bytes % 4) || (offset % 4))131 return -EINVAL;132 133 for (i = offset; i < offset + bytes; i += 4) {134 ret = stm32_bsec_smc(STM32_SMC_PROG_OTP, i >> 2, *buf32++,135 NULL);136 if (ret) {137 dev_err(dev, "Can't write data%d (%d)\n", i >> 2, ret);138 return ret;139 }140 }141 142 if (offset + bytes >= priv->lower * 4)143 dev_warn(dev, "Update of upper OTPs with ECC protection (word programming, only once)\n");144 145 return 0;146}147 148static int stm32_bsec_pta_read(void *context, unsigned int offset, void *buf,149 size_t bytes)150{151 struct stm32_romem_priv *priv = context;152 153 return stm32_bsec_optee_ta_read(priv->ctx, offset, buf, bytes);154}155 156static int stm32_bsec_pta_write(void *context, unsigned int offset, void *buf,157 size_t bytes)158{159 struct stm32_romem_priv *priv = context;160 161 return stm32_bsec_optee_ta_write(priv->ctx, priv->lower, offset, buf, bytes);162}163 164static bool stm32_bsec_smc_check(void)165{166 u32 val;167 int ret;168 169 /* check that the OP-TEE support the BSEC SMC (legacy mode) */170 ret = stm32_bsec_smc(STM32_SMC_READ_SHADOW, 0, 0, &val);171 172 return !ret;173}174 175static bool optee_presence_check(void)176{177 struct device_node *np;178 bool tee_detected = false;179 180 /* check that the OP-TEE node is present and available. */181 np = of_find_compatible_node(NULL, NULL, "linaro,optee-tz");182 if (np && of_device_is_available(np))183 tee_detected = true;184 of_node_put(np);185 186 return tee_detected;187}188 189static int stm32_romem_probe(struct platform_device *pdev)190{191 const struct stm32_romem_cfg *cfg;192 struct device *dev = &pdev->dev;193 struct stm32_romem_priv *priv;194 struct resource *res;195 int rc;196 197 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);198 if (!priv)199 return -ENOMEM;200 201 priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);202 if (IS_ERR(priv->base))203 return PTR_ERR(priv->base);204 205 priv->cfg.name = "stm32-romem";206 priv->cfg.word_size = 1;207 priv->cfg.stride = 1;208 priv->cfg.dev = dev;209 priv->cfg.priv = priv;210 priv->cfg.owner = THIS_MODULE;211 priv->cfg.type = NVMEM_TYPE_OTP;212 priv->cfg.add_legacy_fixed_of_cells = true;213 214 priv->lower = 0;215 216 cfg = device_get_match_data(dev);217 if (!cfg) {218 priv->cfg.read_only = true;219 priv->cfg.size = resource_size(res);220 priv->cfg.reg_read = stm32_romem_read;221 } else {222 priv->cfg.size = cfg->size;223 priv->lower = cfg->lower;224 if (cfg->ta || optee_presence_check()) {225 rc = stm32_bsec_optee_ta_open(&priv->ctx);226 if (rc) {227 /* wait for OP-TEE client driver to be up and ready */228 if (rc == -EPROBE_DEFER)229 return -EPROBE_DEFER;230 /* BSEC PTA is required or SMC not supported */231 if (cfg->ta || !stm32_bsec_smc_check())232 return rc;233 }234 }235 if (priv->ctx) {236 rc = devm_add_action_or_reset(dev, stm32_bsec_optee_ta_close, priv->ctx);237 if (rc) {238 dev_err(dev, "devm_add_action_or_reset() failed (%d)\n", rc);239 return rc;240 }241 priv->cfg.reg_read = stm32_bsec_pta_read;242 priv->cfg.reg_write = stm32_bsec_pta_write;243 } else {244 priv->cfg.reg_read = stm32_bsec_read;245 priv->cfg.reg_write = stm32_bsec_write;246 }247 }248 249 return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &priv->cfg));250}251 252/*253 * STM32MP15/13 BSEC OTP regions: 4096 OTP bits (with 3072 effective bits)254 * => 96 x 32-bits data words255 * - Lower: 1K bits, 2:1 redundancy, incremental bit programming256 * => 32 (x 32-bits) lower shadow registers = words 0 to 31257 * - Upper: 2K bits, ECC protection, word programming only258 * => 64 (x 32-bits) = words 32 to 95259 */260static const struct stm32_romem_cfg stm32mp15_bsec_cfg = {261 .size = 384,262 .lower = 32,263 .ta = false,264};265 266static const struct stm32_romem_cfg stm32mp13_bsec_cfg = {267 .size = 384,268 .lower = 32,269 .ta = true,270};271 272/*273 * STM32MP25 BSEC OTP: 3 regions of 32-bits data words274 * lower OTP (OTP0 to OTP127), bitwise (1-bit) programmable275 * mid OTP (OTP128 to OTP255), bulk (32-bit) programmable276 * upper OTP (OTP256 to OTP383), bulk (32-bit) programmable277 * but no access to HWKEY and ECIES key: limited at OTP367278 */279static const struct stm32_romem_cfg stm32mp25_bsec_cfg = {280 .size = 368 * 4,281 .lower = 127,282 .ta = true,283};284 285static const struct of_device_id stm32_romem_of_match[] __maybe_unused = {286 { .compatible = "st,stm32f4-otp", }, {287 .compatible = "st,stm32mp15-bsec",288 .data = (void *)&stm32mp15_bsec_cfg,289 }, {290 .compatible = "st,stm32mp13-bsec",291 .data = (void *)&stm32mp13_bsec_cfg,292 }, {293 .compatible = "st,stm32mp25-bsec",294 .data = (void *)&stm32mp25_bsec_cfg,295 },296 { /* sentinel */ },297};298MODULE_DEVICE_TABLE(of, stm32_romem_of_match);299 300static struct platform_driver stm32_romem_driver = {301 .probe = stm32_romem_probe,302 .driver = {303 .name = "stm32-romem",304 .of_match_table = of_match_ptr(stm32_romem_of_match),305 },306};307module_platform_driver(stm32_romem_driver);308 309MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");310MODULE_DESCRIPTION("STMicroelectronics STM32 RO-MEM");311MODULE_ALIAS("platform:nvmem-stm32-romem");312MODULE_LICENSE("GPL v2");313