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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/* 3 * Private structs/constants for PARISC IOSAPIC support4 *5 * Copyright (C) 2000 Hewlett Packard (Grant Grundler)6 * Copyright (C) 2000,2003 Grant Grundler (grundler at parisc-linux.org)7 * Copyright (C) 2002 Matthew Wilcox (willy at parisc-linux.org)8 */9 10/*11** This file is private to iosapic driver.12** If stuff needs to be used by another driver, move it to a common file.13**14** WARNING: fields most data structures here are ordered to make sure15** they pack nicely for 64-bit compilation. (ie sizeof(long) == 8)16*/17 18 19/*20** Interrupt Routing Stuff21** -----------------------22** The interrupt routing table consists of entries derived from23** MP Specification Draft 1.5. There is one interrupt routing 24** table per cell. N- and L-class consist of a single cell.25*/26struct irt_entry {27 28 /* Entry Type 139 identifies an I/O SAPIC interrupt entry */29 u8 entry_type;30 31 /* Entry Length 16 indicates entry is 16 bytes long */32 u8 entry_length;33 34 /* 35 ** Interrupt Type of 0 indicates a vectored interrupt, 36 ** all other values are reserved 37 */38 u8 interrupt_type;39 40 /* 41 ** PO and EL42 ** Polarity of SAPIC I/O input signals: 43 ** 00 = Reserved 44 ** 01 = Active high 45 ** 10 = Reserved 46 ** 11 = Active low 47 ** Trigger mode of SAPIC I/O input signals: 48 ** 00 = Reserved 49 ** 01 = Edge-triggered 50 ** 10 = Reserved 51 ** 11 = Level-triggered52 */53 u8 polarity_trigger;54 55 /* 56 ** IRQ and DEVNO57 ** irq identifies PCI interrupt signal where58 ** 0x0 corresponds to INT_A#, 59 ** 0x1 corresponds to INT_B#, 60 ** 0x2 corresponds to INT_C# 61 ** 0x3 corresponds to INT_D# 62 ** PCI device number where interrupt originates 63 */64 u8 src_bus_irq_devno;65 66 /* Source Bus ID identifies the bus where interrupt signal comes from */67 u8 src_bus_id;68 69 /* 70 ** Segment ID is unique across a protection domain and71 ** identifies a segment of PCI buses (reserved in 72 ** MP Specification Draft 1.5) 73 */74 u8 src_seg_id;75 76 /* 77 ** Destination I/O SAPIC INTIN# identifies the INTIN n pin 78 ** to which the signal is connected 79 */80 u8 dest_iosapic_intin;81 82 /* 83 ** Destination I/O SAPIC Address identifies the I/O SAPIC 84 ** to which the signal is connected 85 */86 u64 dest_iosapic_addr;87};88 89#define IRT_IOSAPIC_TYPE 13990#define IRT_IOSAPIC_LENGTH 1691 92#define IRT_VECTORED_INTR 093 94#define IRT_PO_MASK 0x395#define IRT_ACTIVE_HI 196#define IRT_ACTIVE_LO 397 98#define IRT_EL_MASK 0x399#define IRT_EL_SHIFT 2100#define IRT_EDGE_TRIG 1101#define IRT_LEVEL_TRIG 3102 103#define IRT_IRQ_MASK 0x3104#define IRT_DEV_MASK 0x1f105#define IRT_DEV_SHIFT 2106 107#define IRT_IRQ_DEVNO_MASK ((IRT_DEV_MASK << IRT_DEV_SHIFT) | IRT_IRQ_MASK)108 109#ifdef SUPPORT_MULTI_CELL110struct iosapic_irt {111 struct iosapic_irt *irt_next; /* next routing table */112 struct irt_entry *irt_base; /* intr routing table address */113 size_t irte_count; /* number of entries in the table */114 size_t irte_size; /* size (bytes) of each entry */115};116#endif117 118struct vector_info {119 struct iosapic_info *iosapic; /* I/O SAPIC this vector is on */120 struct irt_entry *irte; /* IRT entry */121 __le32 __iomem *eoi_addr; /* precalculate EOI reg address */122 __le32 eoi_data; /* IA64: ? PA: swapped txn_data */123 int txn_irq; /* virtual IRQ number for processor */124 ulong txn_addr; /* IA64: id_eid PA: partial HPA */125 u32 txn_data; /* CPU interrupt bit */126 u8 status; /* status/flags */127 u8 irqline; /* INTINn(IRQ) */128};129 130 131struct iosapic_info {132 struct iosapic_info * isi_next; /* list of I/O SAPIC */133 void __iomem * addr; /* remapped address */134 unsigned long isi_hpa; /* physical base address */135 struct vector_info * isi_vector; /* IRdT (IRQ line) array */136 int isi_num_vectors; /* size of IRdT array */137 int isi_status; /* status/flags */138 unsigned int isi_version; /* DEBUG: data fr version reg */139};140 141 142 143#ifdef __IA64__144/*145** PA risc does NOT have any local sapics. IA64 does.146** PIB (Processor Interrupt Block) is handled by Astro or Dew (Stretch CEC).147**148** PA: Get id_eid from IRT and hardcode PIB to 0xfeeNNNN0149** Emulate the data on PAT platforms.150*/151struct local_sapic_info {152 struct local_sapic_info *lsi_next; /* point to next CPU info */153 int *lsi_cpu_id; /* point to logical CPU id */154 unsigned long *lsi_id_eid; /* point to IA-64 CPU id */155 int *lsi_status; /* point to CPU status */156 void *lsi_private; /* point to special info */157};158 159/*160** "root" data structure which ties everything together.161** Should always be able to start with sapic_root and locate162** the desired information.163*/164struct sapic_info {165 struct sapic_info *si_next; /* info is per cell */166 int si_cellid; /* cell id */167 unsigned int si_status; /* status */168 char *si_pib_base; /* intr blk base address */169 local_sapic_info_t *si_local_info;170 io_sapic_info_t *si_io_info;171 extint_info_t *si_extint_info;/* External Intr info */172};173#endif174 175