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1// SPDX-License-Identifier: GPL-2.02/*3 * pci-j721e - PCIe controller driver for TI's J721E SoCs4 *5 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com6 * Author: Kishon Vijay Abraham I <kishon@ti.com>7 */8 9#include <linux/clk.h>10#include <linux/clk-provider.h>11#include <linux/container_of.h>12#include <linux/delay.h>13#include <linux/gpio/consumer.h>14#include <linux/io.h>15#include <linux/irqchip/chained_irq.h>16#include <linux/irqdomain.h>17#include <linux/mfd/syscon.h>18#include <linux/of.h>19#include <linux/pci.h>20#include <linux/platform_device.h>21#include <linux/pm_runtime.h>22#include <linux/regmap.h>23 24#include "../../pci.h"25#include "pcie-cadence.h"26 27#define cdns_pcie_to_rc(p) container_of(p, struct cdns_pcie_rc, pcie)28 29#define ENABLE_REG_SYS_2 0x10830#define STATUS_REG_SYS_2 0x50831#define STATUS_CLR_REG_SYS_2 0x70832#define LINK_DOWN BIT(1)33#define J7200_LINK_DOWN BIT(10)34 35#define J721E_PCIE_USER_CMD_STATUS 0x436#define LINK_TRAINING_ENABLE BIT(0)37 38#define J721E_PCIE_USER_LINKSTATUS 0x1439#define LINK_STATUS GENMASK(1, 0)40 41enum link_status {42 NO_RECEIVERS_DETECTED,43 LINK_TRAINING_IN_PROGRESS,44 LINK_UP_DL_IN_PROGRESS,45 LINK_UP_DL_COMPLETED,46};47 48#define J721E_MODE_RC BIT(7)49#define LANE_COUNT(n) ((n) << 8)50 51#define ACSPCIE_PAD_DISABLE_MASK GENMASK(1, 0)52#define GENERATION_SEL_MASK GENMASK(1, 0)53 54struct j721e_pcie {55 struct cdns_pcie *cdns_pcie;56 struct clk *refclk;57 u32 mode;58 u32 num_lanes;59 u32 max_lanes;60 struct gpio_desc *reset_gpio;61 void __iomem *user_cfg_base;62 void __iomem *intd_cfg_base;63 u32 linkdown_irq_regfield;64};65 66enum j721e_pcie_mode {67 PCI_MODE_RC,68 PCI_MODE_EP,69};70 71struct j721e_pcie_data {72 enum j721e_pcie_mode mode;73 unsigned int quirk_retrain_flag:1;74 unsigned int quirk_detect_quiet_flag:1;75 unsigned int quirk_disable_flr:1;76 u32 linkdown_irq_regfield;77 unsigned int byte_access_allowed:1;78 unsigned int max_lanes;79};80 81static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset)82{83 return readl(pcie->user_cfg_base + offset);84}85 86static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset,87 u32 value)88{89 writel(value, pcie->user_cfg_base + offset);90}91 92static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset)93{94 return readl(pcie->intd_cfg_base + offset);95}96 97static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset,98 u32 value)99{100 writel(value, pcie->intd_cfg_base + offset);101}102 103static irqreturn_t j721e_pcie_link_irq_handler(int irq, void *priv)104{105 struct j721e_pcie *pcie = priv;106 struct device *dev = pcie->cdns_pcie->dev;107 u32 reg;108 109 reg = j721e_pcie_intd_readl(pcie, STATUS_REG_SYS_2);110 if (!(reg & pcie->linkdown_irq_regfield))111 return IRQ_NONE;112 113 dev_err(dev, "LINK DOWN!\n");114 115 j721e_pcie_intd_writel(pcie, STATUS_CLR_REG_SYS_2, pcie->linkdown_irq_regfield);116 return IRQ_HANDLED;117}118 119static void j721e_pcie_config_link_irq(struct j721e_pcie *pcie)120{121 u32 reg;122 123 reg = j721e_pcie_intd_readl(pcie, ENABLE_REG_SYS_2);124 reg |= pcie->linkdown_irq_regfield;125 j721e_pcie_intd_writel(pcie, ENABLE_REG_SYS_2, reg);126}127 128static int j721e_pcie_start_link(struct cdns_pcie *cdns_pcie)129{130 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);131 u32 reg;132 133 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);134 reg |= LINK_TRAINING_ENABLE;135 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);136 137 return 0;138}139 140static void j721e_pcie_stop_link(struct cdns_pcie *cdns_pcie)141{142 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);143 u32 reg;144 145 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS);146 reg &= ~LINK_TRAINING_ENABLE;147 j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg);148}149 150static bool j721e_pcie_link_up(struct cdns_pcie *cdns_pcie)151{152 struct j721e_pcie *pcie = dev_get_drvdata(cdns_pcie->dev);153 u32 reg;154 155 reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS);156 reg &= LINK_STATUS;157 if (reg == LINK_UP_DL_COMPLETED)158 return true;159 160 return false;161}162 163static const struct cdns_pcie_ops j721e_pcie_ops = {164 .start_link = j721e_pcie_start_link,165 .stop_link = j721e_pcie_stop_link,166 .link_up = j721e_pcie_link_up,167};168 169static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon,170 unsigned int offset)171{172 struct device *dev = pcie->cdns_pcie->dev;173 u32 mask = J721E_MODE_RC;174 u32 mode = pcie->mode;175 u32 val = 0;176 int ret = 0;177 178 if (mode == PCI_MODE_RC)179 val = J721E_MODE_RC;180 181 ret = regmap_update_bits(syscon, offset, mask, val);182 if (ret)183 dev_err(dev, "failed to set pcie mode\n");184 185 return ret;186}187 188static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,189 struct regmap *syscon, unsigned int offset)190{191 struct device *dev = pcie->cdns_pcie->dev;192 struct device_node *np = dev->of_node;193 int link_speed;194 u32 val = 0;195 int ret;196 197 link_speed = of_pci_get_max_link_speed(np);198 if (link_speed < 2)199 link_speed = 2;200 201 val = link_speed - 1;202 ret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val);203 if (ret)204 dev_err(dev, "failed to set link speed\n");205 206 return ret;207}208 209static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,210 struct regmap *syscon, unsigned int offset)211{212 struct device *dev = pcie->cdns_pcie->dev;213 u32 lanes = pcie->num_lanes;214 u32 mask = BIT(8);215 u32 val = 0;216 int ret;217 218 if (pcie->max_lanes == 4)219 mask = GENMASK(9, 8);220 221 val = LANE_COUNT(lanes - 1);222 ret = regmap_update_bits(syscon, offset, mask, val);223 if (ret)224 dev_err(dev, "failed to set link count\n");225 226 return ret;227}228 229static int j721e_enable_acspcie_refclk(struct j721e_pcie *pcie,230 struct regmap *syscon)231{232 struct device *dev = pcie->cdns_pcie->dev;233 struct device_node *node = dev->of_node;234 u32 mask = ACSPCIE_PAD_DISABLE_MASK;235 struct of_phandle_args args;236 u32 val;237 int ret;238 239 ret = of_parse_phandle_with_fixed_args(node,240 "ti,syscon-acspcie-proxy-ctrl",241 1, 0, &args);242 if (ret) {243 dev_err(dev,244 "ti,syscon-acspcie-proxy-ctrl has invalid arguments\n");245 return ret;246 }247 248 /* Clear PAD IO disable bits to enable refclk output */249 val = ~(args.args[0]);250 ret = regmap_update_bits(syscon, 0, mask, val);251 if (ret) {252 dev_err(dev, "failed to enable ACSPCIE refclk: %d\n", ret);253 return ret;254 }255 256 return 0;257}258 259static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie)260{261 struct device *dev = pcie->cdns_pcie->dev;262 struct device_node *node = dev->of_node;263 struct of_phandle_args args;264 unsigned int offset = 0;265 struct regmap *syscon;266 int ret;267 268 syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl");269 if (IS_ERR(syscon)) {270 dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n");271 return PTR_ERR(syscon);272 }273 274 /* Do not error out to maintain old DT compatibility */275 ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-pcie-ctrl", 1,276 0, &args);277 if (!ret)278 offset = args.args[0];279 280 ret = j721e_pcie_set_mode(pcie, syscon, offset);281 if (ret < 0) {282 dev_err(dev, "Failed to set pci mode\n");283 return ret;284 }285 286 ret = j721e_pcie_set_link_speed(pcie, syscon, offset);287 if (ret < 0) {288 dev_err(dev, "Failed to set link speed\n");289 return ret;290 }291 292 ret = j721e_pcie_set_lane_count(pcie, syscon, offset);293 if (ret < 0) {294 dev_err(dev, "Failed to set num-lanes\n");295 return ret;296 }297 298 /* Enable ACSPCIE refclk output if the optional property exists */299 syscon = syscon_regmap_lookup_by_phandle_optional(node,300 "ti,syscon-acspcie-proxy-ctrl");301 if (!syscon)302 return 0;303 304 return j721e_enable_acspcie_refclk(pcie, syscon);305}306 307static int cdns_ti_pcie_config_read(struct pci_bus *bus, unsigned int devfn,308 int where, int size, u32 *value)309{310 if (pci_is_root_bus(bus))311 return pci_generic_config_read32(bus, devfn, where, size,312 value);313 314 return pci_generic_config_read(bus, devfn, where, size, value);315}316 317static int cdns_ti_pcie_config_write(struct pci_bus *bus, unsigned int devfn,318 int where, int size, u32 value)319{320 if (pci_is_root_bus(bus))321 return pci_generic_config_write32(bus, devfn, where, size,322 value);323 324 return pci_generic_config_write(bus, devfn, where, size, value);325}326 327static struct pci_ops cdns_ti_pcie_host_ops = {328 .map_bus = cdns_pci_map_bus,329 .read = cdns_ti_pcie_config_read,330 .write = cdns_ti_pcie_config_write,331};332 333static const struct j721e_pcie_data j721e_pcie_rc_data = {334 .mode = PCI_MODE_RC,335 .quirk_retrain_flag = true,336 .byte_access_allowed = false,337 .linkdown_irq_regfield = LINK_DOWN,338 .max_lanes = 2,339};340 341static const struct j721e_pcie_data j721e_pcie_ep_data = {342 .mode = PCI_MODE_EP,343 .linkdown_irq_regfield = LINK_DOWN,344 .max_lanes = 2,345};346 347static const struct j721e_pcie_data j7200_pcie_rc_data = {348 .mode = PCI_MODE_RC,349 .quirk_detect_quiet_flag = true,350 .linkdown_irq_regfield = J7200_LINK_DOWN,351 .byte_access_allowed = true,352 .max_lanes = 2,353};354 355static const struct j721e_pcie_data j7200_pcie_ep_data = {356 .mode = PCI_MODE_EP,357 .quirk_detect_quiet_flag = true,358 .quirk_disable_flr = true,359 .max_lanes = 2,360};361 362static const struct j721e_pcie_data am64_pcie_rc_data = {363 .mode = PCI_MODE_RC,364 .linkdown_irq_regfield = J7200_LINK_DOWN,365 .byte_access_allowed = true,366 .max_lanes = 1,367};368 369static const struct j721e_pcie_data am64_pcie_ep_data = {370 .mode = PCI_MODE_EP,371 .linkdown_irq_regfield = J7200_LINK_DOWN,372 .max_lanes = 1,373};374 375static const struct j721e_pcie_data j784s4_pcie_rc_data = {376 .mode = PCI_MODE_RC,377 .quirk_retrain_flag = true,378 .byte_access_allowed = false,379 .linkdown_irq_regfield = LINK_DOWN,380 .max_lanes = 4,381};382 383static const struct j721e_pcie_data j784s4_pcie_ep_data = {384 .mode = PCI_MODE_EP,385 .linkdown_irq_regfield = LINK_DOWN,386 .max_lanes = 4,387};388 389static const struct of_device_id of_j721e_pcie_match[] = {390 {391 .compatible = "ti,j721e-pcie-host",392 .data = &j721e_pcie_rc_data,393 },394 {395 .compatible = "ti,j721e-pcie-ep",396 .data = &j721e_pcie_ep_data,397 },398 {399 .compatible = "ti,j7200-pcie-host",400 .data = &j7200_pcie_rc_data,401 },402 {403 .compatible = "ti,j7200-pcie-ep",404 .data = &j7200_pcie_ep_data,405 },406 {407 .compatible = "ti,am64-pcie-host",408 .data = &am64_pcie_rc_data,409 },410 {411 .compatible = "ti,am64-pcie-ep",412 .data = &am64_pcie_ep_data,413 },414 {415 .compatible = "ti,j784s4-pcie-host",416 .data = &j784s4_pcie_rc_data,417 },418 {419 .compatible = "ti,j784s4-pcie-ep",420 .data = &j784s4_pcie_ep_data,421 },422 {},423};424 425static int j721e_pcie_probe(struct platform_device *pdev)426{427 struct device *dev = &pdev->dev;428 struct device_node *node = dev->of_node;429 struct pci_host_bridge *bridge;430 const struct j721e_pcie_data *data;431 struct cdns_pcie *cdns_pcie;432 struct j721e_pcie *pcie;433 struct cdns_pcie_rc *rc = NULL;434 struct cdns_pcie_ep *ep = NULL;435 struct gpio_desc *gpiod;436 void __iomem *base;437 struct clk *clk;438 u32 num_lanes;439 u32 mode;440 int ret;441 int irq;442 443 data = of_device_get_match_data(dev);444 if (!data)445 return -EINVAL;446 447 mode = (u32)data->mode;448 449 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);450 if (!pcie)451 return -ENOMEM;452 453 switch (mode) {454 case PCI_MODE_RC:455 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_HOST))456 return -ENODEV;457 458 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));459 if (!bridge)460 return -ENOMEM;461 462 if (!data->byte_access_allowed)463 bridge->ops = &cdns_ti_pcie_host_ops;464 rc = pci_host_bridge_priv(bridge);465 rc->quirk_retrain_flag = data->quirk_retrain_flag;466 rc->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag;467 468 cdns_pcie = &rc->pcie;469 cdns_pcie->dev = dev;470 cdns_pcie->ops = &j721e_pcie_ops;471 pcie->cdns_pcie = cdns_pcie;472 break;473 case PCI_MODE_EP:474 if (!IS_ENABLED(CONFIG_PCIE_CADENCE_EP))475 return -ENODEV;476 477 ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);478 if (!ep)479 return -ENOMEM;480 481 ep->quirk_detect_quiet_flag = data->quirk_detect_quiet_flag;482 ep->quirk_disable_flr = data->quirk_disable_flr;483 484 cdns_pcie = &ep->pcie;485 cdns_pcie->dev = dev;486 cdns_pcie->ops = &j721e_pcie_ops;487 pcie->cdns_pcie = cdns_pcie;488 break;489 default:490 dev_err(dev, "INVALID device type %d\n", mode);491 return 0;492 }493 494 pcie->mode = mode;495 pcie->linkdown_irq_regfield = data->linkdown_irq_regfield;496 497 base = devm_platform_ioremap_resource_byname(pdev, "intd_cfg");498 if (IS_ERR(base))499 return PTR_ERR(base);500 pcie->intd_cfg_base = base;501 502 base = devm_platform_ioremap_resource_byname(pdev, "user_cfg");503 if (IS_ERR(base))504 return PTR_ERR(base);505 pcie->user_cfg_base = base;506 507 ret = of_property_read_u32(node, "num-lanes", &num_lanes);508 if (ret || num_lanes > data->max_lanes) {509 dev_warn(dev, "num-lanes property not provided or invalid, setting num-lanes to 1\n");510 num_lanes = 1;511 }512 513 pcie->num_lanes = num_lanes;514 pcie->max_lanes = data->max_lanes;515 516 if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)))517 return -EINVAL;518 519 irq = platform_get_irq_byname(pdev, "link_state");520 if (irq < 0)521 return irq;522 523 dev_set_drvdata(dev, pcie);524 pm_runtime_enable(dev);525 ret = pm_runtime_get_sync(dev);526 if (ret < 0) {527 dev_err_probe(dev, ret, "pm_runtime_get_sync failed\n");528 goto err_get_sync;529 }530 531 ret = j721e_pcie_ctrl_init(pcie);532 if (ret < 0) {533 dev_err_probe(dev, ret, "pm_runtime_get_sync failed\n");534 goto err_get_sync;535 }536 537 ret = devm_request_irq(dev, irq, j721e_pcie_link_irq_handler, 0,538 "j721e-pcie-link-down-irq", pcie);539 if (ret < 0) {540 dev_err_probe(dev, ret, "failed to request link state IRQ %d\n", irq);541 goto err_get_sync;542 }543 544 j721e_pcie_config_link_irq(pcie);545 546 switch (mode) {547 case PCI_MODE_RC:548 gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);549 if (IS_ERR(gpiod)) {550 ret = dev_err_probe(dev, PTR_ERR(gpiod), "Failed to get reset GPIO\n");551 goto err_get_sync;552 }553 pcie->reset_gpio = gpiod;554 555 ret = cdns_pcie_init_phy(dev, cdns_pcie);556 if (ret) {557 dev_err_probe(dev, ret, "Failed to init phy\n");558 goto err_get_sync;559 }560 561 clk = devm_clk_get_optional(dev, "pcie_refclk");562 if (IS_ERR(clk)) {563 ret = dev_err_probe(dev, PTR_ERR(clk), "failed to get pcie_refclk\n");564 goto err_pcie_setup;565 }566 567 ret = clk_prepare_enable(clk);568 if (ret) {569 dev_err_probe(dev, ret, "failed to enable pcie_refclk\n");570 goto err_pcie_setup;571 }572 pcie->refclk = clk;573 574 /*575 * The "Power Sequencing and Reset Signal Timings" table of the576 * PCI Express Card Electromechanical Specification, Revision577 * 5.1, Section 2.9.2, Symbol "T_PERST-CLK", indicates PERST#578 * should be deasserted after minimum of 100us once REFCLK is579 * stable. The REFCLK to the connector in RC mode is selected580 * while enabling the PHY. So deassert PERST# after 100 us.581 */582 if (gpiod) {583 fsleep(PCIE_T_PERST_CLK_US);584 gpiod_set_value_cansleep(gpiod, 1);585 }586 587 ret = cdns_pcie_host_setup(rc);588 if (ret < 0) {589 clk_disable_unprepare(pcie->refclk);590 goto err_pcie_setup;591 }592 593 break;594 case PCI_MODE_EP:595 ret = cdns_pcie_init_phy(dev, cdns_pcie);596 if (ret) {597 dev_err_probe(dev, ret, "Failed to init phy\n");598 goto err_get_sync;599 }600 601 ret = cdns_pcie_ep_setup(ep);602 if (ret < 0)603 goto err_pcie_setup;604 605 break;606 }607 608 return 0;609 610err_pcie_setup:611 cdns_pcie_disable_phy(cdns_pcie);612 613err_get_sync:614 pm_runtime_put(dev);615 pm_runtime_disable(dev);616 617 return ret;618}619 620static void j721e_pcie_remove(struct platform_device *pdev)621{622 struct j721e_pcie *pcie = platform_get_drvdata(pdev);623 struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;624 struct device *dev = &pdev->dev;625 626 clk_disable_unprepare(pcie->refclk);627 cdns_pcie_disable_phy(cdns_pcie);628 pm_runtime_put(dev);629 pm_runtime_disable(dev);630}631 632static int j721e_pcie_suspend_noirq(struct device *dev)633{634 struct j721e_pcie *pcie = dev_get_drvdata(dev);635 636 if (pcie->mode == PCI_MODE_RC) {637 gpiod_set_value_cansleep(pcie->reset_gpio, 0);638 clk_disable_unprepare(pcie->refclk);639 }640 641 cdns_pcie_disable_phy(pcie->cdns_pcie);642 643 return 0;644}645 646static int j721e_pcie_resume_noirq(struct device *dev)647{648 struct j721e_pcie *pcie = dev_get_drvdata(dev);649 struct cdns_pcie *cdns_pcie = pcie->cdns_pcie;650 int ret;651 652 ret = j721e_pcie_ctrl_init(pcie);653 if (ret < 0)654 return ret;655 656 j721e_pcie_config_link_irq(pcie);657 658 /*659 * This is not called explicitly in the probe, it is called by660 * cdns_pcie_init_phy().661 */662 ret = cdns_pcie_enable_phy(pcie->cdns_pcie);663 if (ret < 0)664 return ret;665 666 if (pcie->mode == PCI_MODE_RC) {667 struct cdns_pcie_rc *rc = cdns_pcie_to_rc(cdns_pcie);668 669 ret = clk_prepare_enable(pcie->refclk);670 if (ret < 0)671 return ret;672 673 /*674 * The "Power Sequencing and Reset Signal Timings" table of the675 * PCI Express Card Electromechanical Specification, Revision676 * 5.1, Section 2.9.2, Symbol "T_PERST-CLK", indicates PERST#677 * should be deasserted after minimum of 100us once REFCLK is678 * stable. The REFCLK to the connector in RC mode is selected679 * while enabling the PHY. So deassert PERST# after 100 us.680 */681 if (pcie->reset_gpio) {682 fsleep(PCIE_T_PERST_CLK_US);683 gpiod_set_value_cansleep(pcie->reset_gpio, 1);684 }685 686 ret = cdns_pcie_host_link_setup(rc);687 if (ret < 0) {688 clk_disable_unprepare(pcie->refclk);689 return ret;690 }691 692 /*693 * Reset internal status of BARs to force reinitialization in694 * cdns_pcie_host_init().695 */696 for (enum cdns_pcie_rp_bar bar = RP_BAR0; bar <= RP_NO_BAR; bar++)697 rc->avail_ib_bar[bar] = true;698 699 ret = cdns_pcie_host_init(rc);700 if (ret) {701 clk_disable_unprepare(pcie->refclk);702 return ret;703 }704 }705 706 return 0;707}708 709static DEFINE_NOIRQ_DEV_PM_OPS(j721e_pcie_pm_ops,710 j721e_pcie_suspend_noirq,711 j721e_pcie_resume_noirq);712 713static struct platform_driver j721e_pcie_driver = {714 .probe = j721e_pcie_probe,715 .remove_new = j721e_pcie_remove,716 .driver = {717 .name = "j721e-pcie",718 .of_match_table = of_j721e_pcie_match,719 .suppress_bind_attrs = true,720 .pm = pm_sleep_ptr(&j721e_pcie_pm_ops),721 },722};723builtin_platform_driver(j721e_pcie_driver);724