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1/* SPDX-License-Identifier: GPL-2.0 */2// Copyright (c) 2017 Cadence3// Cadence PCIe controller driver.4// Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>5 6#ifndef _PCIE_CADENCE_H7#define _PCIE_CADENCE_H8 9#include <linux/kernel.h>10#include <linux/pci.h>11#include <linux/pci-epf.h>12#include <linux/phy/phy.h>13 14/* Parameters for the waiting for link up routine */15#define LINK_WAIT_MAX_RETRIES 1016#define LINK_WAIT_USLEEP_MIN 9000017#define LINK_WAIT_USLEEP_MAX 10000018 19/*20 * Local Management Registers21 */22#define CDNS_PCIE_LM_BASE 0x0010000023 24/* Vendor ID Register */25#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044)26#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0)27#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 028#define CDNS_PCIE_LM_ID_VENDOR(vid) \29 (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK)30#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16)31#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 1632#define CDNS_PCIE_LM_ID_SUBSYS(sub) \33 (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK)34 35/* Root Port Requester ID Register */36#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228)37#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0)38#define CDNS_PCIE_LM_RP_RID_SHIFT 039#define CDNS_PCIE_LM_RP_RID_(rid) \40 (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK)41 42/* Endpoint Bus and Device Number Register */43#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022c)44#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0)45#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 046#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8)47#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 848 49/* Endpoint Function f BAR b Configuration Registers */50#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn) \51 (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn))52#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \53 (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008)54#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \55 (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008)56#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn) \57 (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn))58#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \59 (CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008)60#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \61 (CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008)62#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \63 (GENMASK(4, 0) << ((b) * 8))64#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \65 (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b))66#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \67 (GENMASK(7, 5) << ((b) * 8))68#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \69 (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b))70 71/* Endpoint Function Configuration Register */72#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02c0)73 74/* Root Complex BAR Configuration Register */75#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300)76#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0)77#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \78 (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK)79#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6)80#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \81 (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK)82#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9)83#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \84 (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK)85#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14)86#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \87 (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK)88#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17)89#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 090#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18)91#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19)92#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 093#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20)94#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31)95 96/* BAR control values applicable to both Endpoint Function and Root Complex */97#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x098#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x199#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4100#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5101#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6102#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7103 104#define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \105 (CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6))106#define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \107 (CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6))108#define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \109 (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6))110#define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \111 (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6))112#define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \113 (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6))114#define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \115 (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6))116#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \117 (((aperture) - 2) << ((bar) * 8))118 119/* PTM Control Register */120#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0da8)121#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17)122 123/*124 * Endpoint Function Registers (PCI configuration space for endpoint functions)125 */126#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12))127 128#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90129#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xb0130#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xc0131#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200132 133/*134 * Endpoint PF Registers135 */136#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000)137#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8)138 139/*140 * Root Port Registers (PCI configuration space for the root port function)141 */142#define CDNS_PCIE_RP_BASE 0x00200000143#define CDNS_PCIE_RP_CAP_OFFSET 0xc0144 145/*146 * Address Translation Registers147 */148#define CDNS_PCIE_AT_BASE 0x00400000149 150/* Region r Outbound AXI to PCIe Address Translation Register 0 */151#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \152 (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020)153#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0)154#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \155 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)156#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12)157#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \158 (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK)159#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20)160#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \161 (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK)162 163/* Region r Outbound AXI to PCIe Address Translation Register 1 */164#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \165 (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020)166 167/* Region r Outbound PCIe Descriptor Register 0 */168#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \169 (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020)170#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0)171#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2172#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6173#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xa174#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xb175#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xc176#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xd177/* Bit 23 MUST be set in RC mode. */178#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23)179#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24)180#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \181 (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK)182 183/* Region r Outbound PCIe Descriptor Register 1 */184#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \185 (CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020)186#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0)187#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \188 ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK)189 190/* Region r AXI Region Base Address Register 0 */191#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \192 (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020)193#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0)194#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \195 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)196 197/* Region r AXI Region Base Address Register 1 */198#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \199 (CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020)200 201/* Root Port BAR Inbound PCIe to AXI Address Translation Register */202#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \203 (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008)204#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0)205#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \206 (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK)207#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \208 (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008)209 210/* AXI link down register */211#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824)212 213/* LTSSM Capabilities register */214#define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x0054)215#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1)216#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1217#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \218 (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \219 CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK)220 221enum cdns_pcie_rp_bar {222 RP_BAR_UNDEFINED = -1,223 RP_BAR0,224 RP_BAR1,225 RP_NO_BAR226};227 228#define CDNS_PCIE_RP_MAX_IB 0x3229#define CDNS_PCIE_MAX_OB 32230 231struct cdns_pcie_rp_ib_bar {232 u64 size;233 bool free;234};235 236/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */237#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \238 (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008)239#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \240 (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008)241 242/* Normal/Vendor specific message access: offset inside some outbound region */243#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5)244#define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \245 (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK)246#define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8)247#define CDNS_PCIE_NORMAL_MSG_CODE(code) \248 (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK)249#define CDNS_PCIE_MSG_NO_DATA BIT(16)250 251struct cdns_pcie;252 253enum cdns_pcie_msg_code {254 MSG_CODE_ASSERT_INTA = 0x20,255 MSG_CODE_ASSERT_INTB = 0x21,256 MSG_CODE_ASSERT_INTC = 0x22,257 MSG_CODE_ASSERT_INTD = 0x23,258 MSG_CODE_DEASSERT_INTA = 0x24,259 MSG_CODE_DEASSERT_INTB = 0x25,260 MSG_CODE_DEASSERT_INTC = 0x26,261 MSG_CODE_DEASSERT_INTD = 0x27,262};263 264enum cdns_pcie_msg_routing {265 /* Route to Root Complex */266 MSG_ROUTING_TO_RC,267 268 /* Use Address Routing */269 MSG_ROUTING_BY_ADDR,270 271 /* Use ID Routing */272 MSG_ROUTING_BY_ID,273 274 /* Route as Broadcast Message from Root Complex */275 MSG_ROUTING_BCAST,276 277 /* Local message; terminate at receiver (INTx messages) */278 MSG_ROUTING_LOCAL,279 280 /* Gather & route to Root Complex (PME_TO_Ack message) */281 MSG_ROUTING_GATHER,282};283 284struct cdns_pcie_ops {285 int (*start_link)(struct cdns_pcie *pcie);286 void (*stop_link)(struct cdns_pcie *pcie);287 bool (*link_up)(struct cdns_pcie *pcie);288 u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr);289};290 291/**292 * struct cdns_pcie - private data for Cadence PCIe controller drivers293 * @reg_base: IO mapped register base294 * @mem_res: start/end offsets in the physical system memory to map PCI accesses295 * @dev: PCIe controller296 * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint.297 * @phy_count: number of supported PHY devices298 * @phy: list of pointers to specific PHY control blocks299 * @link: list of pointers to corresponding device link representations300 * @ops: Platform-specific ops to control various inputs from Cadence PCIe301 * wrapper302 */303struct cdns_pcie {304 void __iomem *reg_base;305 struct resource *mem_res;306 struct device *dev;307 bool is_rc;308 int phy_count;309 struct phy **phy;310 struct device_link **link;311 const struct cdns_pcie_ops *ops;312};313 314/**315 * struct cdns_pcie_rc - private data for this PCIe Root Complex driver316 * @pcie: Cadence PCIe controller317 * @cfg_res: start/end offsets in the physical system memory to map PCI318 * configuration space accesses319 * @cfg_base: IO mapped window to access the PCI configuration space of a320 * single function at a time321 * @vendor_id: PCI vendor ID322 * @device_id: PCI device ID323 * @avail_ib_bar: Status of RP_BAR0, RP_BAR1 and RP_NO_BAR if it's free or324 * available325 * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2326 * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk327 */328struct cdns_pcie_rc {329 struct cdns_pcie pcie;330 struct resource *cfg_res;331 void __iomem *cfg_base;332 u32 vendor_id;333 u32 device_id;334 bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB];335 unsigned int quirk_retrain_flag:1;336 unsigned int quirk_detect_quiet_flag:1;337};338 339/**340 * struct cdns_pcie_epf - Structure to hold info about endpoint function341 * @epf: Info about virtual functions attached to the physical function342 * @epf_bar: reference to the pci_epf_bar for the six Base Address Registers343 */344struct cdns_pcie_epf {345 struct cdns_pcie_epf *epf;346 struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS];347};348 349/**350 * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver351 * @pcie: Cadence PCIe controller352 * @max_regions: maximum number of regions supported by hardware353 * @ob_region_map: bitmask of mapped outbound regions354 * @ob_addr: base addresses in the AXI bus where the outbound regions start355 * @irq_phys_addr: base address on the AXI bus where the MSI/INTX IRQ356 * dedicated outbound regions is mapped.357 * @irq_cpu_addr: base address in the CPU space where a write access triggers358 * the sending of a memory write (MSI) / normal message (INTX359 * IRQ) TLP through the PCIe bus.360 * @irq_pci_addr: used to save the current mapping of the MSI/INTX IRQ361 * dedicated outbound region.362 * @irq_pci_fn: the latest PCI function that has updated the mapping of363 * the MSI/INTX IRQ dedicated outbound region.364 * @irq_pending: bitmask of asserted INTX IRQs.365 * @lock: spin lock to disable interrupts while modifying PCIe controller366 * registers fields (RMW) accessible by both remote RC and EP to367 * minimize time between read and write368 * @epf: Structure to hold info about endpoint function369 * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk370 * @quirk_disable_flr: Disable FLR (Function Level Reset) quirk flag371 */372struct cdns_pcie_ep {373 struct cdns_pcie pcie;374 u32 max_regions;375 unsigned long ob_region_map;376 phys_addr_t *ob_addr;377 phys_addr_t irq_phys_addr;378 void __iomem *irq_cpu_addr;379 u64 irq_pci_addr;380 u8 irq_pci_fn;381 u8 irq_pending;382 /* protect writing to PCI_STATUS while raising INTX interrupts */383 spinlock_t lock;384 struct cdns_pcie_epf *epf;385 unsigned int quirk_detect_quiet_flag:1;386 unsigned int quirk_disable_flr:1;387};388 389 390/* Register access */391static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value)392{393 writel(value, pcie->reg_base + reg);394}395 396static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg)397{398 return readl(pcie->reg_base + reg);399}400 401static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size)402{403 void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4);404 unsigned int offset = (unsigned long)addr & 0x3;405 u32 val = readl(aligned_addr);406 407 if (!IS_ALIGNED((uintptr_t)addr, size)) {408 pr_warn("Address %p and size %d are not aligned\n", addr, size);409 return 0;410 }411 412 if (size > 2)413 return val;414 415 return (val >> (8 * offset)) & ((1 << (size * 8)) - 1);416}417 418static inline void cdns_pcie_write_sz(void __iomem *addr, int size, u32 value)419{420 void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4);421 unsigned int offset = (unsigned long)addr & 0x3;422 u32 mask;423 u32 val;424 425 if (!IS_ALIGNED((uintptr_t)addr, size)) {426 pr_warn("Address %p and size %d are not aligned\n", addr, size);427 return;428 }429 430 if (size > 2) {431 writel(value, addr);432 return;433 }434 435 mask = ~(((1 << (size * 8)) - 1) << (offset * 8));436 val = readl(aligned_addr) & mask;437 val |= value << (offset * 8);438 writel(val, aligned_addr);439}440 441/* Root Port register access */442static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie,443 u32 reg, u8 value)444{445 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;446 447 cdns_pcie_write_sz(addr, 0x1, value);448}449 450static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie,451 u32 reg, u16 value)452{453 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;454 455 cdns_pcie_write_sz(addr, 0x2, value);456}457 458static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg)459{460 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;461 462 return cdns_pcie_read_sz(addr, 0x2);463}464 465/* Endpoint Function register access */466static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn,467 u32 reg, u8 value)468{469 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg;470 471 cdns_pcie_write_sz(addr, 0x1, value);472}473 474static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn,475 u32 reg, u16 value)476{477 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg;478 479 cdns_pcie_write_sz(addr, 0x2, value);480}481 482static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn,483 u32 reg, u32 value)484{485 writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);486}487 488static inline u16 cdns_pcie_ep_fn_readw(struct cdns_pcie *pcie, u8 fn, u32 reg)489{490 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg;491 492 return cdns_pcie_read_sz(addr, 0x2);493}494 495static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg)496{497 return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);498}499 500static inline int cdns_pcie_start_link(struct cdns_pcie *pcie)501{502 if (pcie->ops->start_link)503 return pcie->ops->start_link(pcie);504 505 return 0;506}507 508static inline void cdns_pcie_stop_link(struct cdns_pcie *pcie)509{510 if (pcie->ops->stop_link)511 pcie->ops->stop_link(pcie);512}513 514static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie)515{516 if (pcie->ops->link_up)517 return pcie->ops->link_up(pcie);518 519 return true;520}521 522#ifdef CONFIG_PCIE_CADENCE_HOST523int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc);524int cdns_pcie_host_init(struct cdns_pcie_rc *rc);525int cdns_pcie_host_setup(struct cdns_pcie_rc *rc);526void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,527 int where);528#else529static inline int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc)530{531 return 0;532}533 534static inline int cdns_pcie_host_init(struct cdns_pcie_rc *rc)535{536 return 0;537}538 539static inline int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)540{541 return 0;542}543 544static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,545 int where)546{547 return NULL;548}549#endif550 551#ifdef CONFIG_PCIE_CADENCE_EP552int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep);553#else554static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)555{556 return 0;557}558#endif559 560void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie);561 562void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,563 u32 r, bool is_io,564 u64 cpu_addr, u64 pci_addr, size_t size);565 566void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie,567 u8 busnr, u8 fn,568 u32 r, u64 cpu_addr);569 570void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r);571void cdns_pcie_disable_phy(struct cdns_pcie *pcie);572int cdns_pcie_enable_phy(struct cdns_pcie *pcie);573int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie);574extern const struct dev_pm_ops cdns_pcie_pm_ops;575 576#endif /* _PCIE_CADENCE_H */577