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1// SPDX-License-Identifier: GPL-2.02/*3 * PCIe controller EP driver for Freescale Layerscape SoCs4 *5 * Copyright (C) 2018 NXP Semiconductor.6 *7 * Author: Xiaowei Bao <xiaowei.bao@nxp.com>8 */9 10#include <linux/kernel.h>11#include <linux/init.h>12#include <linux/of_pci.h>13#include <linux/of_platform.h>14#include <linux/of_address.h>15#include <linux/pci.h>16#include <linux/platform_device.h>17#include <linux/resource.h>18 19#include "pcie-designware.h"20 21#define PEX_PF0_CONFIG 0xC001422#define PEX_PF0_CFG_READY BIT(0)23 24/* PEX PFa PCIE PME and message interrupt registers*/25#define PEX_PF0_PME_MES_DR 0xC002026#define PEX_PF0_PME_MES_DR_LUD BIT(7)27#define PEX_PF0_PME_MES_DR_LDD BIT(9)28#define PEX_PF0_PME_MES_DR_HRD BIT(10)29 30#define PEX_PF0_PME_MES_IER 0xC002831#define PEX_PF0_PME_MES_IER_LUDIE BIT(7)32#define PEX_PF0_PME_MES_IER_LDDIE BIT(9)33#define PEX_PF0_PME_MES_IER_HRDIE BIT(10)34 35#define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)36 37struct ls_pcie_ep_drvdata {38 u32 func_offset;39 const struct dw_pcie_ep_ops *ops;40 const struct dw_pcie_ops *dw_pcie_ops;41};42 43struct ls_pcie_ep {44 struct dw_pcie *pci;45 struct pci_epc_features *ls_epc;46 const struct ls_pcie_ep_drvdata *drvdata;47 int irq;48 u32 lnkcap;49 bool big_endian;50};51 52static u32 ls_pcie_pf_lut_readl(struct ls_pcie_ep *pcie, u32 offset)53{54 struct dw_pcie *pci = pcie->pci;55 56 if (pcie->big_endian)57 return ioread32be(pci->dbi_base + offset);58 else59 return ioread32(pci->dbi_base + offset);60}61 62static void ls_pcie_pf_lut_writel(struct ls_pcie_ep *pcie, u32 offset, u32 value)63{64 struct dw_pcie *pci = pcie->pci;65 66 if (pcie->big_endian)67 iowrite32be(value, pci->dbi_base + offset);68 else69 iowrite32(value, pci->dbi_base + offset);70}71 72static irqreturn_t ls_pcie_ep_event_handler(int irq, void *dev_id)73{74 struct ls_pcie_ep *pcie = dev_id;75 struct dw_pcie *pci = pcie->pci;76 u32 val, cfg;77 u8 offset;78 79 val = ls_pcie_pf_lut_readl(pcie, PEX_PF0_PME_MES_DR);80 ls_pcie_pf_lut_writel(pcie, PEX_PF0_PME_MES_DR, val);81 82 if (!val)83 return IRQ_NONE;84 85 if (val & PEX_PF0_PME_MES_DR_LUD) {86 87 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);88 89 /*90 * The values of the Maximum Link Width and Supported Link91 * Speed from the Link Capabilities Register will be lost92 * during link down or hot reset. Restore initial value93 * that configured by the Reset Configuration Word (RCW).94 */95 dw_pcie_dbi_ro_wr_en(pci);96 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, pcie->lnkcap);97 dw_pcie_dbi_ro_wr_dis(pci);98 99 cfg = ls_pcie_pf_lut_readl(pcie, PEX_PF0_CONFIG);100 cfg |= PEX_PF0_CFG_READY;101 ls_pcie_pf_lut_writel(pcie, PEX_PF0_CONFIG, cfg);102 dw_pcie_ep_linkup(&pci->ep);103 104 dev_dbg(pci->dev, "Link up\n");105 } else if (val & PEX_PF0_PME_MES_DR_LDD) {106 dev_dbg(pci->dev, "Link down\n");107 dw_pcie_ep_linkdown(&pci->ep);108 } else if (val & PEX_PF0_PME_MES_DR_HRD) {109 dev_dbg(pci->dev, "Hot reset\n");110 }111 112 return IRQ_HANDLED;113}114 115static int ls_pcie_ep_interrupt_init(struct ls_pcie_ep *pcie,116 struct platform_device *pdev)117{118 u32 val;119 int ret;120 121 pcie->irq = platform_get_irq_byname(pdev, "pme");122 if (pcie->irq < 0)123 return pcie->irq;124 125 ret = devm_request_irq(&pdev->dev, pcie->irq, ls_pcie_ep_event_handler,126 IRQF_SHARED, pdev->name, pcie);127 if (ret) {128 dev_err(&pdev->dev, "Can't register PCIe IRQ\n");129 return ret;130 }131 132 /* Enable interrupts */133 val = ls_pcie_pf_lut_readl(pcie, PEX_PF0_PME_MES_IER);134 val |= PEX_PF0_PME_MES_IER_LDDIE | PEX_PF0_PME_MES_IER_HRDIE |135 PEX_PF0_PME_MES_IER_LUDIE;136 ls_pcie_pf_lut_writel(pcie, PEX_PF0_PME_MES_IER, val);137 138 return 0;139}140 141static const struct pci_epc_features*142ls_pcie_ep_get_features(struct dw_pcie_ep *ep)143{144 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);145 struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);146 147 return pcie->ls_epc;148}149 150static void ls_pcie_ep_init(struct dw_pcie_ep *ep)151{152 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);153 struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);154 struct dw_pcie_ep_func *ep_func;155 enum pci_barno bar;156 157 ep_func = dw_pcie_ep_get_func_from_ep(ep, 0);158 if (!ep_func)159 return;160 161 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)162 dw_pcie_ep_reset_bar(pci, bar);163 164 pcie->ls_epc->msi_capable = ep_func->msi_cap ? true : false;165 pcie->ls_epc->msix_capable = ep_func->msix_cap ? true : false;166}167 168static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,169 unsigned int type, u16 interrupt_num)170{171 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);172 173 switch (type) {174 case PCI_IRQ_INTX:175 return dw_pcie_ep_raise_intx_irq(ep, func_no);176 case PCI_IRQ_MSI:177 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);178 case PCI_IRQ_MSIX:179 return dw_pcie_ep_raise_msix_irq_doorbell(ep, func_no,180 interrupt_num);181 default:182 dev_err(pci->dev, "UNKNOWN IRQ type\n");183 return -EINVAL;184 }185}186 187static unsigned int ls_pcie_ep_get_dbi_offset(struct dw_pcie_ep *ep, u8 func_no)188{189 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);190 struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);191 192 WARN_ON(func_no && !pcie->drvdata->func_offset);193 return pcie->drvdata->func_offset * func_no;194}195 196static const struct dw_pcie_ep_ops ls_pcie_ep_ops = {197 .init = ls_pcie_ep_init,198 .raise_irq = ls_pcie_ep_raise_irq,199 .get_features = ls_pcie_ep_get_features,200 .get_dbi_offset = ls_pcie_ep_get_dbi_offset,201};202 203static const struct ls_pcie_ep_drvdata ls1_ep_drvdata = {204 .ops = &ls_pcie_ep_ops,205};206 207static const struct ls_pcie_ep_drvdata ls2_ep_drvdata = {208 .func_offset = 0x20000,209 .ops = &ls_pcie_ep_ops,210};211 212static const struct ls_pcie_ep_drvdata lx2_ep_drvdata = {213 .func_offset = 0x8000,214 .ops = &ls_pcie_ep_ops,215};216 217static const struct of_device_id ls_pcie_ep_of_match[] = {218 { .compatible = "fsl,ls1028a-pcie-ep", .data = &ls1_ep_drvdata },219 { .compatible = "fsl,ls1046a-pcie-ep", .data = &ls1_ep_drvdata },220 { .compatible = "fsl,ls1088a-pcie-ep", .data = &ls2_ep_drvdata },221 { .compatible = "fsl,ls2088a-pcie-ep", .data = &ls2_ep_drvdata },222 { .compatible = "fsl,lx2160ar2-pcie-ep", .data = &lx2_ep_drvdata },223 { },224};225 226static int __init ls_pcie_ep_probe(struct platform_device *pdev)227{228 struct device *dev = &pdev->dev;229 struct dw_pcie *pci;230 struct ls_pcie_ep *pcie;231 struct pci_epc_features *ls_epc;232 struct resource *dbi_base;233 u8 offset;234 int ret;235 236 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);237 if (!pcie)238 return -ENOMEM;239 240 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);241 if (!pci)242 return -ENOMEM;243 244 ls_epc = devm_kzalloc(dev, sizeof(*ls_epc), GFP_KERNEL);245 if (!ls_epc)246 return -ENOMEM;247 248 pcie->drvdata = of_device_get_match_data(dev);249 250 pci->dev = dev;251 pci->ops = pcie->drvdata->dw_pcie_ops;252 253 ls_epc->bar[BAR_2].only_64bit = true;254 ls_epc->bar[BAR_3].type = BAR_RESERVED;255 ls_epc->bar[BAR_4].only_64bit = true;256 ls_epc->bar[BAR_5].type = BAR_RESERVED;257 ls_epc->linkup_notifier = true;258 259 pcie->pci = pci;260 pcie->ls_epc = ls_epc;261 262 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");263 pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);264 if (IS_ERR(pci->dbi_base))265 return PTR_ERR(pci->dbi_base);266 267 pci->ep.ops = &ls_pcie_ep_ops;268 269 pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian");270 271 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));272 273 platform_set_drvdata(pdev, pcie);274 275 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);276 pcie->lnkcap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);277 278 ret = dw_pcie_ep_init(&pci->ep);279 if (ret)280 return ret;281 282 ret = dw_pcie_ep_init_registers(&pci->ep);283 if (ret) {284 dev_err(dev, "Failed to initialize DWC endpoint registers\n");285 dw_pcie_ep_deinit(&pci->ep);286 return ret;287 }288 289 pci_epc_init_notify(pci->ep.epc);290 291 return ls_pcie_ep_interrupt_init(pcie, pdev);292}293 294static struct platform_driver ls_pcie_ep_driver = {295 .driver = {296 .name = "layerscape-pcie-ep",297 .of_match_table = ls_pcie_ep_of_match,298 .suppress_bind_attrs = true,299 },300};301builtin_platform_driver_probe(ls_pcie_ep_driver, ls_pcie_ep_probe);302