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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Synopsys DesignWare PCIe host controller driver4 *5 * Copyright (C) 2013 Samsung Electronics Co., Ltd.6 * https://www.samsung.com7 *8 * Author: Jingoo Han <jg1.han@samsung.com>9 */10 11#ifndef _PCIE_DESIGNWARE_H12#define _PCIE_DESIGNWARE_H13 14#include <linux/bitfield.h>15#include <linux/bitops.h>16#include <linux/clk.h>17#include <linux/dma-mapping.h>18#include <linux/dma/edma.h>19#include <linux/gpio/consumer.h>20#include <linux/irq.h>21#include <linux/msi.h>22#include <linux/pci.h>23#include <linux/reset.h>24 25#include <linux/pci-epc.h>26#include <linux/pci-epf.h>27 28/* DWC PCIe IP-core versions (native support since v4.70a) */29#define DW_PCIE_VER_365A 0x3336352a30#define DW_PCIE_VER_460A 0x3436302a31#define DW_PCIE_VER_470A 0x3437302a32#define DW_PCIE_VER_480A 0x3438302a33#define DW_PCIE_VER_490A 0x3439302a34#define DW_PCIE_VER_520A 0x3532302a35#define DW_PCIE_VER_540A 0x3534302a36 37#define __dw_pcie_ver_cmp(_pci, _ver, _op) \38 ((_pci)->version _op DW_PCIE_VER_ ## _ver)39 40#define dw_pcie_ver_is(_pci, _ver) __dw_pcie_ver_cmp(_pci, _ver, ==)41 42#define dw_pcie_ver_is_ge(_pci, _ver) __dw_pcie_ver_cmp(_pci, _ver, >=)43 44#define dw_pcie_ver_type_is(_pci, _ver, _type) \45 (__dw_pcie_ver_cmp(_pci, _ver, ==) && \46 __dw_pcie_ver_cmp(_pci, TYPE_ ## _type, ==))47 48#define dw_pcie_ver_type_is_ge(_pci, _ver, _type) \49 (__dw_pcie_ver_cmp(_pci, _ver, ==) && \50 __dw_pcie_ver_cmp(_pci, TYPE_ ## _type, >=))51 52/* DWC PCIe controller capabilities */53#define DW_PCIE_CAP_REQ_RES 054#define DW_PCIE_CAP_IATU_UNROLL 155#define DW_PCIE_CAP_CDM_CHECK 256 57#define dw_pcie_cap_is(_pci, _cap) \58 test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps)59 60#define dw_pcie_cap_set(_pci, _cap) \61 set_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps)62 63/* Parameters for the waiting for link up routine */64#define LINK_WAIT_MAX_RETRIES 1065#define LINK_WAIT_SLEEP_MS 9066 67/* Parameters for the waiting for iATU enabled routine */68#define LINK_WAIT_MAX_IATU_RETRIES 569#define LINK_WAIT_IATU 970 71/* Synopsys-specific PCIe configuration registers */72#define PCIE_PORT_FORCE 0x70873#define PORT_FORCE_DO_DESKEW_FOR_SRIS BIT(23)74 75#define PCIE_PORT_AFR 0x70C76#define PORT_AFR_N_FTS_MASK GENMASK(15, 8)77#define PORT_AFR_N_FTS(n) FIELD_PREP(PORT_AFR_N_FTS_MASK, n)78#define PORT_AFR_CC_N_FTS_MASK GENMASK(23, 16)79#define PORT_AFR_CC_N_FTS(n) FIELD_PREP(PORT_AFR_CC_N_FTS_MASK, n)80#define PORT_AFR_ENTER_ASPM BIT(30)81#define PORT_AFR_L0S_ENTRANCE_LAT_SHIFT 2482#define PORT_AFR_L0S_ENTRANCE_LAT_MASK GENMASK(26, 24)83#define PORT_AFR_L1_ENTRANCE_LAT_SHIFT 2784#define PORT_AFR_L1_ENTRANCE_LAT_MASK GENMASK(29, 27)85 86#define PCIE_PORT_LINK_CONTROL 0x71087#define PORT_LINK_DLL_LINK_EN BIT(5)88#define PORT_LINK_FAST_LINK_MODE BIT(7)89#define PORT_LINK_MODE_MASK GENMASK(21, 16)90#define PORT_LINK_MODE(n) FIELD_PREP(PORT_LINK_MODE_MASK, n)91#define PORT_LINK_MODE_1_LANES PORT_LINK_MODE(0x1)92#define PORT_LINK_MODE_2_LANES PORT_LINK_MODE(0x3)93#define PORT_LINK_MODE_4_LANES PORT_LINK_MODE(0x7)94#define PORT_LINK_MODE_8_LANES PORT_LINK_MODE(0xf)95 96#define PCIE_PORT_LANE_SKEW 0x71497#define PORT_LANE_SKEW_INSERT_MASK GENMASK(23, 0)98 99#define PCIE_PORT_DEBUG0 0x728100#define PORT_LOGIC_LTSSM_STATE_MASK 0x1f101#define PORT_LOGIC_LTSSM_STATE_L0 0x11102#define PCIE_PORT_DEBUG1 0x72C103#define PCIE_PORT_DEBUG1_LINK_UP BIT(4)104#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING BIT(29)105 106#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C107#define PORT_LOGIC_N_FTS_MASK GENMASK(7, 0)108#define PORT_LOGIC_SPEED_CHANGE BIT(17)109#define PORT_LOGIC_LINK_WIDTH_MASK GENMASK(12, 8)110#define PORT_LOGIC_LINK_WIDTH(n) FIELD_PREP(PORT_LOGIC_LINK_WIDTH_MASK, n)111#define PORT_LOGIC_LINK_WIDTH_1_LANES PORT_LOGIC_LINK_WIDTH(0x1)112#define PORT_LOGIC_LINK_WIDTH_2_LANES PORT_LOGIC_LINK_WIDTH(0x2)113#define PORT_LOGIC_LINK_WIDTH_4_LANES PORT_LOGIC_LINK_WIDTH(0x4)114#define PORT_LOGIC_LINK_WIDTH_8_LANES PORT_LOGIC_LINK_WIDTH(0x8)115 116#define PCIE_MSI_ADDR_LO 0x820117#define PCIE_MSI_ADDR_HI 0x824118#define PCIE_MSI_INTR0_ENABLE 0x828119#define PCIE_MSI_INTR0_MASK 0x82C120#define PCIE_MSI_INTR0_STATUS 0x830121 122#define GEN3_RELATED_OFF 0x890123#define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0)124#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13)125#define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16)126#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24127#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24)128#define GEN3_RELATED_OFF_RATE_SHADOW_SEL_16_0GT 0x1129 130#define GEN3_EQ_CONTROL_OFF 0x8A8131#define GEN3_EQ_CONTROL_OFF_FB_MODE GENMASK(3, 0)132#define GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE BIT(4)133#define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC GENMASK(23, 8)134#define GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL BIT(24)135 136#define GEN3_EQ_FB_MODE_DIR_CHANGE_OFF 0x8AC137#define GEN3_EQ_FMDC_T_MIN_PHASE23 GENMASK(4, 0)138#define GEN3_EQ_FMDC_N_EVALS GENMASK(9, 5)139#define GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA GENMASK(13, 10)140#define GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA GENMASK(17, 14)141 142#define PCIE_PORT_MULTI_LANE_CTRL 0x8C0143#define PORT_MLTI_UPCFG_SUPPORT BIT(7)144 145#define PCIE_VERSION_NUMBER 0x8F8146#define PCIE_VERSION_TYPE 0x8FC147 148/*149 * iATU inbound and outbound windows CSRs. Before the IP-core v4.80a each150 * iATU region CSRs had been indirectly accessible by means of the dedicated151 * viewport selector. The iATU/eDMA CSRs space was re-designed in DWC PCIe152 * v4.80a in a way so the viewport was unrolled into the directly accessible153 * iATU/eDMA CSRs space.154 */155#define PCIE_ATU_VIEWPORT 0x900156#define PCIE_ATU_REGION_DIR_IB BIT(31)157#define PCIE_ATU_REGION_DIR_OB 0158#define PCIE_ATU_VIEWPORT_BASE 0x904159#define PCIE_ATU_UNROLL_BASE(dir, index) \160 (((index) << 9) | ((dir == PCIE_ATU_REGION_DIR_IB) ? BIT(8) : 0))161#define PCIE_ATU_VIEWPORT_SIZE 0x2C162#define PCIE_ATU_REGION_CTRL1 0x000163#define PCIE_ATU_INCREASE_REGION_SIZE BIT(13)164#define PCIE_ATU_TYPE_MEM 0x0165#define PCIE_ATU_TYPE_IO 0x2166#define PCIE_ATU_TYPE_CFG0 0x4167#define PCIE_ATU_TYPE_CFG1 0x5168#define PCIE_ATU_TYPE_MSG 0x10169#define PCIE_ATU_TD BIT(8)170#define PCIE_ATU_FUNC_NUM(pf) ((pf) << 20)171#define PCIE_ATU_REGION_CTRL2 0x004172#define PCIE_ATU_ENABLE BIT(31)173#define PCIE_ATU_BAR_MODE_ENABLE BIT(30)174#define PCIE_ATU_INHIBIT_PAYLOAD BIT(22)175#define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19)176#define PCIE_ATU_LOWER_BASE 0x008177#define PCIE_ATU_UPPER_BASE 0x00C178#define PCIE_ATU_LIMIT 0x010179#define PCIE_ATU_LOWER_TARGET 0x014180#define PCIE_ATU_BUS(x) FIELD_PREP(GENMASK(31, 24), x)181#define PCIE_ATU_DEV(x) FIELD_PREP(GENMASK(23, 19), x)182#define PCIE_ATU_FUNC(x) FIELD_PREP(GENMASK(18, 16), x)183#define PCIE_ATU_UPPER_TARGET 0x018184#define PCIE_ATU_UPPER_LIMIT 0x020185 186#define PCIE_MISC_CONTROL_1_OFF 0x8BC187#define PCIE_DBI_RO_WR_EN BIT(0)188 189#define PCIE_MSIX_DOORBELL 0x948190#define PCIE_MSIX_DOORBELL_PF_SHIFT 24191 192/*193 * eDMA CSRs. DW PCIe IP-core v4.70a and older had the eDMA registers accessible194 * over the Port Logic registers space. Afterwards the unrolled mapping was195 * introduced so eDMA and iATU could be accessed via a dedicated registers196 * space.197 */198#define PCIE_DMA_VIEWPORT_BASE 0x970199#define PCIE_DMA_UNROLL_BASE 0x80000200#define PCIE_DMA_CTRL 0x008201#define PCIE_DMA_NUM_WR_CHAN GENMASK(3, 0)202#define PCIE_DMA_NUM_RD_CHAN GENMASK(19, 16)203 204#define PCIE_PL_CHK_REG_CONTROL_STATUS 0xB20205#define PCIE_PL_CHK_REG_CHK_REG_START BIT(0)206#define PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS BIT(1)207#define PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR BIT(16)208#define PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR BIT(17)209#define PCIE_PL_CHK_REG_CHK_REG_COMPLETE BIT(18)210 211#define PCIE_PL_CHK_REG_ERR_ADDR 0xB28212 213/*214 * 16.0 GT/s (Gen 4) lane margining register definitions215 */216#define GEN4_LANE_MARGINING_1_OFF 0xB80217#define MARGINING_MAX_VOLTAGE_OFFSET GENMASK(29, 24)218#define MARGINING_NUM_VOLTAGE_STEPS GENMASK(22, 16)219#define MARGINING_MAX_TIMING_OFFSET GENMASK(13, 8)220#define MARGINING_NUM_TIMING_STEPS GENMASK(5, 0)221 222#define GEN4_LANE_MARGINING_2_OFF 0xB84223#define MARGINING_IND_ERROR_SAMPLER BIT(28)224#define MARGINING_SAMPLE_REPORTING_METHOD BIT(27)225#define MARGINING_IND_LEFT_RIGHT_TIMING BIT(26)226#define MARGINING_IND_UP_DOWN_VOLTAGE BIT(25)227#define MARGINING_VOLTAGE_SUPPORTED BIT(24)228#define MARGINING_MAXLANES GENMASK(20, 16)229#define MARGINING_SAMPLE_RATE_TIMING GENMASK(13, 8)230#define MARGINING_SAMPLE_RATE_VOLTAGE GENMASK(5, 0)231/*232 * iATU Unroll-specific register definitions233 * From 4.80 core version the address translation will be made by unroll234 */235#define PCIE_ATU_UNR_REGION_CTRL1 0x00236#define PCIE_ATU_UNR_REGION_CTRL2 0x04237#define PCIE_ATU_UNR_LOWER_BASE 0x08238#define PCIE_ATU_UNR_UPPER_BASE 0x0C239#define PCIE_ATU_UNR_LOWER_LIMIT 0x10240#define PCIE_ATU_UNR_LOWER_TARGET 0x14241#define PCIE_ATU_UNR_UPPER_TARGET 0x18242#define PCIE_ATU_UNR_UPPER_LIMIT 0x20243 244/*245 * RAS-DES register definitions246 */247#define PCIE_RAS_DES_EVENT_COUNTER_CONTROL 0x8248#define EVENT_COUNTER_ALL_CLEAR 0x3249#define EVENT_COUNTER_ENABLE_ALL 0x7250#define EVENT_COUNTER_ENABLE_SHIFT 2251#define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(7, 0)252#define EVENT_COUNTER_EVENT_SEL_SHIFT 16253#define EVENT_COUNTER_EVENT_Tx_L0S 0x2254#define EVENT_COUNTER_EVENT_Rx_L0S 0x3255#define EVENT_COUNTER_EVENT_L1 0x5256#define EVENT_COUNTER_EVENT_L1_1 0x7257#define EVENT_COUNTER_EVENT_L1_2 0x8258#define EVENT_COUNTER_GROUP_SEL_SHIFT 24259#define EVENT_COUNTER_GROUP_5 0x5260 261#define PCIE_RAS_DES_EVENT_COUNTER_DATA 0xc262 263/*264 * The default address offset between dbi_base and atu_base. Root controller265 * drivers are not required to initialize atu_base if the offset matches this266 * default; the driver core automatically derives atu_base from dbi_base using267 * this offset, if atu_base not set.268 */269#define DEFAULT_DBI_ATU_OFFSET (0x3 << 20)270#define DEFAULT_DBI_DMA_OFFSET PCIE_DMA_UNROLL_BASE271 272#define MAX_MSI_IRQS 256273#define MAX_MSI_IRQS_PER_CTRL 32274#define MAX_MSI_CTRLS (MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL)275#define MSI_REG_CTRL_BLOCK_SIZE 12276#define MSI_DEF_NUM_VECTORS 32277 278/* Maximum number of inbound/outbound iATUs */279#define MAX_IATU_IN 256280#define MAX_IATU_OUT 256281 282/* Default eDMA LLP memory size */283#define DMA_LLP_MEM_SIZE PAGE_SIZE284 285struct dw_pcie;286struct dw_pcie_rp;287struct dw_pcie_ep;288 289enum dw_pcie_device_mode {290 DW_PCIE_UNKNOWN_TYPE,291 DW_PCIE_EP_TYPE,292 DW_PCIE_LEG_EP_TYPE,293 DW_PCIE_RC_TYPE,294};295 296enum dw_pcie_app_clk {297 DW_PCIE_DBI_CLK,298 DW_PCIE_MSTR_CLK,299 DW_PCIE_SLV_CLK,300 DW_PCIE_NUM_APP_CLKS301};302 303enum dw_pcie_core_clk {304 DW_PCIE_PIPE_CLK,305 DW_PCIE_CORE_CLK,306 DW_PCIE_AUX_CLK,307 DW_PCIE_REF_CLK,308 DW_PCIE_NUM_CORE_CLKS309};310 311enum dw_pcie_app_rst {312 DW_PCIE_DBI_RST,313 DW_PCIE_MSTR_RST,314 DW_PCIE_SLV_RST,315 DW_PCIE_NUM_APP_RSTS316};317 318enum dw_pcie_core_rst {319 DW_PCIE_NON_STICKY_RST,320 DW_PCIE_STICKY_RST,321 DW_PCIE_CORE_RST,322 DW_PCIE_PIPE_RST,323 DW_PCIE_PHY_RST,324 DW_PCIE_HOT_RST,325 DW_PCIE_PWR_RST,326 DW_PCIE_NUM_CORE_RSTS327};328 329enum dw_pcie_ltssm {330 /* Need to align with PCIE_PORT_DEBUG0 bits 0:5 */331 DW_PCIE_LTSSM_DETECT_QUIET = 0x0,332 DW_PCIE_LTSSM_DETECT_ACT = 0x1,333 DW_PCIE_LTSSM_L0 = 0x11,334 DW_PCIE_LTSSM_L2_IDLE = 0x15,335 336 DW_PCIE_LTSSM_UNKNOWN = 0xFFFFFFFF,337};338 339struct dw_pcie_ob_atu_cfg {340 int index;341 int type;342 u8 func_no;343 u8 code;344 u8 routing;345 u64 cpu_addr;346 u64 pci_addr;347 u64 size;348};349 350struct dw_pcie_host_ops {351 int (*init)(struct dw_pcie_rp *pp);352 void (*deinit)(struct dw_pcie_rp *pp);353 void (*post_init)(struct dw_pcie_rp *pp);354 int (*msi_init)(struct dw_pcie_rp *pp);355 void (*pme_turn_off)(struct dw_pcie_rp *pp);356};357 358struct dw_pcie_rp {359 bool has_msi_ctrl:1;360 bool cfg0_io_shared:1;361 u64 cfg0_base;362 void __iomem *va_cfg0_base;363 u32 cfg0_size;364 resource_size_t io_base;365 phys_addr_t io_bus_addr;366 u32 io_size;367 int irq;368 const struct dw_pcie_host_ops *ops;369 int msi_irq[MAX_MSI_CTRLS];370 struct irq_domain *irq_domain;371 struct irq_domain *msi_domain;372 dma_addr_t msi_data;373 struct irq_chip *msi_irq_chip;374 u32 num_vectors;375 u32 irq_mask[MAX_MSI_CTRLS];376 struct pci_host_bridge *bridge;377 raw_spinlock_t lock;378 DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);379 bool use_atu_msg;380 int msg_atu_index;381 struct resource *msg_res;382};383 384struct dw_pcie_ep_ops {385 void (*pre_init)(struct dw_pcie_ep *ep);386 void (*init)(struct dw_pcie_ep *ep);387 int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,388 unsigned int type, u16 interrupt_num);389 const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);390 /*391 * Provide a method to implement the different func config space392 * access for different platform, if different func have different393 * offset, return the offset of func. if use write a register way394 * return a 0, and implement code in callback function of platform395 * driver.396 */397 unsigned int (*get_dbi_offset)(struct dw_pcie_ep *ep, u8 func_no);398 unsigned int (*get_dbi2_offset)(struct dw_pcie_ep *ep, u8 func_no);399};400 401struct dw_pcie_ep_func {402 struct list_head list;403 u8 func_no;404 u8 msi_cap; /* MSI capability offset */405 u8 msix_cap; /* MSI-X capability offset */406};407 408struct dw_pcie_ep {409 struct pci_epc *epc;410 struct list_head func_list;411 const struct dw_pcie_ep_ops *ops;412 phys_addr_t phys_base;413 size_t addr_size;414 size_t page_size;415 u8 bar_to_atu[PCI_STD_NUM_BARS];416 phys_addr_t *outbound_addr;417 unsigned long *ib_window_map;418 unsigned long *ob_window_map;419 void __iomem *msi_mem;420 phys_addr_t msi_mem_phys;421 struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS];422};423 424struct dw_pcie_ops {425 u64 (*cpu_addr_fixup)(struct dw_pcie *pcie, u64 cpu_addr);426 u32 (*read_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,427 size_t size);428 void (*write_dbi)(struct dw_pcie *pcie, void __iomem *base, u32 reg,429 size_t size, u32 val);430 void (*write_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg,431 size_t size, u32 val);432 int (*link_up)(struct dw_pcie *pcie);433 enum dw_pcie_ltssm (*get_ltssm)(struct dw_pcie *pcie);434 int (*start_link)(struct dw_pcie *pcie);435 void (*stop_link)(struct dw_pcie *pcie);436};437 438struct dw_pcie {439 struct device *dev;440 void __iomem *dbi_base;441 resource_size_t dbi_phys_addr;442 void __iomem *dbi_base2;443 void __iomem *atu_base;444 resource_size_t atu_phys_addr;445 size_t atu_size;446 u32 num_ib_windows;447 u32 num_ob_windows;448 u32 region_align;449 u64 region_limit;450 struct dw_pcie_rp pp;451 struct dw_pcie_ep ep;452 const struct dw_pcie_ops *ops;453 u32 version;454 u32 type;455 unsigned long caps;456 int num_lanes;457 int max_link_speed;458 u8 n_fts[2];459 struct dw_edma_chip edma;460 struct clk_bulk_data app_clks[DW_PCIE_NUM_APP_CLKS];461 struct clk_bulk_data core_clks[DW_PCIE_NUM_CORE_CLKS];462 struct reset_control_bulk_data app_rsts[DW_PCIE_NUM_APP_RSTS];463 struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS];464 struct gpio_desc *pe_rst;465 bool suspended;466};467 468#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)469 470#define to_dw_pcie_from_ep(endpoint) \471 container_of((endpoint), struct dw_pcie, ep)472 473int dw_pcie_get_resources(struct dw_pcie *pci);474 475void dw_pcie_version_detect(struct dw_pcie *pci);476 477u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);478u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap);479 480int dw_pcie_read(void __iomem *addr, int size, u32 *val);481int dw_pcie_write(void __iomem *addr, int size, u32 val);482 483u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size);484void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val);485void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val);486int dw_pcie_link_up(struct dw_pcie *pci);487void dw_pcie_upconfig_setup(struct dw_pcie *pci);488int dw_pcie_wait_for_link(struct dw_pcie *pci);489int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,490 const struct dw_pcie_ob_atu_cfg *atu);491int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,492 u64 cpu_addr, u64 pci_addr, u64 size);493int dw_pcie_prog_ep_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,494 int type, u64 cpu_addr, u8 bar);495void dw_pcie_disable_atu(struct dw_pcie *pci, u32 dir, int index);496void dw_pcie_setup(struct dw_pcie *pci);497void dw_pcie_iatu_detect(struct dw_pcie *pci);498int dw_pcie_edma_detect(struct dw_pcie *pci);499void dw_pcie_edma_remove(struct dw_pcie *pci);500 501int dw_pcie_suspend_noirq(struct dw_pcie *pci);502int dw_pcie_resume_noirq(struct dw_pcie *pci);503 504static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val)505{506 dw_pcie_write_dbi(pci, reg, 0x4, val);507}508 509static inline u32 dw_pcie_readl_dbi(struct dw_pcie *pci, u32 reg)510{511 return dw_pcie_read_dbi(pci, reg, 0x4);512}513 514static inline void dw_pcie_writew_dbi(struct dw_pcie *pci, u32 reg, u16 val)515{516 dw_pcie_write_dbi(pci, reg, 0x2, val);517}518 519static inline u16 dw_pcie_readw_dbi(struct dw_pcie *pci, u32 reg)520{521 return dw_pcie_read_dbi(pci, reg, 0x2);522}523 524static inline void dw_pcie_writeb_dbi(struct dw_pcie *pci, u32 reg, u8 val)525{526 dw_pcie_write_dbi(pci, reg, 0x1, val);527}528 529static inline u8 dw_pcie_readb_dbi(struct dw_pcie *pci, u32 reg)530{531 return dw_pcie_read_dbi(pci, reg, 0x1);532}533 534static inline void dw_pcie_writel_dbi2(struct dw_pcie *pci, u32 reg, u32 val)535{536 dw_pcie_write_dbi2(pci, reg, 0x4, val);537}538 539static inline unsigned int dw_pcie_ep_get_dbi_offset(struct dw_pcie_ep *ep,540 u8 func_no)541{542 unsigned int dbi_offset = 0;543 544 if (ep->ops->get_dbi_offset)545 dbi_offset = ep->ops->get_dbi_offset(ep, func_no);546 547 return dbi_offset;548}549 550static inline u32 dw_pcie_ep_read_dbi(struct dw_pcie_ep *ep, u8 func_no,551 u32 reg, size_t size)552{553 unsigned int offset = dw_pcie_ep_get_dbi_offset(ep, func_no);554 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);555 556 return dw_pcie_read_dbi(pci, offset + reg, size);557}558 559static inline void dw_pcie_ep_write_dbi(struct dw_pcie_ep *ep, u8 func_no,560 u32 reg, size_t size, u32 val)561{562 unsigned int offset = dw_pcie_ep_get_dbi_offset(ep, func_no);563 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);564 565 dw_pcie_write_dbi(pci, offset + reg, size, val);566}567 568static inline void dw_pcie_ep_writel_dbi(struct dw_pcie_ep *ep, u8 func_no,569 u32 reg, u32 val)570{571 dw_pcie_ep_write_dbi(ep, func_no, reg, 0x4, val);572}573 574static inline u32 dw_pcie_ep_readl_dbi(struct dw_pcie_ep *ep, u8 func_no,575 u32 reg)576{577 return dw_pcie_ep_read_dbi(ep, func_no, reg, 0x4);578}579 580static inline void dw_pcie_ep_writew_dbi(struct dw_pcie_ep *ep, u8 func_no,581 u32 reg, u16 val)582{583 dw_pcie_ep_write_dbi(ep, func_no, reg, 0x2, val);584}585 586static inline u16 dw_pcie_ep_readw_dbi(struct dw_pcie_ep *ep, u8 func_no,587 u32 reg)588{589 return dw_pcie_ep_read_dbi(ep, func_no, reg, 0x2);590}591 592static inline void dw_pcie_ep_writeb_dbi(struct dw_pcie_ep *ep, u8 func_no,593 u32 reg, u8 val)594{595 dw_pcie_ep_write_dbi(ep, func_no, reg, 0x1, val);596}597 598static inline u8 dw_pcie_ep_readb_dbi(struct dw_pcie_ep *ep, u8 func_no,599 u32 reg)600{601 return dw_pcie_ep_read_dbi(ep, func_no, reg, 0x1);602}603 604static inline unsigned int dw_pcie_ep_get_dbi2_offset(struct dw_pcie_ep *ep,605 u8 func_no)606{607 unsigned int dbi2_offset = 0;608 609 if (ep->ops->get_dbi2_offset)610 dbi2_offset = ep->ops->get_dbi2_offset(ep, func_no);611 else if (ep->ops->get_dbi_offset) /* for backward compatibility */612 dbi2_offset = ep->ops->get_dbi_offset(ep, func_no);613 614 return dbi2_offset;615}616 617static inline void dw_pcie_ep_write_dbi2(struct dw_pcie_ep *ep, u8 func_no,618 u32 reg, size_t size, u32 val)619{620 unsigned int offset = dw_pcie_ep_get_dbi2_offset(ep, func_no);621 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);622 623 dw_pcie_write_dbi2(pci, offset + reg, size, val);624}625 626static inline void dw_pcie_ep_writel_dbi2(struct dw_pcie_ep *ep, u8 func_no,627 u32 reg, u32 val)628{629 dw_pcie_ep_write_dbi2(ep, func_no, reg, 0x4, val);630}631 632static inline void dw_pcie_dbi_ro_wr_en(struct dw_pcie *pci)633{634 u32 reg;635 u32 val;636 637 reg = PCIE_MISC_CONTROL_1_OFF;638 val = dw_pcie_readl_dbi(pci, reg);639 val |= PCIE_DBI_RO_WR_EN;640 dw_pcie_writel_dbi(pci, reg, val);641}642 643static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)644{645 u32 reg;646 u32 val;647 648 reg = PCIE_MISC_CONTROL_1_OFF;649 val = dw_pcie_readl_dbi(pci, reg);650 val &= ~PCIE_DBI_RO_WR_EN;651 dw_pcie_writel_dbi(pci, reg, val);652}653 654static inline int dw_pcie_start_link(struct dw_pcie *pci)655{656 if (pci->ops && pci->ops->start_link)657 return pci->ops->start_link(pci);658 659 return 0;660}661 662static inline void dw_pcie_stop_link(struct dw_pcie *pci)663{664 if (pci->ops && pci->ops->stop_link)665 pci->ops->stop_link(pci);666}667 668static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(struct dw_pcie *pci)669{670 u32 val;671 672 if (pci->ops && pci->ops->get_ltssm)673 return pci->ops->get_ltssm(pci);674 675 val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0);676 677 return (enum dw_pcie_ltssm)FIELD_GET(PORT_LOGIC_LTSSM_STATE_MASK, val);678}679 680#ifdef CONFIG_PCIE_DW_HOST681irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp);682int dw_pcie_setup_rc(struct dw_pcie_rp *pp);683int dw_pcie_host_init(struct dw_pcie_rp *pp);684void dw_pcie_host_deinit(struct dw_pcie_rp *pp);685int dw_pcie_allocate_domains(struct dw_pcie_rp *pp);686void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn,687 int where);688#else689static inline irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp)690{691 return IRQ_NONE;692}693 694static inline int dw_pcie_setup_rc(struct dw_pcie_rp *pp)695{696 return 0;697}698 699static inline int dw_pcie_host_init(struct dw_pcie_rp *pp)700{701 return 0;702}703 704static inline void dw_pcie_host_deinit(struct dw_pcie_rp *pp)705{706}707 708static inline int dw_pcie_allocate_domains(struct dw_pcie_rp *pp)709{710 return 0;711}712static inline void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus,713 unsigned int devfn,714 int where)715{716 return NULL;717}718#endif719 720#ifdef CONFIG_PCIE_DW_EP721void dw_pcie_ep_linkup(struct dw_pcie_ep *ep);722void dw_pcie_ep_linkdown(struct dw_pcie_ep *ep);723int dw_pcie_ep_init(struct dw_pcie_ep *ep);724int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep);725void dw_pcie_ep_deinit(struct dw_pcie_ep *ep);726void dw_pcie_ep_cleanup(struct dw_pcie_ep *ep);727int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no);728int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,729 u8 interrupt_num);730int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,731 u16 interrupt_num);732int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no,733 u16 interrupt_num);734void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar);735struct dw_pcie_ep_func *736dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no);737#else738static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)739{740}741 742static inline void dw_pcie_ep_linkdown(struct dw_pcie_ep *ep)743{744}745 746static inline int dw_pcie_ep_init(struct dw_pcie_ep *ep)747{748 return 0;749}750 751static inline int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep)752{753 return 0;754}755 756static inline void dw_pcie_ep_deinit(struct dw_pcie_ep *ep)757{758}759 760static inline void dw_pcie_ep_cleanup(struct dw_pcie_ep *ep)761{762}763 764static inline int dw_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep, u8 func_no)765{766 return 0;767}768 769static inline int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,770 u8 interrupt_num)771{772 return 0;773}774 775static inline int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,776 u16 interrupt_num)777{778 return 0;779}780 781static inline int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep,782 u8 func_no,783 u16 interrupt_num)784{785 return 0;786}787 788static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)789{790}791 792static inline struct dw_pcie_ep_func *793dw_pcie_ep_get_func_from_ep(struct dw_pcie_ep *ep, u8 func_no)794{795 return NULL;796}797#endif798#endif /* _PCIE_DESIGNWARE_H */799