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1// SPDX-License-Identifier: GPL-2.02/*3 * PCIe host controller driver for Rockchip SoCs.4 *5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd.6 * http://www.rock-chips.com7 *8 * Author: Simon Xue <xxm@rock-chips.com>9 */10 11#include <linux/clk.h>12#include <linux/gpio/consumer.h>13#include <linux/irqchip/chained_irq.h>14#include <linux/irqdomain.h>15#include <linux/mfd/syscon.h>16#include <linux/module.h>17#include <linux/of.h>18#include <linux/of_irq.h>19#include <linux/phy/phy.h>20#include <linux/platform_device.h>21#include <linux/regmap.h>22#include <linux/reset.h>23 24#include "pcie-designware.h"25 26/*27 * The upper 16 bits of PCIE_CLIENT_CONFIG are a write28 * mask for the lower 16 bits.29 */30#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))31#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)32#define HIWORD_DISABLE_BIT(val) HIWORD_UPDATE(val, ~val)33 34#define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)35 36#define PCIE_CLIENT_RC_MODE HIWORD_UPDATE_BIT(0x40)37#define PCIE_CLIENT_EP_MODE HIWORD_UPDATE(0xf0, 0x0)38#define PCIE_CLIENT_ENABLE_LTSSM HIWORD_UPDATE_BIT(0xc)39#define PCIE_CLIENT_DISABLE_LTSSM HIWORD_UPDATE(0x0c, 0x8)40#define PCIE_CLIENT_INTR_STATUS_MISC 0x1041#define PCIE_CLIENT_INTR_MASK_MISC 0x2442#define PCIE_SMLH_LINKUP BIT(16)43#define PCIE_RDLH_LINKUP BIT(17)44#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP)45#define PCIE_RDLH_LINK_UP_CHGED BIT(1)46#define PCIE_LINK_REQ_RST_NOT_INT BIT(2)47#define PCIE_L0S_ENTRY 0x1148#define PCIE_CLIENT_GENERAL_CONTROL 0x049#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x850#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c51#define PCIE_CLIENT_GENERAL_DEBUG 0x10452#define PCIE_CLIENT_HOT_RESET_CTRL 0x18053#define PCIE_CLIENT_LTSSM_STATUS 0x30054#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)55#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0)56 57struct rockchip_pcie {58 struct dw_pcie pci;59 void __iomem *apb_base;60 struct phy *phy;61 struct clk_bulk_data *clks;62 unsigned int clk_cnt;63 struct reset_control *rst;64 struct gpio_desc *rst_gpio;65 struct regulator *vpcie3v3;66 struct irq_domain *irq_domain;67 const struct rockchip_pcie_of_data *data;68};69 70struct rockchip_pcie_of_data {71 enum dw_pcie_device_mode mode;72 const struct pci_epc_features *epc_features;73};74 75static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip, u32 reg)76{77 return readl_relaxed(rockchip->apb_base + reg);78}79 80static void rockchip_pcie_writel_apb(struct rockchip_pcie *rockchip, u32 val,81 u32 reg)82{83 writel_relaxed(val, rockchip->apb_base + reg);84}85 86static void rockchip_pcie_intx_handler(struct irq_desc *desc)87{88 struct irq_chip *chip = irq_desc_get_chip(desc);89 struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);90 unsigned long reg, hwirq;91 92 chained_irq_enter(chip, desc);93 94 reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_LEGACY);95 96 for_each_set_bit(hwirq, ®, 4)97 generic_handle_domain_irq(rockchip->irq_domain, hwirq);98 99 chained_irq_exit(chip, desc);100}101 102static void rockchip_intx_mask(struct irq_data *data)103{104 rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data),105 HIWORD_UPDATE_BIT(BIT(data->hwirq)),106 PCIE_CLIENT_INTR_MASK_LEGACY);107};108 109static void rockchip_intx_unmask(struct irq_data *data)110{111 rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data),112 HIWORD_DISABLE_BIT(BIT(data->hwirq)),113 PCIE_CLIENT_INTR_MASK_LEGACY);114};115 116static struct irq_chip rockchip_intx_irq_chip = {117 .name = "INTx",118 .irq_mask = rockchip_intx_mask,119 .irq_unmask = rockchip_intx_unmask,120 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,121};122 123static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,124 irq_hw_number_t hwirq)125{126 irq_set_chip_and_handler(irq, &rockchip_intx_irq_chip, handle_level_irq);127 irq_set_chip_data(irq, domain->host_data);128 129 return 0;130}131 132static const struct irq_domain_ops intx_domain_ops = {133 .map = rockchip_pcie_intx_map,134};135 136static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)137{138 struct device *dev = rockchip->pci.dev;139 struct device_node *intc;140 141 intc = of_get_child_by_name(dev->of_node, "legacy-interrupt-controller");142 if (!intc) {143 dev_err(dev, "missing child interrupt-controller node\n");144 return -EINVAL;145 }146 147 rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX,148 &intx_domain_ops, rockchip);149 of_node_put(intc);150 if (!rockchip->irq_domain) {151 dev_err(dev, "failed to get a INTx IRQ domain\n");152 return -EINVAL;153 }154 155 return 0;156}157 158static u32 rockchip_pcie_get_ltssm(struct rockchip_pcie *rockchip)159{160 return rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS);161}162 163static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)164{165 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM,166 PCIE_CLIENT_GENERAL_CONTROL);167}168 169static void rockchip_pcie_disable_ltssm(struct rockchip_pcie *rockchip)170{171 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_DISABLE_LTSSM,172 PCIE_CLIENT_GENERAL_CONTROL);173}174 175static int rockchip_pcie_link_up(struct dw_pcie *pci)176{177 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);178 u32 val = rockchip_pcie_get_ltssm(rockchip);179 180 if ((val & PCIE_LINKUP) == PCIE_LINKUP &&181 (val & PCIE_LTSSM_STATUS_MASK) == PCIE_L0S_ENTRY)182 return 1;183 184 return 0;185}186 187static int rockchip_pcie_start_link(struct dw_pcie *pci)188{189 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);190 191 /* Reset device */192 gpiod_set_value_cansleep(rockchip->rst_gpio, 0);193 194 rockchip_pcie_enable_ltssm(rockchip);195 196 /*197 * PCIe requires the refclk to be stable for 100µs prior to releasing198 * PERST. See table 2-4 in section 2.6.2 AC Specifications of the PCI199 * Express Card Electromechanical Specification, 1.1. However, we don't200 * know if the refclk is coming from RC's PHY or external OSC. If it's201 * from RC, so enabling LTSSM is the just right place to release #PERST.202 * We need more extra time as before, rather than setting just203 * 100us as we don't know how long should the device need to reset.204 */205 msleep(100);206 gpiod_set_value_cansleep(rockchip->rst_gpio, 1);207 208 return 0;209}210 211static void rockchip_pcie_stop_link(struct dw_pcie *pci)212{213 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);214 215 rockchip_pcie_disable_ltssm(rockchip);216}217 218static int rockchip_pcie_host_init(struct dw_pcie_rp *pp)219{220 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);221 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);222 struct device *dev = rockchip->pci.dev;223 int irq, ret;224 225 irq = of_irq_get_byname(dev->of_node, "legacy");226 if (irq < 0)227 return irq;228 229 ret = rockchip_pcie_init_irq_domain(rockchip);230 if (ret < 0)231 dev_err(dev, "failed to init irq domain\n");232 233 irq_set_chained_handler_and_data(irq, rockchip_pcie_intx_handler,234 rockchip);235 236 return 0;237}238 239static const struct dw_pcie_host_ops rockchip_pcie_host_ops = {240 .init = rockchip_pcie_host_init,241};242 243static void rockchip_pcie_ep_init(struct dw_pcie_ep *ep)244{245 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);246 enum pci_barno bar;247 248 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)249 dw_pcie_ep_reset_bar(pci, bar);250};251 252static int rockchip_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,253 unsigned int type, u16 interrupt_num)254{255 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);256 257 switch (type) {258 case PCI_IRQ_INTX:259 return dw_pcie_ep_raise_intx_irq(ep, func_no);260 case PCI_IRQ_MSI:261 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);262 case PCI_IRQ_MSIX:263 return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);264 default:265 dev_err(pci->dev, "UNKNOWN IRQ type\n");266 }267 268 return 0;269}270 271static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = {272 .linkup_notifier = true,273 .msi_capable = true,274 .msix_capable = true,275 .align = SZ_64K,276 .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },277 .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },278 .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },279 .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },280 .bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },281 .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },282};283 284/*285 * BAR4 on rk3588 exposes the ATU Port Logic Structure to the host regardless of286 * iATU settings for BAR4. This means that BAR4 cannot be used by an EPF driver,287 * so mark it as RESERVED. (rockchip_pcie_ep_init() will disable all BARs by288 * default.) If the host could write to BAR4, the iATU settings (for all other289 * BARs) would be overwritten, resulting in (all other BARs) no longer working.290 */291static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = {292 .linkup_notifier = true,293 .msi_capable = true,294 .msix_capable = true,295 .align = SZ_64K,296 .bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },297 .bar[BAR_1] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },298 .bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },299 .bar[BAR_3] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },300 .bar[BAR_4] = { .type = BAR_RESERVED, },301 .bar[BAR_5] = { .type = BAR_FIXED, .fixed_size = SZ_1M, },302};303 304static const struct pci_epc_features *305rockchip_pcie_get_features(struct dw_pcie_ep *ep)306{307 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);308 struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);309 310 return rockchip->data->epc_features;311}312 313static const struct dw_pcie_ep_ops rockchip_pcie_ep_ops = {314 .init = rockchip_pcie_ep_init,315 .raise_irq = rockchip_pcie_raise_irq,316 .get_features = rockchip_pcie_get_features,317};318 319static int rockchip_pcie_clk_init(struct rockchip_pcie *rockchip)320{321 struct device *dev = rockchip->pci.dev;322 int ret;323 324 ret = devm_clk_bulk_get_all(dev, &rockchip->clks);325 if (ret < 0)326 return dev_err_probe(dev, ret, "failed to get clocks\n");327 328 rockchip->clk_cnt = ret;329 330 ret = clk_bulk_prepare_enable(rockchip->clk_cnt, rockchip->clks);331 if (ret)332 return dev_err_probe(dev, ret, "failed to enable clocks\n");333 334 return 0;335}336 337static int rockchip_pcie_resource_get(struct platform_device *pdev,338 struct rockchip_pcie *rockchip)339{340 rockchip->apb_base = devm_platform_ioremap_resource_byname(pdev, "apb");341 if (IS_ERR(rockchip->apb_base))342 return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->apb_base),343 "failed to map apb registers\n");344 345 rockchip->rst_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",346 GPIOD_OUT_LOW);347 if (IS_ERR(rockchip->rst_gpio))348 return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst_gpio),349 "failed to get reset gpio\n");350 351 rockchip->rst = devm_reset_control_array_get_exclusive(&pdev->dev);352 if (IS_ERR(rockchip->rst))353 return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst),354 "failed to get reset lines\n");355 356 return 0;357}358 359static int rockchip_pcie_phy_init(struct rockchip_pcie *rockchip)360{361 struct device *dev = rockchip->pci.dev;362 int ret;363 364 rockchip->phy = devm_phy_get(dev, "pcie-phy");365 if (IS_ERR(rockchip->phy))366 return dev_err_probe(dev, PTR_ERR(rockchip->phy),367 "missing PHY\n");368 369 ret = phy_init(rockchip->phy);370 if (ret < 0)371 return ret;372 373 ret = phy_power_on(rockchip->phy);374 if (ret)375 phy_exit(rockchip->phy);376 377 return ret;378}379 380static void rockchip_pcie_phy_deinit(struct rockchip_pcie *rockchip)381{382 phy_exit(rockchip->phy);383 phy_power_off(rockchip->phy);384}385 386static const struct dw_pcie_ops dw_pcie_ops = {387 .link_up = rockchip_pcie_link_up,388 .start_link = rockchip_pcie_start_link,389 .stop_link = rockchip_pcie_stop_link,390};391 392static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg)393{394 struct rockchip_pcie *rockchip = arg;395 struct dw_pcie *pci = &rockchip->pci;396 struct device *dev = pci->dev;397 u32 reg, val;398 399 reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC);400 rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);401 402 dev_dbg(dev, "PCIE_CLIENT_INTR_STATUS_MISC: %#x\n", reg);403 dev_dbg(dev, "LTSSM_STATUS: %#x\n", rockchip_pcie_get_ltssm(rockchip));404 405 if (reg & PCIE_LINK_REQ_RST_NOT_INT) {406 dev_dbg(dev, "hot reset or link-down reset\n");407 dw_pcie_ep_linkdown(&pci->ep);408 }409 410 if (reg & PCIE_RDLH_LINK_UP_CHGED) {411 val = rockchip_pcie_get_ltssm(rockchip);412 if ((val & PCIE_LINKUP) == PCIE_LINKUP) {413 dev_dbg(dev, "link up\n");414 dw_pcie_ep_linkup(&pci->ep);415 }416 }417 418 return IRQ_HANDLED;419}420 421static int rockchip_pcie_configure_rc(struct rockchip_pcie *rockchip)422{423 struct dw_pcie_rp *pp;424 u32 val;425 426 if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_HOST))427 return -ENODEV;428 429 /* LTSSM enable control mode */430 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);431 rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);432 433 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE,434 PCIE_CLIENT_GENERAL_CONTROL);435 436 pp = &rockchip->pci.pp;437 pp->ops = &rockchip_pcie_host_ops;438 439 return dw_pcie_host_init(pp);440}441 442static int rockchip_pcie_configure_ep(struct platform_device *pdev,443 struct rockchip_pcie *rockchip)444{445 struct device *dev = &pdev->dev;446 int irq, ret;447 u32 val;448 449 if (!IS_ENABLED(CONFIG_PCIE_ROCKCHIP_DW_EP))450 return -ENODEV;451 452 irq = platform_get_irq_byname(pdev, "sys");453 if (irq < 0) {454 dev_err(dev, "missing sys IRQ resource\n");455 return irq;456 }457 458 ret = devm_request_threaded_irq(dev, irq, NULL,459 rockchip_pcie_ep_sys_irq_thread,460 IRQF_ONESHOT, "pcie-sys", rockchip);461 if (ret) {462 dev_err(dev, "failed to request PCIe sys IRQ\n");463 return ret;464 }465 466 /* LTSSM enable control mode */467 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);468 rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);469 470 rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_EP_MODE,471 PCIE_CLIENT_GENERAL_CONTROL);472 473 rockchip->pci.ep.ops = &rockchip_pcie_ep_ops;474 rockchip->pci.ep.page_size = SZ_64K;475 476 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));477 478 ret = dw_pcie_ep_init(&rockchip->pci.ep);479 if (ret) {480 dev_err(dev, "failed to initialize endpoint\n");481 return ret;482 }483 484 ret = dw_pcie_ep_init_registers(&rockchip->pci.ep);485 if (ret) {486 dev_err(dev, "failed to initialize DWC endpoint registers\n");487 dw_pcie_ep_deinit(&rockchip->pci.ep);488 return ret;489 }490 491 pci_epc_init_notify(rockchip->pci.ep.epc);492 493 /* unmask DLL up/down indicator and hot reset/link-down reset */494 rockchip_pcie_writel_apb(rockchip, 0x60000, PCIE_CLIENT_INTR_MASK_MISC);495 496 return ret;497}498 499static int rockchip_pcie_probe(struct platform_device *pdev)500{501 struct device *dev = &pdev->dev;502 struct rockchip_pcie *rockchip;503 const struct rockchip_pcie_of_data *data;504 int ret;505 506 data = of_device_get_match_data(dev);507 if (!data)508 return -EINVAL;509 510 rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);511 if (!rockchip)512 return -ENOMEM;513 514 platform_set_drvdata(pdev, rockchip);515 516 rockchip->pci.dev = dev;517 rockchip->pci.ops = &dw_pcie_ops;518 rockchip->data = data;519 520 ret = rockchip_pcie_resource_get(pdev, rockchip);521 if (ret)522 return ret;523 524 ret = reset_control_assert(rockchip->rst);525 if (ret)526 return ret;527 528 /* DON'T MOVE ME: must be enable before PHY init */529 rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");530 if (IS_ERR(rockchip->vpcie3v3)) {531 if (PTR_ERR(rockchip->vpcie3v3) != -ENODEV)532 return dev_err_probe(dev, PTR_ERR(rockchip->vpcie3v3),533 "failed to get vpcie3v3 regulator\n");534 rockchip->vpcie3v3 = NULL;535 } else {536 ret = regulator_enable(rockchip->vpcie3v3);537 if (ret)538 return dev_err_probe(dev, ret,539 "failed to enable vpcie3v3 regulator\n");540 }541 542 ret = rockchip_pcie_phy_init(rockchip);543 if (ret)544 goto disable_regulator;545 546 ret = reset_control_deassert(rockchip->rst);547 if (ret)548 goto deinit_phy;549 550 ret = rockchip_pcie_clk_init(rockchip);551 if (ret)552 goto deinit_phy;553 554 switch (data->mode) {555 case DW_PCIE_RC_TYPE:556 ret = rockchip_pcie_configure_rc(rockchip);557 if (ret)558 goto deinit_clk;559 break;560 case DW_PCIE_EP_TYPE:561 ret = rockchip_pcie_configure_ep(pdev, rockchip);562 if (ret)563 goto deinit_clk;564 break;565 default:566 dev_err(dev, "INVALID device type %d\n", data->mode);567 ret = -EINVAL;568 goto deinit_clk;569 }570 571 return 0;572 573deinit_clk:574 clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks);575deinit_phy:576 rockchip_pcie_phy_deinit(rockchip);577disable_regulator:578 if (rockchip->vpcie3v3)579 regulator_disable(rockchip->vpcie3v3);580 581 return ret;582}583 584static const struct rockchip_pcie_of_data rockchip_pcie_rc_of_data_rk3568 = {585 .mode = DW_PCIE_RC_TYPE,586};587 588static const struct rockchip_pcie_of_data rockchip_pcie_ep_of_data_rk3568 = {589 .mode = DW_PCIE_EP_TYPE,590 .epc_features = &rockchip_pcie_epc_features_rk3568,591};592 593static const struct rockchip_pcie_of_data rockchip_pcie_ep_of_data_rk3588 = {594 .mode = DW_PCIE_EP_TYPE,595 .epc_features = &rockchip_pcie_epc_features_rk3588,596};597 598static const struct of_device_id rockchip_pcie_of_match[] = {599 {600 .compatible = "rockchip,rk3568-pcie",601 .data = &rockchip_pcie_rc_of_data_rk3568,602 },603 {604 .compatible = "rockchip,rk3568-pcie-ep",605 .data = &rockchip_pcie_ep_of_data_rk3568,606 },607 {608 .compatible = "rockchip,rk3588-pcie-ep",609 .data = &rockchip_pcie_ep_of_data_rk3588,610 },611 {},612};613 614static struct platform_driver rockchip_pcie_driver = {615 .driver = {616 .name = "rockchip-dw-pcie",617 .of_match_table = rockchip_pcie_of_match,618 .suppress_bind_attrs = true,619 },620 .probe = rockchip_pcie_probe,621};622builtin_platform_driver(rockchip_pcie_driver);623