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1// SPDX-License-Identifier: GPL-2.02/*3 * Qualcomm PCIe Endpoint controller driver4 *5 * Copyright (c) 2020, The Linux Foundation. All rights reserved.6 * Author: Siddartha Mohanadoss <smohanad@codeaurora.org7 *8 * Copyright (c) 2021, Linaro Ltd.9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org10 */11 12#include <linux/clk.h>13#include <linux/debugfs.h>14#include <linux/delay.h>15#include <linux/gpio/consumer.h>16#include <linux/interconnect.h>17#include <linux/mfd/syscon.h>18#include <linux/phy/pcie.h>19#include <linux/phy/phy.h>20#include <linux/platform_device.h>21#include <linux/pm_domain.h>22#include <linux/regmap.h>23#include <linux/reset.h>24#include <linux/module.h>25 26#include "../../pci.h"27#include "pcie-designware.h"28#include "pcie-qcom-common.h"29 30/* PARF registers */31#define PARF_SYS_CTRL 0x0032#define PARF_DB_CTRL 0x1033#define PARF_PM_CTRL 0x2034#define PARF_MHI_CLOCK_RESET_CTRL 0x17435#define PARF_MHI_BASE_ADDR_LOWER 0x17836#define PARF_MHI_BASE_ADDR_UPPER 0x17c37#define PARF_DEBUG_INT_EN 0x19038#define PARF_AXI_MSTR_RD_HALT_NO_WRITES 0x1a439#define PARF_AXI_MSTR_WR_ADDR_HALT 0x1a840#define PARF_Q2A_FLUSH 0x1ac41#define PARF_LTSSM 0x1b042#define PARF_CFG_BITS 0x21043#define PARF_INT_ALL_STATUS 0x22444#define PARF_INT_ALL_CLEAR 0x22845#define PARF_INT_ALL_MASK 0x22c46#define PARF_SLV_ADDR_MSB_CTRL 0x2c047#define PARF_DBI_BASE_ADDR 0x35048#define PARF_DBI_BASE_ADDR_HI 0x35449#define PARF_SLV_ADDR_SPACE_SIZE 0x35850#define PARF_SLV_ADDR_SPACE_SIZE_HI 0x35c51#define PARF_NO_SNOOP_OVERIDE 0x3d452#define PARF_ATU_BASE_ADDR 0x63453#define PARF_ATU_BASE_ADDR_HI 0x63854#define PARF_SRIS_MODE 0x64455#define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc0456#define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c57#define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc1058#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc8459#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc8860#define PARF_DEVICE_TYPE 0x100061#define PARF_BDF_TO_SID_CFG 0x2c0062#define PARF_INT_ALL_5_MASK 0x2dcc63 64/* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */65#define PARF_INT_ALL_LINK_DOWN BIT(1)66#define PARF_INT_ALL_BME BIT(2)67#define PARF_INT_ALL_PM_TURNOFF BIT(3)68#define PARF_INT_ALL_DEBUG BIT(4)69#define PARF_INT_ALL_LTR BIT(5)70#define PARF_INT_ALL_MHI_Q6 BIT(6)71#define PARF_INT_ALL_MHI_A7 BIT(7)72#define PARF_INT_ALL_DSTATE_CHANGE BIT(8)73#define PARF_INT_ALL_L1SUB_TIMEOUT BIT(9)74#define PARF_INT_ALL_MMIO_WRITE BIT(10)75#define PARF_INT_ALL_CFG_WRITE BIT(11)76#define PARF_INT_ALL_BRIDGE_FLUSH_N BIT(12)77#define PARF_INT_ALL_LINK_UP BIT(13)78#define PARF_INT_ALL_AER_LEGACY BIT(14)79#define PARF_INT_ALL_PLS_ERR BIT(15)80#define PARF_INT_ALL_PME_LEGACY BIT(16)81#define PARF_INT_ALL_PLS_PME BIT(17)82#define PARF_INT_ALL_EDMA BIT(22)83 84/* PARF_BDF_TO_SID_CFG register fields */85#define PARF_BDF_TO_SID_BYPASS BIT(0)86 87/* PARF_DEBUG_INT_EN register fields */88#define PARF_DEBUG_INT_PM_DSTATE_CHANGE BIT(1)89#define PARF_DEBUG_INT_CFG_BUS_MASTER_EN BIT(2)90#define PARF_DEBUG_INT_RADM_PM_TURNOFF BIT(3)91 92/* PARF_NO_SNOOP_OVERIDE register fields */93#define WR_NO_SNOOP_OVERIDE_EN BIT(1)94#define RD_NO_SNOOP_OVERIDE_EN BIT(3)95 96/* PARF_DEVICE_TYPE register fields */97#define PARF_DEVICE_TYPE_EP 0x098 99/* PARF_PM_CTRL register fields */100#define PARF_PM_CTRL_REQ_EXIT_L1 BIT(1)101#define PARF_PM_CTRL_READY_ENTR_L23 BIT(2)102#define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5)103 104/* PARF_MHI_CLOCK_RESET_CTRL fields */105#define PARF_MSTR_AXI_CLK_EN BIT(1)106 107/* PARF_AXI_MSTR_RD_HALT_NO_WRITES register fields */108#define PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN BIT(0)109 110/* PARF_AXI_MSTR_WR_ADDR_HALT register fields */111#define PARF_AXI_MSTR_WR_ADDR_HALT_EN BIT(31)112 113/* PARF_Q2A_FLUSH register fields */114#define PARF_Q2A_FLUSH_EN BIT(16)115 116/* PARF_SYS_CTRL register fields */117#define PARF_SYS_CTRL_AUX_PWR_DET BIT(4)118#define PARF_SYS_CTRL_CORE_CLK_CGC_DIS BIT(6)119#define PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS BIT(10)120#define PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE BIT(11)121 122/* PARF_DB_CTRL register fields */123#define PARF_DB_CTRL_INSR_DBNCR_BLOCK BIT(0)124#define PARF_DB_CTRL_RMVL_DBNCR_BLOCK BIT(1)125#define PARF_DB_CTRL_DBI_WKP_BLOCK BIT(4)126#define PARF_DB_CTRL_SLV_WKP_BLOCK BIT(5)127#define PARF_DB_CTRL_MST_WKP_BLOCK BIT(6)128 129/* PARF_CFG_BITS register fields */130#define PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN BIT(1)131 132/* PARF_INT_ALL_5_MASK fields */133#define PARF_INT_ALL_5_MHI_RAM_DATA_PARITY_ERR BIT(0)134 135/* ELBI registers */136#define ELBI_SYS_STTS 0x08137#define ELBI_CS2_ENABLE 0xa4138 139/* DBI registers */140#define DBI_CON_STATUS 0x44141 142/* DBI register fields */143#define DBI_CON_STATUS_POWER_STATE_MASK GENMASK(1, 0)144 145#define XMLH_LINK_UP 0x400146#define CORE_RESET_TIME_US_MIN 1000147#define CORE_RESET_TIME_US_MAX 1005148#define WAKE_DELAY_US 2000 /* 2 ms */149 150#define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \151 Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]))152 153#define to_pcie_ep(x) dev_get_drvdata((x)->dev)154 155enum qcom_pcie_ep_link_status {156 QCOM_PCIE_EP_LINK_DISABLED,157 QCOM_PCIE_EP_LINK_ENABLED,158 QCOM_PCIE_EP_LINK_UP,159 QCOM_PCIE_EP_LINK_DOWN,160};161 162/**163 * struct qcom_pcie_ep_cfg - Per SoC config struct164 * @hdma_support: HDMA support on this SoC165 * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache snooping166 * @disable_mhi_ram_parity_check: Disable MHI RAM data parity error check167 */168struct qcom_pcie_ep_cfg {169 bool hdma_support;170 bool override_no_snoop;171 bool disable_mhi_ram_parity_check;172};173 174/**175 * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller176 * @pci: Designware PCIe controller struct177 * @parf: Qualcomm PCIe specific PARF register base178 * @elbi: Designware PCIe specific ELBI register base179 * @mmio: MMIO register base180 * @perst_map: PERST regmap181 * @mmio_res: MMIO region resource182 * @core_reset: PCIe Endpoint core reset183 * @reset: PERST# GPIO184 * @wake: WAKE# GPIO185 * @phy: PHY controller block186 * @debugfs: PCIe Endpoint Debugfs directory187 * @icc_mem: Handle to an interconnect path between PCIe and MEM188 * @clks: PCIe clocks189 * @num_clks: PCIe clocks count190 * @perst_en: Flag for PERST enable191 * @perst_sep_en: Flag for PERST separation enable192 * @cfg: PCIe EP config struct193 * @link_status: PCIe Link status194 * @global_irq: Qualcomm PCIe specific Global IRQ195 * @perst_irq: PERST# IRQ196 */197struct qcom_pcie_ep {198 struct dw_pcie pci;199 200 void __iomem *parf;201 void __iomem *elbi;202 void __iomem *mmio;203 struct regmap *perst_map;204 struct resource *mmio_res;205 206 struct reset_control *core_reset;207 struct gpio_desc *reset;208 struct gpio_desc *wake;209 struct phy *phy;210 struct dentry *debugfs;211 212 struct icc_path *icc_mem;213 214 struct clk_bulk_data *clks;215 int num_clks;216 217 u32 perst_en;218 u32 perst_sep_en;219 220 const struct qcom_pcie_ep_cfg *cfg;221 enum qcom_pcie_ep_link_status link_status;222 int global_irq;223 int perst_irq;224};225 226static int qcom_pcie_ep_core_reset(struct qcom_pcie_ep *pcie_ep)227{228 struct dw_pcie *pci = &pcie_ep->pci;229 struct device *dev = pci->dev;230 int ret;231 232 ret = reset_control_assert(pcie_ep->core_reset);233 if (ret) {234 dev_err(dev, "Cannot assert core reset\n");235 return ret;236 }237 238 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX);239 240 ret = reset_control_deassert(pcie_ep->core_reset);241 if (ret) {242 dev_err(dev, "Cannot de-assert core reset\n");243 return ret;244 }245 246 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX);247 248 return 0;249}250 251/*252 * Delatch PERST_EN and PERST_SEPARATION_ENABLE with TCSR to avoid253 * device reset during host reboot and hibernation. The driver is254 * expected to handle this situation.255 */256static void qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep *pcie_ep)257{258 if (pcie_ep->perst_map) {259 regmap_write(pcie_ep->perst_map, pcie_ep->perst_en, 0);260 regmap_write(pcie_ep->perst_map, pcie_ep->perst_sep_en, 0);261 }262}263 264static int qcom_pcie_dw_link_up(struct dw_pcie *pci)265{266 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);267 u32 reg;268 269 reg = readl_relaxed(pcie_ep->elbi + ELBI_SYS_STTS);270 271 return reg & XMLH_LINK_UP;272}273 274static int qcom_pcie_dw_start_link(struct dw_pcie *pci)275{276 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);277 278 enable_irq(pcie_ep->perst_irq);279 280 return 0;281}282 283static void qcom_pcie_dw_stop_link(struct dw_pcie *pci)284{285 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);286 287 disable_irq(pcie_ep->perst_irq);288}289 290static void qcom_pcie_dw_write_dbi2(struct dw_pcie *pci, void __iomem *base,291 u32 reg, size_t size, u32 val)292{293 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);294 int ret;295 296 writel(1, pcie_ep->elbi + ELBI_CS2_ENABLE);297 298 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val);299 if (ret)300 dev_err(pci->dev, "Failed to write DBI2 register (0x%x): %d\n", reg, ret);301 302 writel(0, pcie_ep->elbi + ELBI_CS2_ENABLE);303}304 305static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep)306{307 struct dw_pcie *pci = &pcie_ep->pci;308 u32 offset, status;309 int speed, width;310 int ret;311 312 if (!pcie_ep->icc_mem)313 return;314 315 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);316 status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);317 318 speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status);319 width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status);320 321 ret = icc_set_bw(pcie_ep->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed));322 if (ret)323 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",324 ret);325}326 327static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)328{329 struct dw_pcie *pci = &pcie_ep->pci;330 int ret;331 332 ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks);333 if (ret)334 return ret;335 336 ret = qcom_pcie_ep_core_reset(pcie_ep);337 if (ret)338 goto err_disable_clk;339 340 ret = phy_init(pcie_ep->phy);341 if (ret)342 goto err_disable_clk;343 344 ret = phy_set_mode_ext(pcie_ep->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_EP);345 if (ret)346 goto err_phy_exit;347 348 ret = phy_power_on(pcie_ep->phy);349 if (ret)350 goto err_phy_exit;351 352 /*353 * Some Qualcomm platforms require interconnect bandwidth constraints354 * to be set before enabling interconnect clocks.355 *356 * Set an initial peak bandwidth corresponding to single-lane Gen 1357 * for the pcie-mem path.358 */359 ret = icc_set_bw(pcie_ep->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1));360 if (ret) {361 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",362 ret);363 goto err_phy_off;364 }365 366 return 0;367 368err_phy_off:369 phy_power_off(pcie_ep->phy);370err_phy_exit:371 phy_exit(pcie_ep->phy);372err_disable_clk:373 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks);374 375 return ret;376}377 378static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep)379{380 icc_set_bw(pcie_ep->icc_mem, 0, 0);381 phy_power_off(pcie_ep->phy);382 phy_exit(pcie_ep->phy);383 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks);384}385 386static int qcom_pcie_perst_deassert(struct dw_pcie *pci)387{388 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);389 struct device *dev = pci->dev;390 u32 val, offset;391 int ret;392 393 ret = qcom_pcie_enable_resources(pcie_ep);394 if (ret) {395 dev_err(dev, "Failed to enable resources: %d\n", ret);396 return ret;397 }398 399 /* Assert WAKE# to RC to indicate device is ready */400 gpiod_set_value_cansleep(pcie_ep->wake, 1);401 usleep_range(WAKE_DELAY_US, WAKE_DELAY_US + 500);402 gpiod_set_value_cansleep(pcie_ep->wake, 0);403 404 qcom_pcie_ep_configure_tcsr(pcie_ep);405 406 /* Disable BDF to SID mapping */407 val = readl_relaxed(pcie_ep->parf + PARF_BDF_TO_SID_CFG);408 val |= PARF_BDF_TO_SID_BYPASS;409 writel_relaxed(val, pcie_ep->parf + PARF_BDF_TO_SID_CFG);410 411 /* Enable debug IRQ */412 val = readl_relaxed(pcie_ep->parf + PARF_DEBUG_INT_EN);413 val |= PARF_DEBUG_INT_RADM_PM_TURNOFF |414 PARF_DEBUG_INT_CFG_BUS_MASTER_EN |415 PARF_DEBUG_INT_PM_DSTATE_CHANGE;416 writel_relaxed(val, pcie_ep->parf + PARF_DEBUG_INT_EN);417 418 /* Configure PCIe to endpoint mode */419 writel_relaxed(PARF_DEVICE_TYPE_EP, pcie_ep->parf + PARF_DEVICE_TYPE);420 421 /* Allow entering L1 state */422 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);423 val &= ~PARF_PM_CTRL_REQ_NOT_ENTR_L1;424 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);425 426 /* Read halts write */427 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES);428 val &= ~PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN;429 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES);430 431 /* Write after write halt */432 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT);433 val |= PARF_AXI_MSTR_WR_ADDR_HALT_EN;434 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT);435 436 /* Q2A flush disable */437 val = readl_relaxed(pcie_ep->parf + PARF_Q2A_FLUSH);438 val &= ~PARF_Q2A_FLUSH_EN;439 writel_relaxed(val, pcie_ep->parf + PARF_Q2A_FLUSH);440 441 /*442 * Disable Master AXI clock during idle. Do not allow DBI access443 * to take the core out of L1. Disable core clock gating that444 * gates PIPE clock from propagating to core clock. Report to the445 * host that Vaux is present.446 */447 val = readl_relaxed(pcie_ep->parf + PARF_SYS_CTRL);448 val &= ~PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS;449 val |= PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE |450 PARF_SYS_CTRL_CORE_CLK_CGC_DIS |451 PARF_SYS_CTRL_AUX_PWR_DET;452 writel_relaxed(val, pcie_ep->parf + PARF_SYS_CTRL);453 454 /* Disable the debouncers */455 val = readl_relaxed(pcie_ep->parf + PARF_DB_CTRL);456 val |= PARF_DB_CTRL_INSR_DBNCR_BLOCK | PARF_DB_CTRL_RMVL_DBNCR_BLOCK |457 PARF_DB_CTRL_DBI_WKP_BLOCK | PARF_DB_CTRL_SLV_WKP_BLOCK |458 PARF_DB_CTRL_MST_WKP_BLOCK;459 writel_relaxed(val, pcie_ep->parf + PARF_DB_CTRL);460 461 /* Request to exit from L1SS for MSI and LTR MSG */462 val = readl_relaxed(pcie_ep->parf + PARF_CFG_BITS);463 val |= PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN;464 writel_relaxed(val, pcie_ep->parf + PARF_CFG_BITS);465 466 dw_pcie_dbi_ro_wr_en(pci);467 468 /* Set the L0s Exit Latency to 2us-4us = 0x6 */469 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);470 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);471 val &= ~PCI_EXP_LNKCAP_L0SEL;472 val |= FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6);473 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);474 475 /* Set the L1 Exit Latency to be 32us-64 us = 0x6 */476 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);477 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);478 val &= ~PCI_EXP_LNKCAP_L1EL;479 val |= FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6);480 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);481 482 dw_pcie_dbi_ro_wr_dis(pci);483 484 writel_relaxed(0, pcie_ep->parf + PARF_INT_ALL_MASK);485 val = PARF_INT_ALL_LINK_DOWN | PARF_INT_ALL_BME |486 PARF_INT_ALL_PM_TURNOFF | PARF_INT_ALL_DSTATE_CHANGE |487 PARF_INT_ALL_LINK_UP | PARF_INT_ALL_EDMA;488 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK);489 490 if (pcie_ep->cfg && pcie_ep->cfg->disable_mhi_ram_parity_check) {491 val = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_5_MASK);492 val &= ~PARF_INT_ALL_5_MHI_RAM_DATA_PARITY_ERR;493 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_5_MASK);494 }495 496 ret = dw_pcie_ep_init_registers(&pcie_ep->pci.ep);497 if (ret) {498 dev_err(dev, "Failed to complete initialization: %d\n", ret);499 goto err_disable_resources;500 }501 502 if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) {503 qcom_pcie_common_set_16gt_equalization(pci);504 qcom_pcie_common_set_16gt_lane_margining(pci);505 }506 507 /*508 * The physical address of the MMIO region which is exposed as the BAR509 * should be written to MHI BASE registers.510 */511 writel_relaxed(pcie_ep->mmio_res->start,512 pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER);513 writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER);514 515 /* Gate Master AXI clock to MHI bus during L1SS */516 val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);517 val &= ~PARF_MSTR_AXI_CLK_EN;518 writel_relaxed(val, pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);519 520 pci_epc_init_notify(pcie_ep->pci.ep.epc);521 522 /* Enable LTSSM */523 val = readl_relaxed(pcie_ep->parf + PARF_LTSSM);524 val |= BIT(8);525 writel_relaxed(val, pcie_ep->parf + PARF_LTSSM);526 527 if (pcie_ep->cfg && pcie_ep->cfg->override_no_snoop)528 writel_relaxed(WR_NO_SNOOP_OVERIDE_EN | RD_NO_SNOOP_OVERIDE_EN,529 pcie_ep->parf + PARF_NO_SNOOP_OVERIDE);530 531 return 0;532 533err_disable_resources:534 qcom_pcie_disable_resources(pcie_ep);535 536 return ret;537}538 539static void qcom_pcie_perst_assert(struct dw_pcie *pci)540{541 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);542 543 pci_epc_deinit_notify(pci->ep.epc);544 dw_pcie_ep_cleanup(&pci->ep);545 qcom_pcie_disable_resources(pcie_ep);546 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED;547}548 549/* Common DWC controller ops */550static const struct dw_pcie_ops pci_ops = {551 .link_up = qcom_pcie_dw_link_up,552 .start_link = qcom_pcie_dw_start_link,553 .stop_link = qcom_pcie_dw_stop_link,554 .write_dbi2 = qcom_pcie_dw_write_dbi2,555};556 557static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev,558 struct qcom_pcie_ep *pcie_ep)559{560 struct device *dev = &pdev->dev;561 struct dw_pcie *pci = &pcie_ep->pci;562 struct device_node *syscon;563 struct resource *res;564 int ret;565 566 pcie_ep->parf = devm_platform_ioremap_resource_byname(pdev, "parf");567 if (IS_ERR(pcie_ep->parf))568 return PTR_ERR(pcie_ep->parf);569 570 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");571 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);572 if (IS_ERR(pci->dbi_base))573 return PTR_ERR(pci->dbi_base);574 pci->dbi_base2 = pci->dbi_base;575 576 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");577 pcie_ep->elbi = devm_pci_remap_cfg_resource(dev, res);578 if (IS_ERR(pcie_ep->elbi))579 return PTR_ERR(pcie_ep->elbi);580 581 pcie_ep->mmio_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,582 "mmio");583 if (!pcie_ep->mmio_res) {584 dev_err(dev, "Failed to get mmio resource\n");585 return -EINVAL;586 }587 588 pcie_ep->mmio = devm_pci_remap_cfg_resource(dev, pcie_ep->mmio_res);589 if (IS_ERR(pcie_ep->mmio))590 return PTR_ERR(pcie_ep->mmio);591 592 syscon = of_parse_phandle(dev->of_node, "qcom,perst-regs", 0);593 if (!syscon) {594 dev_dbg(dev, "PERST separation not available\n");595 return 0;596 }597 598 pcie_ep->perst_map = syscon_node_to_regmap(syscon);599 of_node_put(syscon);600 if (IS_ERR(pcie_ep->perst_map))601 return PTR_ERR(pcie_ep->perst_map);602 603 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs",604 1, &pcie_ep->perst_en);605 if (ret < 0) {606 dev_err(dev, "No Perst Enable offset in syscon\n");607 return ret;608 }609 610 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs",611 2, &pcie_ep->perst_sep_en);612 if (ret < 0) {613 dev_err(dev, "No Perst Separation Enable offset in syscon\n");614 return ret;615 }616 617 return 0;618}619 620static int qcom_pcie_ep_get_resources(struct platform_device *pdev,621 struct qcom_pcie_ep *pcie_ep)622{623 struct device *dev = &pdev->dev;624 int ret;625 626 ret = qcom_pcie_ep_get_io_resources(pdev, pcie_ep);627 if (ret) {628 dev_err(dev, "Failed to get io resources %d\n", ret);629 return ret;630 }631 632 pcie_ep->num_clks = devm_clk_bulk_get_all(dev, &pcie_ep->clks);633 if (pcie_ep->num_clks < 0) {634 dev_err(dev, "Failed to get clocks\n");635 return pcie_ep->num_clks;636 }637 638 pcie_ep->core_reset = devm_reset_control_get_exclusive(dev, "core");639 if (IS_ERR(pcie_ep->core_reset))640 return PTR_ERR(pcie_ep->core_reset);641 642 pcie_ep->reset = devm_gpiod_get(dev, "reset", GPIOD_IN);643 if (IS_ERR(pcie_ep->reset))644 return PTR_ERR(pcie_ep->reset);645 646 pcie_ep->wake = devm_gpiod_get_optional(dev, "wake", GPIOD_OUT_LOW);647 if (IS_ERR(pcie_ep->wake))648 return PTR_ERR(pcie_ep->wake);649 650 pcie_ep->phy = devm_phy_optional_get(dev, "pciephy");651 if (IS_ERR(pcie_ep->phy))652 ret = PTR_ERR(pcie_ep->phy);653 654 pcie_ep->icc_mem = devm_of_icc_get(dev, "pcie-mem");655 if (IS_ERR(pcie_ep->icc_mem))656 ret = PTR_ERR(pcie_ep->icc_mem);657 658 return ret;659}660 661/* TODO: Notify clients about PCIe state change */662static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data)663{664 struct qcom_pcie_ep *pcie_ep = data;665 struct dw_pcie *pci = &pcie_ep->pci;666 struct device *dev = pci->dev;667 u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS);668 u32 dstate, val;669 670 writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR);671 672 if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) {673 dev_dbg(dev, "Received Linkdown event\n");674 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DOWN;675 dw_pcie_ep_linkdown(&pci->ep);676 } else if (FIELD_GET(PARF_INT_ALL_BME, status)) {677 dev_dbg(dev, "Received Bus Master Enable event\n");678 pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED;679 qcom_pcie_ep_icc_update(pcie_ep);680 pci_epc_bus_master_enable_notify(pci->ep.epc);681 } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) {682 dev_dbg(dev, "Received PM Turn-off event! Entering L23\n");683 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);684 val |= PARF_PM_CTRL_READY_ENTR_L23;685 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);686 } else if (FIELD_GET(PARF_INT_ALL_DSTATE_CHANGE, status)) {687 dstate = dw_pcie_readl_dbi(pci, DBI_CON_STATUS) &688 DBI_CON_STATUS_POWER_STATE_MASK;689 dev_dbg(dev, "Received D%d state event\n", dstate);690 if (dstate == 3) {691 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);692 val |= PARF_PM_CTRL_REQ_EXIT_L1;693 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);694 }695 } else if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) {696 dev_dbg(dev, "Received Linkup event. Enumeration complete!\n");697 dw_pcie_ep_linkup(&pci->ep);698 pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP;699 } else {700 dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n",701 status);702 }703 704 return IRQ_HANDLED;705}706 707static irqreturn_t qcom_pcie_ep_perst_irq_thread(int irq, void *data)708{709 struct qcom_pcie_ep *pcie_ep = data;710 struct dw_pcie *pci = &pcie_ep->pci;711 struct device *dev = pci->dev;712 u32 perst;713 714 perst = gpiod_get_value(pcie_ep->reset);715 if (perst) {716 dev_dbg(dev, "PERST asserted by host. Shutting down the PCIe link!\n");717 qcom_pcie_perst_assert(pci);718 } else {719 dev_dbg(dev, "PERST de-asserted by host. Starting link training!\n");720 qcom_pcie_perst_deassert(pci);721 }722 723 irq_set_irq_type(gpiod_to_irq(pcie_ep->reset),724 (perst ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW));725 726 return IRQ_HANDLED;727}728 729static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev,730 struct qcom_pcie_ep *pcie_ep)731{732 struct device *dev = pcie_ep->pci.dev;733 char *name;734 int ret;735 736 name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_global_irq%d",737 pcie_ep->pci.ep.epc->domain_nr);738 if (!name)739 return -ENOMEM;740 741 pcie_ep->global_irq = platform_get_irq_byname(pdev, "global");742 if (pcie_ep->global_irq < 0)743 return pcie_ep->global_irq;744 745 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->global_irq, NULL,746 qcom_pcie_ep_global_irq_thread,747 IRQF_ONESHOT,748 name, pcie_ep);749 if (ret) {750 dev_err(&pdev->dev, "Failed to request Global IRQ\n");751 return ret;752 }753 754 name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_perst_irq%d",755 pcie_ep->pci.ep.epc->domain_nr);756 if (!name)757 return -ENOMEM;758 759 pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset);760 irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN);761 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL,762 qcom_pcie_ep_perst_irq_thread,763 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,764 name, pcie_ep);765 if (ret) {766 dev_err(&pdev->dev, "Failed to request PERST IRQ\n");767 disable_irq(pcie_ep->global_irq);768 return ret;769 }770 771 return 0;772}773 774static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,775 unsigned int type, u16 interrupt_num)776{777 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);778 779 switch (type) {780 case PCI_IRQ_INTX:781 return dw_pcie_ep_raise_intx_irq(ep, func_no);782 case PCI_IRQ_MSI:783 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);784 default:785 dev_err(pci->dev, "Unknown IRQ type\n");786 return -EINVAL;787 }788}789 790static int qcom_pcie_ep_link_transition_count(struct seq_file *s, void *data)791{792 struct qcom_pcie_ep *pcie_ep = (struct qcom_pcie_ep *)793 dev_get_drvdata(s->private);794 795 seq_printf(s, "L0s transition count: %u\n",796 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L0S));797 798 seq_printf(s, "L1 transition count: %u\n",799 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L1));800 801 seq_printf(s, "L1.1 transition count: %u\n",802 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1));803 804 seq_printf(s, "L1.2 transition count: %u\n",805 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2));806 807 seq_printf(s, "L2 transition count: %u\n",808 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L2));809 810 return 0;811}812 813static void qcom_pcie_ep_init_debugfs(struct qcom_pcie_ep *pcie_ep)814{815 struct dw_pcie *pci = &pcie_ep->pci;816 817 debugfs_create_devm_seqfile(pci->dev, "link_transition_count", pcie_ep->debugfs,818 qcom_pcie_ep_link_transition_count);819}820 821static const struct pci_epc_features qcom_pcie_epc_features = {822 .linkup_notifier = true,823 .msi_capable = true,824 .msix_capable = false,825 .align = SZ_4K,826};827 828static const struct pci_epc_features *829qcom_pcie_epc_get_features(struct dw_pcie_ep *pci_ep)830{831 return &qcom_pcie_epc_features;832}833 834static void qcom_pcie_ep_init(struct dw_pcie_ep *ep)835{836 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);837 enum pci_barno bar;838 839 for (bar = BAR_0; bar <= BAR_5; bar++)840 dw_pcie_ep_reset_bar(pci, bar);841}842 843static const struct dw_pcie_ep_ops pci_ep_ops = {844 .init = qcom_pcie_ep_init,845 .raise_irq = qcom_pcie_ep_raise_irq,846 .get_features = qcom_pcie_epc_get_features,847};848 849static int qcom_pcie_ep_probe(struct platform_device *pdev)850{851 struct device *dev = &pdev->dev;852 struct qcom_pcie_ep *pcie_ep;853 char *name;854 int ret;855 856 pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL);857 if (!pcie_ep)858 return -ENOMEM;859 860 pcie_ep->pci.dev = dev;861 pcie_ep->pci.ops = &pci_ops;862 pcie_ep->pci.ep.ops = &pci_ep_ops;863 pcie_ep->pci.edma.nr_irqs = 1;864 865 pcie_ep->cfg = of_device_get_match_data(dev);866 if (pcie_ep->cfg && pcie_ep->cfg->hdma_support) {867 pcie_ep->pci.edma.ll_wr_cnt = 8;868 pcie_ep->pci.edma.ll_rd_cnt = 8;869 pcie_ep->pci.edma.mf = EDMA_MF_HDMA_NATIVE;870 }871 872 platform_set_drvdata(pdev, pcie_ep);873 874 ret = qcom_pcie_ep_get_resources(pdev, pcie_ep);875 if (ret)876 return ret;877 878 ret = dw_pcie_ep_init(&pcie_ep->pci.ep);879 if (ret) {880 dev_err(dev, "Failed to initialize endpoint: %d\n", ret);881 return ret;882 }883 884 ret = qcom_pcie_ep_enable_irq_resources(pdev, pcie_ep);885 if (ret)886 goto err_ep_deinit;887 888 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node);889 if (!name) {890 ret = -ENOMEM;891 goto err_disable_irqs;892 }893 894 pcie_ep->debugfs = debugfs_create_dir(name, NULL);895 qcom_pcie_ep_init_debugfs(pcie_ep);896 897 return 0;898 899err_disable_irqs:900 disable_irq(pcie_ep->global_irq);901 disable_irq(pcie_ep->perst_irq);902 903err_ep_deinit:904 dw_pcie_ep_deinit(&pcie_ep->pci.ep);905 906 return ret;907}908 909static void qcom_pcie_ep_remove(struct platform_device *pdev)910{911 struct qcom_pcie_ep *pcie_ep = platform_get_drvdata(pdev);912 913 disable_irq(pcie_ep->global_irq);914 disable_irq(pcie_ep->perst_irq);915 916 debugfs_remove_recursive(pcie_ep->debugfs);917 918 if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED)919 return;920 921 qcom_pcie_disable_resources(pcie_ep);922}923 924static const struct qcom_pcie_ep_cfg cfg_1_34_0 = {925 .hdma_support = true,926 .override_no_snoop = true,927 .disable_mhi_ram_parity_check = true,928};929 930static const struct of_device_id qcom_pcie_ep_match[] = {931 { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0},932 { .compatible = "qcom,sdx55-pcie-ep", },933 { .compatible = "qcom,sm8450-pcie-ep", },934 { }935};936MODULE_DEVICE_TABLE(of, qcom_pcie_ep_match);937 938static struct platform_driver qcom_pcie_ep_driver = {939 .probe = qcom_pcie_ep_probe,940 .remove_new = qcom_pcie_ep_remove,941 .driver = {942 .name = "qcom-pcie-ep",943 .of_match_table = qcom_pcie_ep_match,944 },945};946builtin_platform_driver(qcom_pcie_ep_driver);947 948MODULE_AUTHOR("Siddartha Mohanadoss <smohanad@codeaurora.org>");949MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");950MODULE_DESCRIPTION("Qualcomm PCIe Endpoint controller driver");951MODULE_LICENSE("GPL v2");952