784 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * PCIe controller driver for Renesas R-Car Gen4 Series SoCs4 * Copyright (C) 2022-2023 Renesas Electronics Corporation5 *6 * The r8a779g0 (R-Car V4H) controller requires a specific firmware to be7 * provided, to initialize the PHY. Otherwise, the PCIe controller will not8 * work.9 */10 11#include <linux/delay.h>12#include <linux/firmware.h>13#include <linux/interrupt.h>14#include <linux/io.h>15#include <linux/iopoll.h>16#include <linux/module.h>17#include <linux/of.h>18#include <linux/pci.h>19#include <linux/platform_device.h>20#include <linux/pm_runtime.h>21#include <linux/reset.h>22 23#include "../../pci.h"24#include "pcie-designware.h"25 26/* Renesas-specific */27/* PCIe Mode Setting Register 0 */28#define PCIEMSR0 0x000029#define APP_SRIS_MODE BIT(6)30#define DEVICE_TYPE_EP 031#define DEVICE_TYPE_RC BIT(4)32#define BIFUR_MOD_SET_ON BIT(0)33 34/* PCIe Interrupt Status 0 */35#define PCIEINTSTS0 0x008436 37/* PCIe Interrupt Status 0 Enable */38#define PCIEINTSTS0EN 0x031039#define MSI_CTRL_INT BIT(26)40#define SMLH_LINK_UP BIT(7)41#define RDLH_LINK_UP BIT(6)42 43/* PCIe DMA Interrupt Status Enable */44#define PCIEDMAINTSTSEN 0x031445#define PCIEDMAINTSTSEN_INIT GENMASK(15, 0)46 47/* Port Logic Registers 89 */48#define PRTLGC89 0x0b7049 50/* Port Logic Registers 90 */51#define PRTLGC90 0x0b7452 53/* PCIe Reset Control Register 1 */54#define PCIERSTCTRL1 0x001455#define APP_HOLD_PHY_RST BIT(16)56#define APP_LTSSM_ENABLE BIT(0)57 58/* PCIe Power Management Control */59#define PCIEPWRMNGCTRL 0x007060#define APP_CLK_REQ_N BIT(11)61#define APP_CLK_PM_EN BIT(10)62 63#define RCAR_NUM_SPEED_CHANGE_RETRIES 1064#define RCAR_MAX_LINK_SPEED 465 66#define RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET 0x100067#define RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET 0x80068 69#define RCAR_GEN4_PCIE_FIRMWARE_NAME "rcar_gen4_pcie.bin"70#define RCAR_GEN4_PCIE_FIRMWARE_BASE_ADDR 0xc00071MODULE_FIRMWARE(RCAR_GEN4_PCIE_FIRMWARE_NAME);72 73struct rcar_gen4_pcie;74struct rcar_gen4_pcie_drvdata {75 void (*additional_common_init)(struct rcar_gen4_pcie *rcar);76 int (*ltssm_control)(struct rcar_gen4_pcie *rcar, bool enable);77 enum dw_pcie_device_mode mode;78};79 80struct rcar_gen4_pcie {81 struct dw_pcie dw;82 void __iomem *base;83 void __iomem *phy_base;84 struct platform_device *pdev;85 const struct rcar_gen4_pcie_drvdata *drvdata;86};87#define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw)88 89/* Common */90static int rcar_gen4_pcie_link_up(struct dw_pcie *dw)91{92 struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);93 u32 val, mask;94 95 val = readl(rcar->base + PCIEINTSTS0);96 mask = RDLH_LINK_UP | SMLH_LINK_UP;97 98 return (val & mask) == mask;99}100 101/*102 * Manually initiate the speed change. Return 0 if change succeeded; otherwise103 * -ETIMEDOUT.104 */105static int rcar_gen4_pcie_speed_change(struct dw_pcie *dw)106{107 u32 val;108 int i;109 110 val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);111 val &= ~PORT_LOGIC_SPEED_CHANGE;112 dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val);113 114 val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);115 val |= PORT_LOGIC_SPEED_CHANGE;116 dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val);117 118 for (i = 0; i < RCAR_NUM_SPEED_CHANGE_RETRIES; i++) {119 val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);120 if (!(val & PORT_LOGIC_SPEED_CHANGE))121 return 0;122 usleep_range(10000, 11000);123 }124 125 return -ETIMEDOUT;126}127 128/*129 * Enable LTSSM of this controller and manually initiate the speed change.130 * Always return 0.131 */132static int rcar_gen4_pcie_start_link(struct dw_pcie *dw)133{134 struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);135 int i, changes, ret;136 137 if (rcar->drvdata->ltssm_control) {138 ret = rcar->drvdata->ltssm_control(rcar, true);139 if (ret)140 return ret;141 }142 143 /*144 * Require direct speed change with retrying here if the max_link_speed145 * is PCIe Gen2 or higher.146 */147 changes = min_not_zero(dw->max_link_speed, RCAR_MAX_LINK_SPEED) - 1;148 149 /*150 * Since dw_pcie_setup_rc() sets it once, PCIe Gen2 will be trained.151 * So, this needs remaining times for up to PCIe Gen4 if RC mode.152 */153 if (changes && rcar->drvdata->mode == DW_PCIE_RC_TYPE)154 changes--;155 156 for (i = 0; i < changes; i++) {157 /* It may not be connected in EP mode yet. So, break the loop */158 if (rcar_gen4_pcie_speed_change(dw))159 break;160 }161 162 return 0;163}164 165static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw)166{167 struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);168 169 if (rcar->drvdata->ltssm_control)170 rcar->drvdata->ltssm_control(rcar, false);171}172 173static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)174{175 struct dw_pcie *dw = &rcar->dw;176 u32 val;177 int ret;178 179 ret = clk_bulk_prepare_enable(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);180 if (ret) {181 dev_err(dw->dev, "Enabling core clocks failed\n");182 return ret;183 }184 185 if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc))186 reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);187 188 val = readl(rcar->base + PCIEMSR0);189 if (rcar->drvdata->mode == DW_PCIE_RC_TYPE) {190 val |= DEVICE_TYPE_RC;191 } else if (rcar->drvdata->mode == DW_PCIE_EP_TYPE) {192 val |= DEVICE_TYPE_EP;193 } else {194 ret = -EINVAL;195 goto err_unprepare;196 }197 198 if (dw->num_lanes < 4)199 val |= BIFUR_MOD_SET_ON;200 201 writel(val, rcar->base + PCIEMSR0);202 203 ret = reset_control_deassert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);204 if (ret)205 goto err_unprepare;206 207 if (rcar->drvdata->additional_common_init)208 rcar->drvdata->additional_common_init(rcar);209 210 return 0;211 212err_unprepare:213 clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);214 215 return ret;216}217 218static void rcar_gen4_pcie_common_deinit(struct rcar_gen4_pcie *rcar)219{220 struct dw_pcie *dw = &rcar->dw;221 222 reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);223 clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);224}225 226static int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar)227{228 struct device *dev = rcar->dw.dev;229 int err;230 231 pm_runtime_enable(dev);232 err = pm_runtime_resume_and_get(dev);233 if (err < 0) {234 dev_err(dev, "Runtime resume failed\n");235 pm_runtime_disable(dev);236 }237 238 return err;239}240 241static void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar)242{243 struct device *dev = rcar->dw.dev;244 245 pm_runtime_put(dev);246 pm_runtime_disable(dev);247}248 249static int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar)250{251 rcar->phy_base = devm_platform_ioremap_resource_byname(rcar->pdev, "phy");252 if (IS_ERR(rcar->phy_base))253 return PTR_ERR(rcar->phy_base);254 255 /* Renesas-specific registers */256 rcar->base = devm_platform_ioremap_resource_byname(rcar->pdev, "app");257 258 return PTR_ERR_OR_ZERO(rcar->base);259}260 261static const struct dw_pcie_ops dw_pcie_ops = {262 .start_link = rcar_gen4_pcie_start_link,263 .stop_link = rcar_gen4_pcie_stop_link,264 .link_up = rcar_gen4_pcie_link_up,265};266 267static struct rcar_gen4_pcie *rcar_gen4_pcie_alloc(struct platform_device *pdev)268{269 struct device *dev = &pdev->dev;270 struct rcar_gen4_pcie *rcar;271 272 rcar = devm_kzalloc(dev, sizeof(*rcar), GFP_KERNEL);273 if (!rcar)274 return ERR_PTR(-ENOMEM);275 276 rcar->dw.ops = &dw_pcie_ops;277 rcar->dw.dev = dev;278 rcar->pdev = pdev;279 rcar->dw.edma.mf = EDMA_MF_EDMA_UNROLL;280 dw_pcie_cap_set(&rcar->dw, REQ_RES);281 platform_set_drvdata(pdev, rcar);282 283 return rcar;284}285 286/* Host mode */287static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp)288{289 struct dw_pcie *dw = to_dw_pcie_from_pp(pp);290 struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);291 int ret;292 u32 val;293 294 gpiod_set_value_cansleep(dw->pe_rst, 1);295 296 ret = rcar_gen4_pcie_common_init(rcar);297 if (ret)298 return ret;299 300 /*301 * According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode302 * Rev.5.20a and 3.5.6.1 "RC mode" in DWC PCIe RC databook v5.20a, we303 * should disable two BARs to avoid unnecessary memory assignment304 * during device enumeration.305 */306 dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_0, 0x0);307 dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_1, 0x0);308 309 /* Enable MSI interrupt signal */310 val = readl(rcar->base + PCIEINTSTS0EN);311 val |= MSI_CTRL_INT;312 writel(val, rcar->base + PCIEINTSTS0EN);313 314 msleep(PCIE_T_PVPERL_MS); /* pe_rst requires 100msec delay */315 316 gpiod_set_value_cansleep(dw->pe_rst, 0);317 318 return 0;319}320 321static void rcar_gen4_pcie_host_deinit(struct dw_pcie_rp *pp)322{323 struct dw_pcie *dw = to_dw_pcie_from_pp(pp);324 struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);325 326 gpiod_set_value_cansleep(dw->pe_rst, 1);327 rcar_gen4_pcie_common_deinit(rcar);328}329 330static const struct dw_pcie_host_ops rcar_gen4_pcie_host_ops = {331 .init = rcar_gen4_pcie_host_init,332 .deinit = rcar_gen4_pcie_host_deinit,333};334 335static int rcar_gen4_add_dw_pcie_rp(struct rcar_gen4_pcie *rcar)336{337 struct dw_pcie_rp *pp = &rcar->dw.pp;338 339 if (!IS_ENABLED(CONFIG_PCIE_RCAR_GEN4_HOST))340 return -ENODEV;341 342 pp->num_vectors = MAX_MSI_IRQS;343 pp->ops = &rcar_gen4_pcie_host_ops;344 345 return dw_pcie_host_init(pp);346}347 348static void rcar_gen4_remove_dw_pcie_rp(struct rcar_gen4_pcie *rcar)349{350 dw_pcie_host_deinit(&rcar->dw.pp);351}352 353/* Endpoint mode */354static void rcar_gen4_pcie_ep_pre_init(struct dw_pcie_ep *ep)355{356 struct dw_pcie *dw = to_dw_pcie_from_ep(ep);357 struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);358 int ret;359 360 ret = rcar_gen4_pcie_common_init(rcar);361 if (ret)362 return;363 364 writel(PCIEDMAINTSTSEN_INIT, rcar->base + PCIEDMAINTSTSEN);365}366 367static void rcar_gen4_pcie_ep_init(struct dw_pcie_ep *ep)368{369 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);370 enum pci_barno bar;371 372 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)373 dw_pcie_ep_reset_bar(pci, bar);374}375 376static void rcar_gen4_pcie_ep_deinit(struct rcar_gen4_pcie *rcar)377{378 writel(0, rcar->base + PCIEDMAINTSTSEN);379 rcar_gen4_pcie_common_deinit(rcar);380}381 382static int rcar_gen4_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,383 unsigned int type, u16 interrupt_num)384{385 struct dw_pcie *dw = to_dw_pcie_from_ep(ep);386 387 switch (type) {388 case PCI_IRQ_INTX:389 return dw_pcie_ep_raise_intx_irq(ep, func_no);390 case PCI_IRQ_MSI:391 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);392 default:393 dev_err(dw->dev, "Unknown IRQ type\n");394 return -EINVAL;395 }396 397 return 0;398}399 400static const struct pci_epc_features rcar_gen4_pcie_epc_features = {401 .linkup_notifier = false,402 .msi_capable = true,403 .msix_capable = false,404 .bar[BAR_1] = { .type = BAR_RESERVED, },405 .bar[BAR_3] = { .type = BAR_RESERVED, },406 .bar[BAR_5] = { .type = BAR_RESERVED, },407 .align = SZ_1M,408};409 410static const struct pci_epc_features*411rcar_gen4_pcie_ep_get_features(struct dw_pcie_ep *ep)412{413 return &rcar_gen4_pcie_epc_features;414}415 416static unsigned int rcar_gen4_pcie_ep_get_dbi_offset(struct dw_pcie_ep *ep,417 u8 func_no)418{419 return func_no * RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET;420}421 422static unsigned int rcar_gen4_pcie_ep_get_dbi2_offset(struct dw_pcie_ep *ep,423 u8 func_no)424{425 return func_no * RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET;426}427 428static const struct dw_pcie_ep_ops pcie_ep_ops = {429 .pre_init = rcar_gen4_pcie_ep_pre_init,430 .init = rcar_gen4_pcie_ep_init,431 .raise_irq = rcar_gen4_pcie_ep_raise_irq,432 .get_features = rcar_gen4_pcie_ep_get_features,433 .get_dbi_offset = rcar_gen4_pcie_ep_get_dbi_offset,434 .get_dbi2_offset = rcar_gen4_pcie_ep_get_dbi2_offset,435};436 437static int rcar_gen4_add_dw_pcie_ep(struct rcar_gen4_pcie *rcar)438{439 struct dw_pcie_ep *ep = &rcar->dw.ep;440 struct device *dev = rcar->dw.dev;441 int ret;442 443 if (!IS_ENABLED(CONFIG_PCIE_RCAR_GEN4_EP))444 return -ENODEV;445 446 ep->ops = &pcie_ep_ops;447 448 ret = dw_pcie_ep_init(ep);449 if (ret) {450 rcar_gen4_pcie_ep_deinit(rcar);451 return ret;452 }453 454 ret = dw_pcie_ep_init_registers(ep);455 if (ret) {456 dev_err(dev, "Failed to initialize DWC endpoint registers\n");457 dw_pcie_ep_deinit(ep);458 rcar_gen4_pcie_ep_deinit(rcar);459 }460 461 pci_epc_init_notify(ep->epc);462 463 return ret;464}465 466static void rcar_gen4_remove_dw_pcie_ep(struct rcar_gen4_pcie *rcar)467{468 dw_pcie_ep_deinit(&rcar->dw.ep);469 rcar_gen4_pcie_ep_deinit(rcar);470}471 472/* Common */473static int rcar_gen4_add_dw_pcie(struct rcar_gen4_pcie *rcar)474{475 rcar->drvdata = of_device_get_match_data(&rcar->pdev->dev);476 if (!rcar->drvdata)477 return -EINVAL;478 479 switch (rcar->drvdata->mode) {480 case DW_PCIE_RC_TYPE:481 return rcar_gen4_add_dw_pcie_rp(rcar);482 case DW_PCIE_EP_TYPE:483 return rcar_gen4_add_dw_pcie_ep(rcar);484 default:485 return -EINVAL;486 }487}488 489static int rcar_gen4_pcie_probe(struct platform_device *pdev)490{491 struct rcar_gen4_pcie *rcar;492 int err;493 494 rcar = rcar_gen4_pcie_alloc(pdev);495 if (IS_ERR(rcar))496 return PTR_ERR(rcar);497 498 err = rcar_gen4_pcie_get_resources(rcar);499 if (err)500 return err;501 502 err = rcar_gen4_pcie_prepare(rcar);503 if (err)504 return err;505 506 err = rcar_gen4_add_dw_pcie(rcar);507 if (err)508 goto err_unprepare;509 510 return 0;511 512err_unprepare:513 rcar_gen4_pcie_unprepare(rcar);514 515 return err;516}517 518static void rcar_gen4_remove_dw_pcie(struct rcar_gen4_pcie *rcar)519{520 switch (rcar->drvdata->mode) {521 case DW_PCIE_RC_TYPE:522 rcar_gen4_remove_dw_pcie_rp(rcar);523 break;524 case DW_PCIE_EP_TYPE:525 rcar_gen4_remove_dw_pcie_ep(rcar);526 break;527 default:528 break;529 }530}531 532static void rcar_gen4_pcie_remove(struct platform_device *pdev)533{534 struct rcar_gen4_pcie *rcar = platform_get_drvdata(pdev);535 536 rcar_gen4_remove_dw_pcie(rcar);537 rcar_gen4_pcie_unprepare(rcar);538}539 540static int r8a779f0_pcie_ltssm_control(struct rcar_gen4_pcie *rcar, bool enable)541{542 u32 val;543 544 val = readl(rcar->base + PCIERSTCTRL1);545 if (enable) {546 val |= APP_LTSSM_ENABLE;547 val &= ~APP_HOLD_PHY_RST;548 } else {549 /*550 * Since the datasheet of R-Car doesn't mention how to assert551 * the APP_HOLD_PHY_RST, don't assert it again. Otherwise,552 * hang-up issue happened in the dw_edma_core_off() when553 * the controller didn't detect a PCI device.554 */555 val &= ~APP_LTSSM_ENABLE;556 }557 writel(val, rcar->base + PCIERSTCTRL1);558 559 return 0;560}561 562static void rcar_gen4_pcie_additional_common_init(struct rcar_gen4_pcie *rcar)563{564 struct dw_pcie *dw = &rcar->dw;565 u32 val;566 567 val = dw_pcie_readl_dbi(dw, PCIE_PORT_LANE_SKEW);568 val &= ~PORT_LANE_SKEW_INSERT_MASK;569 if (dw->num_lanes < 4)570 val |= BIT(6);571 dw_pcie_writel_dbi(dw, PCIE_PORT_LANE_SKEW, val);572 573 val = readl(rcar->base + PCIEPWRMNGCTRL);574 val |= APP_CLK_REQ_N | APP_CLK_PM_EN;575 writel(val, rcar->base + PCIEPWRMNGCTRL);576}577 578static void rcar_gen4_pcie_phy_reg_update_bits(struct rcar_gen4_pcie *rcar,579 u32 offset, u32 mask, u32 val)580{581 u32 tmp;582 583 tmp = readl(rcar->phy_base + offset);584 tmp &= ~mask;585 tmp |= val;586 writel(tmp, rcar->phy_base + offset);587}588 589/*590 * SoC datasheet suggests checking port logic register bits during firmware591 * write. If read returns non-zero value, then this function returns -EAGAIN592 * indicating that the write needs to be done again. If read returns zero,593 * then return 0 to indicate success.594 */595static int rcar_gen4_pcie_reg_test_bit(struct rcar_gen4_pcie *rcar,596 u32 offset, u32 mask)597{598 struct dw_pcie *dw = &rcar->dw;599 600 if (dw_pcie_readl_dbi(dw, offset) & mask)601 return -EAGAIN;602 603 return 0;604}605 606static int rcar_gen4_pcie_download_phy_firmware(struct rcar_gen4_pcie *rcar)607{608 /* The check_addr values are magical numbers in the datasheet */609 static const u32 check_addr[] = {610 0x00101018,611 0x00101118,612 0x00101021,613 0x00101121,614 };615 struct dw_pcie *dw = &rcar->dw;616 const struct firmware *fw;617 unsigned int i, timeout;618 u32 data;619 int ret;620 621 ret = request_firmware(&fw, RCAR_GEN4_PCIE_FIRMWARE_NAME, dw->dev);622 if (ret) {623 dev_err(dw->dev, "Failed to load firmware (%s): %d\n",624 RCAR_GEN4_PCIE_FIRMWARE_NAME, ret);625 return ret;626 }627 628 for (i = 0; i < (fw->size / 2); i++) {629 data = fw->data[(i * 2) + 1] << 8 | fw->data[i * 2];630 timeout = 100;631 do {632 dw_pcie_writel_dbi(dw, PRTLGC89, RCAR_GEN4_PCIE_FIRMWARE_BASE_ADDR + i);633 dw_pcie_writel_dbi(dw, PRTLGC90, data);634 if (!rcar_gen4_pcie_reg_test_bit(rcar, PRTLGC89, BIT(30)))635 break;636 if (!(--timeout)) {637 ret = -ETIMEDOUT;638 goto exit;639 }640 usleep_range(100, 200);641 } while (1);642 }643 644 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x0f8, BIT(17), BIT(17));645 646 for (i = 0; i < ARRAY_SIZE(check_addr); i++) {647 timeout = 100;648 do {649 dw_pcie_writel_dbi(dw, PRTLGC89, check_addr[i]);650 ret = rcar_gen4_pcie_reg_test_bit(rcar, PRTLGC89, BIT(30));651 ret |= rcar_gen4_pcie_reg_test_bit(rcar, PRTLGC90, BIT(0));652 if (!ret)653 break;654 if (!(--timeout)) {655 ret = -ETIMEDOUT;656 goto exit;657 }658 usleep_range(100, 200);659 } while (1);660 }661 662exit:663 release_firmware(fw);664 665 return ret;666}667 668static int rcar_gen4_pcie_ltssm_control(struct rcar_gen4_pcie *rcar, bool enable)669{670 struct dw_pcie *dw = &rcar->dw;671 u32 val;672 int ret;673 674 if (!enable) {675 val = readl(rcar->base + PCIERSTCTRL1);676 val &= ~APP_LTSSM_ENABLE;677 writel(val, rcar->base + PCIERSTCTRL1);678 679 return 0;680 }681 682 val = dw_pcie_readl_dbi(dw, PCIE_PORT_FORCE);683 val |= PORT_FORCE_DO_DESKEW_FOR_SRIS;684 dw_pcie_writel_dbi(dw, PCIE_PORT_FORCE, val);685 686 val = readl(rcar->base + PCIEMSR0);687 val |= APP_SRIS_MODE;688 writel(val, rcar->base + PCIEMSR0);689 690 /*691 * The R-Car Gen4 datasheet doesn't describe the PHY registers' name.692 * But, the initialization procedure describes these offsets. So,693 * this driver has magical offset numbers.694 */695 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x700, BIT(28), 0);696 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x700, BIT(20), 0);697 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x700, BIT(12), 0);698 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x700, BIT(4), 0);699 700 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(23, 22), BIT(22));701 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(18, 16), GENMASK(17, 16));702 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(7, 6), BIT(6));703 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(2, 0), GENMASK(11, 0));704 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x1d4, GENMASK(16, 15), GENMASK(16, 15));705 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x514, BIT(26), BIT(26));706 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x0f8, BIT(16), 0);707 rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x0f8, BIT(19), BIT(19));708 709 val = readl(rcar->base + PCIERSTCTRL1);710 val &= ~APP_HOLD_PHY_RST;711 writel(val, rcar->base + PCIERSTCTRL1);712 713 ret = readl_poll_timeout(rcar->phy_base + 0x0f8, val, !(val & BIT(18)), 100, 10000);714 if (ret < 0)715 return ret;716 717 ret = rcar_gen4_pcie_download_phy_firmware(rcar);718 if (ret)719 return ret;720 721 val = readl(rcar->base + PCIERSTCTRL1);722 val |= APP_LTSSM_ENABLE;723 writel(val, rcar->base + PCIERSTCTRL1);724 725 return 0;726}727 728static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_pcie = {729 .ltssm_control = r8a779f0_pcie_ltssm_control,730 .mode = DW_PCIE_RC_TYPE,731};732 733static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_pcie_ep = {734 .ltssm_control = r8a779f0_pcie_ltssm_control,735 .mode = DW_PCIE_EP_TYPE,736};737 738static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_pcie = {739 .additional_common_init = rcar_gen4_pcie_additional_common_init,740 .ltssm_control = rcar_gen4_pcie_ltssm_control,741 .mode = DW_PCIE_RC_TYPE,742};743 744static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_pcie_ep = {745 .additional_common_init = rcar_gen4_pcie_additional_common_init,746 .ltssm_control = rcar_gen4_pcie_ltssm_control,747 .mode = DW_PCIE_EP_TYPE,748};749 750static const struct of_device_id rcar_gen4_pcie_of_match[] = {751 {752 .compatible = "renesas,r8a779f0-pcie",753 .data = &drvdata_r8a779f0_pcie,754 },755 {756 .compatible = "renesas,r8a779f0-pcie-ep",757 .data = &drvdata_r8a779f0_pcie_ep,758 },759 {760 .compatible = "renesas,rcar-gen4-pcie",761 .data = &drvdata_rcar_gen4_pcie,762 },763 {764 .compatible = "renesas,rcar-gen4-pcie-ep",765 .data = &drvdata_rcar_gen4_pcie_ep,766 },767 {},768};769MODULE_DEVICE_TABLE(of, rcar_gen4_pcie_of_match);770 771static struct platform_driver rcar_gen4_pcie_driver = {772 .driver = {773 .name = "pcie-rcar-gen4",774 .of_match_table = rcar_gen4_pcie_of_match,775 .probe_type = PROBE_PREFER_ASYNCHRONOUS,776 },777 .probe = rcar_gen4_pcie_probe,778 .remove_new = rcar_gen4_pcie_remove,779};780module_platform_driver(rcar_gen4_pcie_driver);781 782MODULE_DESCRIPTION("Renesas R-Car Gen4 PCIe controller driver");783MODULE_LICENSE("GPL");784