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1// SPDX-License-Identifier: GPL-2.0+2/*3 * APM X-Gene PCIe Driver4 *5 * Copyright (c) 2014 Applied Micro Circuits Corporation.6 *7 * Author: Tanmay Inamdar <tinamdar@apm.com>.8 */9#include <linux/clk.h>10#include <linux/delay.h>11#include <linux/io.h>12#include <linux/jiffies.h>13#include <linux/memblock.h>14#include <linux/init.h>15#include <linux/of.h>16#include <linux/of_address.h>17#include <linux/of_pci.h>18#include <linux/pci.h>19#include <linux/pci-acpi.h>20#include <linux/pci-ecam.h>21#include <linux/platform_device.h>22#include <linux/slab.h>23 24#include "../pci.h"25 26#define PCIECORE_CTLANDSTATUS 0x5027#define PIM1_1L 0x8028#define IBAR2 0x9829#define IR2MSK 0x9c30#define PIM2_1L 0xa031#define IBAR3L 0xb432#define IR3MSKL 0xbc33#define PIM3_1L 0xc434#define OMR1BARL 0x10035#define OMR2BARL 0x11836#define OMR3BARL 0x13037#define CFGBARL 0x15438#define CFGBARH 0x15839#define CFGCTL 0x15c40#define RTDID 0x16041#define BRIDGE_CFG_0 0x200042#define BRIDGE_CFG_4 0x201043#define BRIDGE_STATUS_0 0x260044 45#define LINK_UP_MASK 0x0000010046#define AXI_EP_CFG_ACCESS 0x1000047#define EN_COHERENCY 0xF000000048#define EN_REG 0x0000000149#define OB_LO_IO 0x0000000250#define XGENE_PCIE_DEVICEID 0xE00451#define PIPE_PHY_RATE_RD(src) ((0xc000 & (u32)(src)) >> 0xe)52 53#define XGENE_V1_PCI_EXP_CAP 0x4054 55/* PCIe IP version */56#define XGENE_PCIE_IP_VER_UNKN 057#define XGENE_PCIE_IP_VER_1 158#define XGENE_PCIE_IP_VER_2 259 60#if defined(CONFIG_PCI_XGENE) || (defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS))61struct xgene_pcie {62 struct device_node *node;63 struct device *dev;64 struct clk *clk;65 void __iomem *csr_base;66 void __iomem *cfg_base;67 unsigned long cfg_addr;68 bool link_up;69 u32 version;70};71 72static u32 xgene_pcie_readl(struct xgene_pcie *port, u32 reg)73{74 return readl(port->csr_base + reg);75}76 77static void xgene_pcie_writel(struct xgene_pcie *port, u32 reg, u32 val)78{79 writel(val, port->csr_base + reg);80}81 82static inline u32 pcie_bar_low_val(u32 addr, u32 flags)83{84 return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;85}86 87static inline struct xgene_pcie *pcie_bus_to_port(struct pci_bus *bus)88{89 struct pci_config_window *cfg;90 91 if (acpi_disabled)92 return (struct xgene_pcie *)(bus->sysdata);93 94 cfg = bus->sysdata;95 return (struct xgene_pcie *)(cfg->priv);96}97 98/*99 * When the address bit [17:16] is 2'b01, the Configuration access will be100 * treated as Type 1 and it will be forwarded to external PCIe device.101 */102static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)103{104 struct xgene_pcie *port = pcie_bus_to_port(bus);105 106 if (bus->number >= (bus->primary + 1))107 return port->cfg_base + AXI_EP_CFG_ACCESS;108 109 return port->cfg_base;110}111 112/*113 * For Configuration request, RTDID register is used as Bus Number,114 * Device Number and Function number of the header fields.115 */116static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)117{118 struct xgene_pcie *port = pcie_bus_to_port(bus);119 unsigned int b, d, f;120 u32 rtdid_val = 0;121 122 b = bus->number;123 d = PCI_SLOT(devfn);124 f = PCI_FUNC(devfn);125 126 if (!pci_is_root_bus(bus))127 rtdid_val = (b << 8) | (d << 3) | f;128 129 xgene_pcie_writel(port, RTDID, rtdid_val);130 /* read the register back to ensure flush */131 xgene_pcie_readl(port, RTDID);132}133 134/*135 * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as136 * the translation from PCI bus to native BUS. Entire DDR region137 * is mapped into PCIe space using these registers, so it can be138 * reached by DMA from EP devices. The BAR0/1 of bridge should be139 * hidden during enumeration to avoid the sizing and resource allocation140 * by PCIe core.141 */142static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)143{144 if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) ||145 (offset == PCI_BASE_ADDRESS_1)))146 return true;147 148 return false;149}150 151static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,152 int offset)153{154 if ((pci_is_root_bus(bus) && devfn != 0) ||155 xgene_pcie_hide_rc_bars(bus, offset))156 return NULL;157 158 xgene_pcie_set_rtdid_reg(bus, devfn);159 return xgene_pcie_get_cfg_base(bus) + offset;160}161 162static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,163 int where, int size, u32 *val)164{165 struct xgene_pcie *port = pcie_bus_to_port(bus);166 int ret;167 168 ret = pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val);169 if (ret != PCIBIOS_SUCCESSFUL)170 return ret;171 172 /*173 * The v1 controller has a bug in its Configuration Request Retry174 * Status (RRS) logic: when RRS Software Visibility is enabled and175 * we read the Vendor and Device ID of a non-existent device, the176 * controller fabricates return data of 0xFFFF0001 ("device exists177 * but is not ready") instead of 0xFFFFFFFF (PCI_ERROR_RESPONSE)178 * ("device does not exist"). This causes the PCI core to retry179 * the read until it times out. Avoid this by not claiming to180 * support RRS SV.181 */182 if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&183 ((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL))184 *val &= ~(PCI_EXP_RTCAP_RRS_SV << 16);185 186 if (size <= 2)187 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);188 189 return PCIBIOS_SUCCESSFUL;190}191#endif192 193#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)194static int xgene_get_csr_resource(struct acpi_device *adev,195 struct resource *res)196{197 struct device *dev = &adev->dev;198 struct resource_entry *entry;199 struct list_head list;200 unsigned long flags;201 int ret;202 203 INIT_LIST_HEAD(&list);204 flags = IORESOURCE_MEM;205 ret = acpi_dev_get_resources(adev, &list,206 acpi_dev_filter_resource_type_cb,207 (void *) flags);208 if (ret < 0) {209 dev_err(dev, "failed to parse _CRS method, error code %d\n",210 ret);211 return ret;212 }213 214 if (ret == 0) {215 dev_err(dev, "no IO and memory resources present in _CRS\n");216 return -EINVAL;217 }218 219 entry = list_first_entry(&list, struct resource_entry, node);220 *res = *entry->res;221 acpi_dev_free_resource_list(&list);222 return 0;223}224 225static int xgene_pcie_ecam_init(struct pci_config_window *cfg, u32 ipversion)226{227 struct device *dev = cfg->parent;228 struct acpi_device *adev = to_acpi_device(dev);229 struct xgene_pcie *port;230 struct resource csr;231 int ret;232 233 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);234 if (!port)235 return -ENOMEM;236 237 ret = xgene_get_csr_resource(adev, &csr);238 if (ret) {239 dev_err(dev, "can't get CSR resource\n");240 return ret;241 }242 port->csr_base = devm_pci_remap_cfg_resource(dev, &csr);243 if (IS_ERR(port->csr_base))244 return PTR_ERR(port->csr_base);245 246 port->cfg_base = cfg->win;247 port->version = ipversion;248 249 cfg->priv = port;250 return 0;251}252 253static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg)254{255 return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_1);256}257 258const struct pci_ecam_ops xgene_v1_pcie_ecam_ops = {259 .init = xgene_v1_pcie_ecam_init,260 .pci_ops = {261 .map_bus = xgene_pcie_map_bus,262 .read = xgene_pcie_config_read32,263 .write = pci_generic_config_write,264 }265};266 267static int xgene_v2_pcie_ecam_init(struct pci_config_window *cfg)268{269 return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_2);270}271 272const struct pci_ecam_ops xgene_v2_pcie_ecam_ops = {273 .init = xgene_v2_pcie_ecam_init,274 .pci_ops = {275 .map_bus = xgene_pcie_map_bus,276 .read = xgene_pcie_config_read32,277 .write = pci_generic_config_write,278 }279};280#endif281 282#if defined(CONFIG_PCI_XGENE)283static u64 xgene_pcie_set_ib_mask(struct xgene_pcie *port, u32 addr,284 u32 flags, u64 size)285{286 u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags;287 u32 val32 = 0;288 u32 val;289 290 val32 = xgene_pcie_readl(port, addr);291 val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16);292 xgene_pcie_writel(port, addr, val);293 294 val32 = xgene_pcie_readl(port, addr + 0x04);295 val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16);296 xgene_pcie_writel(port, addr + 0x04, val);297 298 val32 = xgene_pcie_readl(port, addr + 0x04);299 val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16);300 xgene_pcie_writel(port, addr + 0x04, val);301 302 val32 = xgene_pcie_readl(port, addr + 0x08);303 val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16);304 xgene_pcie_writel(port, addr + 0x08, val);305 306 return mask;307}308 309static void xgene_pcie_linkup(struct xgene_pcie *port,310 u32 *lanes, u32 *speed)311{312 u32 val32;313 314 port->link_up = false;315 val32 = xgene_pcie_readl(port, PCIECORE_CTLANDSTATUS);316 if (val32 & LINK_UP_MASK) {317 port->link_up = true;318 *speed = PIPE_PHY_RATE_RD(val32);319 val32 = xgene_pcie_readl(port, BRIDGE_STATUS_0);320 *lanes = val32 >> 26;321 }322}323 324static int xgene_pcie_init_port(struct xgene_pcie *port)325{326 struct device *dev = port->dev;327 int rc;328 329 port->clk = clk_get(dev, NULL);330 if (IS_ERR(port->clk)) {331 dev_err(dev, "clock not available\n");332 return -ENODEV;333 }334 335 rc = clk_prepare_enable(port->clk);336 if (rc) {337 dev_err(dev, "clock enable failed\n");338 return rc;339 }340 341 return 0;342}343 344static int xgene_pcie_map_reg(struct xgene_pcie *port,345 struct platform_device *pdev)346{347 struct device *dev = port->dev;348 struct resource *res;349 350 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr");351 port->csr_base = devm_pci_remap_cfg_resource(dev, res);352 if (IS_ERR(port->csr_base))353 return PTR_ERR(port->csr_base);354 355 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");356 port->cfg_base = devm_ioremap_resource(dev, res);357 if (IS_ERR(port->cfg_base))358 return PTR_ERR(port->cfg_base);359 port->cfg_addr = res->start;360 361 return 0;362}363 364static void xgene_pcie_setup_ob_reg(struct xgene_pcie *port,365 struct resource *res, u32 offset,366 u64 cpu_addr, u64 pci_addr)367{368 struct device *dev = port->dev;369 resource_size_t size = resource_size(res);370 u64 restype = resource_type(res);371 u64 mask = 0;372 u32 min_size;373 u32 flag = EN_REG;374 375 if (restype == IORESOURCE_MEM) {376 min_size = SZ_128M;377 } else {378 min_size = 128;379 flag |= OB_LO_IO;380 }381 382 if (size >= min_size)383 mask = ~(size - 1) | flag;384 else385 dev_warn(dev, "res size 0x%llx less than minimum 0x%x\n",386 (u64)size, min_size);387 388 xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr));389 xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr));390 xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask));391 xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask));392 xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr));393 xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr));394}395 396static void xgene_pcie_setup_cfg_reg(struct xgene_pcie *port)397{398 u64 addr = port->cfg_addr;399 400 xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr));401 xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr));402 xgene_pcie_writel(port, CFGCTL, EN_REG);403}404 405static int xgene_pcie_map_ranges(struct xgene_pcie *port)406{407 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(port);408 struct resource_entry *window;409 struct device *dev = port->dev;410 411 resource_list_for_each_entry(window, &bridge->windows) {412 struct resource *res = window->res;413 u64 restype = resource_type(res);414 415 dev_dbg(dev, "%pR\n", res);416 417 switch (restype) {418 case IORESOURCE_IO:419 xgene_pcie_setup_ob_reg(port, res, OMR3BARL,420 pci_pio_to_address(res->start),421 res->start - window->offset);422 break;423 case IORESOURCE_MEM:424 if (res->flags & IORESOURCE_PREFETCH)425 xgene_pcie_setup_ob_reg(port, res, OMR2BARL,426 res->start,427 res->start -428 window->offset);429 else430 xgene_pcie_setup_ob_reg(port, res, OMR1BARL,431 res->start,432 res->start -433 window->offset);434 break;435 case IORESOURCE_BUS:436 break;437 default:438 dev_err(dev, "invalid resource %pR\n", res);439 return -EINVAL;440 }441 }442 xgene_pcie_setup_cfg_reg(port);443 return 0;444}445 446static void xgene_pcie_setup_pims(struct xgene_pcie *port, u32 pim_reg,447 u64 pim, u64 size)448{449 xgene_pcie_writel(port, pim_reg, lower_32_bits(pim));450 xgene_pcie_writel(port, pim_reg + 0x04,451 upper_32_bits(pim) | EN_COHERENCY);452 xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size));453 xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size));454}455 456/*457 * X-Gene PCIe support maximum 3 inbound memory regions458 * This function helps to select a region based on size of region459 */460static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size)461{462 if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) {463 *ib_reg_mask |= (1 << 1);464 return 1;465 }466 467 if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) {468 *ib_reg_mask |= (1 << 0);469 return 0;470 }471 472 if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) {473 *ib_reg_mask |= (1 << 2);474 return 2;475 }476 477 return -EINVAL;478}479 480static void xgene_pcie_setup_ib_reg(struct xgene_pcie *port,481 struct of_pci_range *range, u8 *ib_reg_mask)482{483 void __iomem *cfg_base = port->cfg_base;484 struct device *dev = port->dev;485 void __iomem *bar_addr;486 u32 pim_reg;487 u64 cpu_addr = range->cpu_addr;488 u64 pci_addr = range->pci_addr;489 u64 size = range->size;490 u64 mask = ~(size - 1) | EN_REG;491 u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64;492 u32 bar_low;493 int region;494 495 region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size);496 if (region < 0) {497 dev_warn(dev, "invalid pcie dma-range config\n");498 return;499 }500 501 if (range->flags & IORESOURCE_PREFETCH)502 flags |= PCI_BASE_ADDRESS_MEM_PREFETCH;503 504 bar_low = pcie_bar_low_val((u32)cpu_addr, flags);505 switch (region) {506 case 0:507 xgene_pcie_set_ib_mask(port, BRIDGE_CFG_4, flags, size);508 bar_addr = cfg_base + PCI_BASE_ADDRESS_0;509 writel(bar_low, bar_addr);510 writel(upper_32_bits(cpu_addr), bar_addr + 0x4);511 pim_reg = PIM1_1L;512 break;513 case 1:514 xgene_pcie_writel(port, IBAR2, bar_low);515 xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask));516 pim_reg = PIM2_1L;517 break;518 case 2:519 xgene_pcie_writel(port, IBAR3L, bar_low);520 xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr));521 xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask));522 xgene_pcie_writel(port, IR3MSKL + 0x4, upper_32_bits(mask));523 pim_reg = PIM3_1L;524 break;525 }526 527 xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1));528}529 530static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie *port)531{532 struct device_node *np = port->node;533 struct of_pci_range range;534 struct of_pci_range_parser parser;535 struct device *dev = port->dev;536 u8 ib_reg_mask = 0;537 538 if (of_pci_dma_range_parser_init(&parser, np)) {539 dev_err(dev, "missing dma-ranges property\n");540 return -EINVAL;541 }542 543 /* Get the dma-ranges from DT */544 for_each_of_pci_range(&parser, &range) {545 u64 end = range.cpu_addr + range.size - 1;546 547 dev_dbg(dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",548 range.flags, range.cpu_addr, end, range.pci_addr);549 xgene_pcie_setup_ib_reg(port, &range, &ib_reg_mask);550 }551 return 0;552}553 554/* clear BAR configuration which was done by firmware */555static void xgene_pcie_clear_config(struct xgene_pcie *port)556{557 int i;558 559 for (i = PIM1_1L; i <= CFGCTL; i += 4)560 xgene_pcie_writel(port, i, 0);561}562 563static int xgene_pcie_setup(struct xgene_pcie *port)564{565 struct device *dev = port->dev;566 u32 val, lanes = 0, speed = 0;567 int ret;568 569 xgene_pcie_clear_config(port);570 571 /* setup the vendor and device IDs correctly */572 val = (XGENE_PCIE_DEVICEID << 16) | PCI_VENDOR_ID_AMCC;573 xgene_pcie_writel(port, BRIDGE_CFG_0, val);574 575 ret = xgene_pcie_map_ranges(port);576 if (ret)577 return ret;578 579 ret = xgene_pcie_parse_map_dma_ranges(port);580 if (ret)581 return ret;582 583 xgene_pcie_linkup(port, &lanes, &speed);584 if (!port->link_up)585 dev_info(dev, "(rc) link down\n");586 else587 dev_info(dev, "(rc) x%d gen-%d link up\n", lanes, speed + 1);588 return 0;589}590 591static struct pci_ops xgene_pcie_ops = {592 .map_bus = xgene_pcie_map_bus,593 .read = xgene_pcie_config_read32,594 .write = pci_generic_config_write32,595};596 597static int xgene_pcie_probe(struct platform_device *pdev)598{599 struct device *dev = &pdev->dev;600 struct device_node *dn = dev->of_node;601 struct xgene_pcie *port;602 struct pci_host_bridge *bridge;603 int ret;604 605 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port));606 if (!bridge)607 return -ENOMEM;608 609 port = pci_host_bridge_priv(bridge);610 611 port->node = of_node_get(dn);612 port->dev = dev;613 614 port->version = XGENE_PCIE_IP_VER_UNKN;615 if (of_device_is_compatible(port->node, "apm,xgene-pcie"))616 port->version = XGENE_PCIE_IP_VER_1;617 618 ret = xgene_pcie_map_reg(port, pdev);619 if (ret)620 return ret;621 622 ret = xgene_pcie_init_port(port);623 if (ret)624 return ret;625 626 ret = xgene_pcie_setup(port);627 if (ret)628 return ret;629 630 bridge->sysdata = port;631 bridge->ops = &xgene_pcie_ops;632 633 return pci_host_probe(bridge);634}635 636static const struct of_device_id xgene_pcie_match_table[] = {637 {.compatible = "apm,xgene-pcie",},638 {},639};640 641static struct platform_driver xgene_pcie_driver = {642 .driver = {643 .name = "xgene-pcie",644 .of_match_table = xgene_pcie_match_table,645 .suppress_bind_attrs = true,646 },647 .probe = xgene_pcie_probe,648};649builtin_platform_driver(xgene_pcie_driver);650#endif651