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1// SPDX-License-Identifier: GPL-2.02/*3 * Copyright Altera Corporation (C) 2013-2015. All rights reserved4 *5 * Author: Ley Foon Tan <lftan@altera.com>6 * Description: Altera PCIe host controller driver7 */8 9#include <linux/delay.h>10#include <linux/interrupt.h>11#include <linux/irqchip/chained_irq.h>12#include <linux/irqdomain.h>13#include <linux/init.h>14#include <linux/module.h>15#include <linux/of.h>16#include <linux/of_pci.h>17#include <linux/pci.h>18#include <linux/platform_device.h>19#include <linux/slab.h>20 21#include "../pci.h"22 23#define RP_TX_REG0 0x200024#define RP_TX_REG1 0x200425#define RP_TX_CNTRL 0x200826#define RP_TX_EOP 0x227#define RP_TX_SOP 0x128#define RP_RXCPL_STATUS 0x201029#define RP_RXCPL_EOP 0x230#define RP_RXCPL_SOP 0x131#define RP_RXCPL_REG0 0x201432#define RP_RXCPL_REG1 0x201833#define P2A_INT_STATUS 0x306034#define P2A_INT_STS_ALL 0xf35#define P2A_INT_ENABLE 0x307036#define P2A_INT_ENA_ALL 0xf37#define RP_LTSSM 0x3c6438#define RP_LTSSM_MASK 0x1f39#define LTSSM_L0 0xf40 41#define S10_RP_TX_CNTRL 0x200442#define S10_RP_RXCPL_REG 0x200843#define S10_RP_RXCPL_STATUS 0x200C44#define S10_RP_CFG_ADDR(pcie, reg) \45 (((pcie)->hip_base) + (reg) + (1 << 20))46#define S10_RP_SECONDARY(pcie) \47 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))48 49/* TLP configuration type 0 and 1 */50#define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */51#define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */52#define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */53#define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */54#define TLP_PAYLOAD_SIZE 0x0155#define TLP_READ_TAG 0x1d56#define TLP_WRITE_TAG 0x1057#define RP_DEVFN 058#define TLP_CFG_DW0(pcie, cfg) \59 (((cfg) << 24) | \60 TLP_PAYLOAD_SIZE)61#define TLP_CFG_DW1(pcie, tag, be) \62 (((PCI_DEVID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))63#define TLP_CFG_DW2(bus, devfn, offset) \64 (((bus) << 24) | ((devfn) << 16) | (offset))65#define TLP_COMP_STATUS(s) (((s) >> 13) & 7)66#define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff)67#define TLP_HDR_SIZE 368#define TLP_LOOP 50069 70#define LINK_UP_TIMEOUT HZ71#define LINK_RETRAIN_TIMEOUT HZ72 73#define DWORD_MASK 374 75#define S10_TLP_FMTTYPE_CFGRD0 0x0576#define S10_TLP_FMTTYPE_CFGRD1 0x0477#define S10_TLP_FMTTYPE_CFGWR0 0x4578#define S10_TLP_FMTTYPE_CFGWR1 0x4479 80enum altera_pcie_version {81 ALTERA_PCIE_V1 = 0,82 ALTERA_PCIE_V2,83};84 85struct altera_pcie {86 struct platform_device *pdev;87 void __iomem *cra_base;88 void __iomem *hip_base;89 int irq;90 u8 root_bus_nr;91 struct irq_domain *irq_domain;92 struct resource bus_range;93 const struct altera_pcie_data *pcie_data;94};95 96struct altera_pcie_ops {97 int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);98 void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers,99 u32 data, bool align);100 bool (*get_link_status)(struct altera_pcie *pcie);101 int (*rp_read_cfg)(struct altera_pcie *pcie, int where,102 int size, u32 *value);103 int (*rp_write_cfg)(struct altera_pcie *pcie, u8 busno,104 int where, int size, u32 value);105};106 107struct altera_pcie_data {108 const struct altera_pcie_ops *ops;109 enum altera_pcie_version version;110 u32 cap_offset; /* PCIe capability structure register offset */111 u32 cfgrd0;112 u32 cfgrd1;113 u32 cfgwr0;114 u32 cfgwr1;115};116 117struct tlp_rp_regpair_t {118 u32 ctrl;119 u32 reg0;120 u32 reg1;121};122 123static inline void cra_writel(struct altera_pcie *pcie, const u32 value,124 const u32 reg)125{126 writel_relaxed(value, pcie->cra_base + reg);127}128 129static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)130{131 return readl_relaxed(pcie->cra_base + reg);132}133 134static bool altera_pcie_link_up(struct altera_pcie *pcie)135{136 return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);137}138 139static bool s10_altera_pcie_link_up(struct altera_pcie *pcie)140{141 void __iomem *addr = S10_RP_CFG_ADDR(pcie,142 pcie->pcie_data->cap_offset +143 PCI_EXP_LNKSTA);144 145 return !!(readw(addr) & PCI_EXP_LNKSTA_DLLLA);146}147 148/*149 * Altera PCIe port uses BAR0 of RC's configuration space as the translation150 * from PCI bus to native BUS. Entire DDR region is mapped into PCIe space151 * using these registers, so it can be reached by DMA from EP devices.152 * This BAR0 will also access to MSI vector when receiving MSI/MSIX interrupt153 * from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge154 * should be hidden during enumeration to avoid the sizing and resource155 * allocation by PCIe core.156 */157static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn,158 int offset)159{160 if (pci_is_root_bus(bus) && (devfn == 0) &&161 (offset == PCI_BASE_ADDRESS_0))162 return true;163 164 return false;165}166 167static void tlp_write_tx(struct altera_pcie *pcie,168 struct tlp_rp_regpair_t *tlp_rp_regdata)169{170 cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0);171 cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1);172 cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);173}174 175static void s10_tlp_write_tx(struct altera_pcie *pcie, u32 reg0, u32 ctrl)176{177 cra_writel(pcie, reg0, RP_TX_REG0);178 cra_writel(pcie, ctrl, S10_RP_TX_CNTRL);179}180 181static bool altera_pcie_valid_device(struct altera_pcie *pcie,182 struct pci_bus *bus, int dev)183{184 /* If there is no link, then there is no device */185 if (bus->number != pcie->root_bus_nr) {186 if (!pcie->pcie_data->ops->get_link_status(pcie))187 return false;188 }189 190 /* access only one slot on each root port */191 if (bus->number == pcie->root_bus_nr && dev > 0)192 return false;193 194 return true;195}196 197static int tlp_read_packet(struct altera_pcie *pcie, u32 *value)198{199 int i;200 bool sop = false;201 u32 ctrl;202 u32 reg0, reg1;203 u32 comp_status = 1;204 205 /*206 * Minimum 2 loops to read TLP headers and 1 loop to read data207 * payload.208 */209 for (i = 0; i < TLP_LOOP; i++) {210 ctrl = cra_readl(pcie, RP_RXCPL_STATUS);211 if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) {212 reg0 = cra_readl(pcie, RP_RXCPL_REG0);213 reg1 = cra_readl(pcie, RP_RXCPL_REG1);214 215 if (ctrl & RP_RXCPL_SOP) {216 sop = true;217 comp_status = TLP_COMP_STATUS(reg1);218 }219 220 if (ctrl & RP_RXCPL_EOP) {221 if (comp_status)222 return PCIBIOS_DEVICE_NOT_FOUND;223 224 if (value)225 *value = reg0;226 227 return PCIBIOS_SUCCESSFUL;228 }229 }230 udelay(5);231 }232 233 return PCIBIOS_DEVICE_NOT_FOUND;234}235 236static int s10_tlp_read_packet(struct altera_pcie *pcie, u32 *value)237{238 u32 ctrl;239 u32 comp_status;240 u32 dw[4];241 u32 count;242 struct device *dev = &pcie->pdev->dev;243 244 for (count = 0; count < TLP_LOOP; count++) {245 ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS);246 if (ctrl & RP_RXCPL_SOP) {247 /* Read first DW */248 dw[0] = cra_readl(pcie, S10_RP_RXCPL_REG);249 break;250 }251 252 udelay(5);253 }254 255 /* SOP detection failed, return error */256 if (count == TLP_LOOP)257 return PCIBIOS_DEVICE_NOT_FOUND;258 259 count = 1;260 261 /* Poll for EOP */262 while (count < ARRAY_SIZE(dw)) {263 ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS);264 dw[count++] = cra_readl(pcie, S10_RP_RXCPL_REG);265 if (ctrl & RP_RXCPL_EOP) {266 comp_status = TLP_COMP_STATUS(dw[1]);267 if (comp_status)268 return PCIBIOS_DEVICE_NOT_FOUND;269 270 if (value && TLP_BYTE_COUNT(dw[1]) == sizeof(u32) &&271 count == 4)272 *value = dw[3];273 274 return PCIBIOS_SUCCESSFUL;275 }276 }277 278 dev_warn(dev, "Malformed TLP packet\n");279 280 return PCIBIOS_DEVICE_NOT_FOUND;281}282 283static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers,284 u32 data, bool align)285{286 struct tlp_rp_regpair_t tlp_rp_regdata;287 288 tlp_rp_regdata.reg0 = headers[0];289 tlp_rp_regdata.reg1 = headers[1];290 tlp_rp_regdata.ctrl = RP_TX_SOP;291 tlp_write_tx(pcie, &tlp_rp_regdata);292 293 if (align) {294 tlp_rp_regdata.reg0 = headers[2];295 tlp_rp_regdata.reg1 = 0;296 tlp_rp_regdata.ctrl = 0;297 tlp_write_tx(pcie, &tlp_rp_regdata);298 299 tlp_rp_regdata.reg0 = data;300 tlp_rp_regdata.reg1 = 0;301 } else {302 tlp_rp_regdata.reg0 = headers[2];303 tlp_rp_regdata.reg1 = data;304 }305 306 tlp_rp_regdata.ctrl = RP_TX_EOP;307 tlp_write_tx(pcie, &tlp_rp_regdata);308}309 310static void s10_tlp_write_packet(struct altera_pcie *pcie, u32 *headers,311 u32 data, bool dummy)312{313 s10_tlp_write_tx(pcie, headers[0], RP_TX_SOP);314 s10_tlp_write_tx(pcie, headers[1], 0);315 s10_tlp_write_tx(pcie, headers[2], 0);316 s10_tlp_write_tx(pcie, data, RP_TX_EOP);317}318 319static void get_tlp_header(struct altera_pcie *pcie, u8 bus, u32 devfn,320 int where, u8 byte_en, bool read, u32 *headers)321{322 u8 cfg;323 u8 cfg0 = read ? pcie->pcie_data->cfgrd0 : pcie->pcie_data->cfgwr0;324 u8 cfg1 = read ? pcie->pcie_data->cfgrd1 : pcie->pcie_data->cfgwr1;325 u8 tag = read ? TLP_READ_TAG : TLP_WRITE_TAG;326 327 if (pcie->pcie_data->version == ALTERA_PCIE_V1)328 cfg = (bus == pcie->root_bus_nr) ? cfg0 : cfg1;329 else330 cfg = (bus > S10_RP_SECONDARY(pcie)) ? cfg0 : cfg1;331 332 headers[0] = TLP_CFG_DW0(pcie, cfg);333 headers[1] = TLP_CFG_DW1(pcie, tag, byte_en);334 headers[2] = TLP_CFG_DW2(bus, devfn, where);335}336 337static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn,338 int where, u8 byte_en, u32 *value)339{340 u32 headers[TLP_HDR_SIZE];341 342 get_tlp_header(pcie, bus, devfn, where, byte_en, true,343 headers);344 345 pcie->pcie_data->ops->tlp_write_pkt(pcie, headers, 0, false);346 347 return pcie->pcie_data->ops->tlp_read_pkt(pcie, value);348}349 350static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn,351 int where, u8 byte_en, u32 value)352{353 u32 headers[TLP_HDR_SIZE];354 int ret;355 356 get_tlp_header(pcie, bus, devfn, where, byte_en, false,357 headers);358 359 /* check alignment to Qword */360 if ((where & 0x7) == 0)361 pcie->pcie_data->ops->tlp_write_pkt(pcie, headers,362 value, true);363 else364 pcie->pcie_data->ops->tlp_write_pkt(pcie, headers,365 value, false);366 367 ret = pcie->pcie_data->ops->tlp_read_pkt(pcie, NULL);368 if (ret != PCIBIOS_SUCCESSFUL)369 return ret;370 371 /*372 * Monitor changes to PCI_PRIMARY_BUS register on root port373 * and update local copy of root bus number accordingly.374 */375 if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS))376 pcie->root_bus_nr = (u8)(value);377 378 return PCIBIOS_SUCCESSFUL;379}380 381static int s10_rp_read_cfg(struct altera_pcie *pcie, int where,382 int size, u32 *value)383{384 void __iomem *addr = S10_RP_CFG_ADDR(pcie, where);385 386 switch (size) {387 case 1:388 *value = readb(addr);389 break;390 case 2:391 *value = readw(addr);392 break;393 default:394 *value = readl(addr);395 break;396 }397 398 return PCIBIOS_SUCCESSFUL;399}400 401static int s10_rp_write_cfg(struct altera_pcie *pcie, u8 busno,402 int where, int size, u32 value)403{404 void __iomem *addr = S10_RP_CFG_ADDR(pcie, where);405 406 switch (size) {407 case 1:408 writeb(value, addr);409 break;410 case 2:411 writew(value, addr);412 break;413 default:414 writel(value, addr);415 break;416 }417 418 /*419 * Monitor changes to PCI_PRIMARY_BUS register on root port420 * and update local copy of root bus number accordingly.421 */422 if (busno == pcie->root_bus_nr && where == PCI_PRIMARY_BUS)423 pcie->root_bus_nr = value & 0xff;424 425 return PCIBIOS_SUCCESSFUL;426}427 428static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno,429 unsigned int devfn, int where, int size,430 u32 *value)431{432 int ret;433 u32 data;434 u8 byte_en;435 436 if (busno == pcie->root_bus_nr && pcie->pcie_data->ops->rp_read_cfg)437 return pcie->pcie_data->ops->rp_read_cfg(pcie, where,438 size, value);439 440 switch (size) {441 case 1:442 byte_en = 1 << (where & 3);443 break;444 case 2:445 byte_en = 3 << (where & 3);446 break;447 default:448 byte_en = 0xf;449 break;450 }451 452 ret = tlp_cfg_dword_read(pcie, busno, devfn,453 (where & ~DWORD_MASK), byte_en, &data);454 if (ret != PCIBIOS_SUCCESSFUL)455 return ret;456 457 switch (size) {458 case 1:459 *value = (data >> (8 * (where & 0x3))) & 0xff;460 break;461 case 2:462 *value = (data >> (8 * (where & 0x2))) & 0xffff;463 break;464 default:465 *value = data;466 break;467 }468 469 return PCIBIOS_SUCCESSFUL;470}471 472static int _altera_pcie_cfg_write(struct altera_pcie *pcie, u8 busno,473 unsigned int devfn, int where, int size,474 u32 value)475{476 u32 data32;477 u32 shift = 8 * (where & 3);478 u8 byte_en;479 480 if (busno == pcie->root_bus_nr && pcie->pcie_data->ops->rp_write_cfg)481 return pcie->pcie_data->ops->rp_write_cfg(pcie, busno,482 where, size, value);483 484 switch (size) {485 case 1:486 data32 = (value & 0xff) << shift;487 byte_en = 1 << (where & 3);488 break;489 case 2:490 data32 = (value & 0xffff) << shift;491 byte_en = 3 << (where & 3);492 break;493 default:494 data32 = value;495 byte_en = 0xf;496 break;497 }498 499 return tlp_cfg_dword_write(pcie, busno, devfn, (where & ~DWORD_MASK),500 byte_en, data32);501}502 503static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn,504 int where, int size, u32 *value)505{506 struct altera_pcie *pcie = bus->sysdata;507 508 if (altera_pcie_hide_rc_bar(bus, devfn, where))509 return PCIBIOS_BAD_REGISTER_NUMBER;510 511 if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn)))512 return PCIBIOS_DEVICE_NOT_FOUND;513 514 return _altera_pcie_cfg_read(pcie, bus->number, devfn, where, size,515 value);516}517 518static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn,519 int where, int size, u32 value)520{521 struct altera_pcie *pcie = bus->sysdata;522 523 if (altera_pcie_hide_rc_bar(bus, devfn, where))524 return PCIBIOS_BAD_REGISTER_NUMBER;525 526 if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn)))527 return PCIBIOS_DEVICE_NOT_FOUND;528 529 return _altera_pcie_cfg_write(pcie, bus->number, devfn, where, size,530 value);531}532 533static struct pci_ops altera_pcie_ops = {534 .read = altera_pcie_cfg_read,535 .write = altera_pcie_cfg_write,536};537 538static int altera_read_cap_word(struct altera_pcie *pcie, u8 busno,539 unsigned int devfn, int offset, u16 *value)540{541 u32 data;542 int ret;543 544 ret = _altera_pcie_cfg_read(pcie, busno, devfn,545 pcie->pcie_data->cap_offset + offset,546 sizeof(*value),547 &data);548 *value = data;549 return ret;550}551 552static int altera_write_cap_word(struct altera_pcie *pcie, u8 busno,553 unsigned int devfn, int offset, u16 value)554{555 return _altera_pcie_cfg_write(pcie, busno, devfn,556 pcie->pcie_data->cap_offset + offset,557 sizeof(value),558 value);559}560 561static void altera_wait_link_retrain(struct altera_pcie *pcie)562{563 struct device *dev = &pcie->pdev->dev;564 u16 reg16;565 unsigned long start_jiffies;566 567 /* Wait for link training end. */568 start_jiffies = jiffies;569 for (;;) {570 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,571 PCI_EXP_LNKSTA, ®16);572 if (!(reg16 & PCI_EXP_LNKSTA_LT))573 break;574 575 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) {576 dev_err(dev, "link retrain timeout\n");577 break;578 }579 udelay(100);580 }581 582 /* Wait for link is up */583 start_jiffies = jiffies;584 for (;;) {585 if (pcie->pcie_data->ops->get_link_status(pcie))586 break;587 588 if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) {589 dev_err(dev, "link up timeout\n");590 break;591 }592 udelay(100);593 }594}595 596static void altera_pcie_retrain(struct altera_pcie *pcie)597{598 u16 linkcap, linkstat, linkctl;599 600 if (!pcie->pcie_data->ops->get_link_status(pcie))601 return;602 603 /*604 * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but605 * current speed is 2.5 GB/s.606 */607 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKCAP,608 &linkcap);609 if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB)610 return;611 612 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKSTA,613 &linkstat);614 if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {615 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,616 PCI_EXP_LNKCTL, &linkctl);617 linkctl |= PCI_EXP_LNKCTL_RL;618 altera_write_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN,619 PCI_EXP_LNKCTL, linkctl);620 621 altera_wait_link_retrain(pcie);622 }623}624 625static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq,626 irq_hw_number_t hwirq)627{628 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);629 irq_set_chip_data(irq, domain->host_data);630 return 0;631}632 633static const struct irq_domain_ops intx_domain_ops = {634 .map = altera_pcie_intx_map,635 .xlate = pci_irqd_intx_xlate,636};637 638static void altera_pcie_isr(struct irq_desc *desc)639{640 struct irq_chip *chip = irq_desc_get_chip(desc);641 struct altera_pcie *pcie;642 struct device *dev;643 unsigned long status;644 u32 bit;645 int ret;646 647 chained_irq_enter(chip, desc);648 pcie = irq_desc_get_handler_data(desc);649 dev = &pcie->pdev->dev;650 651 while ((status = cra_readl(pcie, P2A_INT_STATUS)652 & P2A_INT_STS_ALL) != 0) {653 for_each_set_bit(bit, &status, PCI_NUM_INTX) {654 /* clear interrupts */655 cra_writel(pcie, 1 << bit, P2A_INT_STATUS);656 657 ret = generic_handle_domain_irq(pcie->irq_domain, bit);658 if (ret)659 dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n", bit);660 }661 }662 663 chained_irq_exit(chip, desc);664}665 666static int altera_pcie_init_irq_domain(struct altera_pcie *pcie)667{668 struct device *dev = &pcie->pdev->dev;669 struct device_node *node = dev->of_node;670 671 /* Setup INTx */672 pcie->irq_domain = irq_domain_add_linear(node, PCI_NUM_INTX,673 &intx_domain_ops, pcie);674 if (!pcie->irq_domain) {675 dev_err(dev, "Failed to get a INTx IRQ domain\n");676 return -ENOMEM;677 }678 679 return 0;680}681 682static void altera_pcie_irq_teardown(struct altera_pcie *pcie)683{684 irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);685 irq_domain_remove(pcie->irq_domain);686 irq_dispose_mapping(pcie->irq);687}688 689static int altera_pcie_parse_dt(struct altera_pcie *pcie)690{691 struct platform_device *pdev = pcie->pdev;692 693 pcie->cra_base = devm_platform_ioremap_resource_byname(pdev, "Cra");694 if (IS_ERR(pcie->cra_base))695 return PTR_ERR(pcie->cra_base);696 697 if (pcie->pcie_data->version == ALTERA_PCIE_V2) {698 pcie->hip_base =699 devm_platform_ioremap_resource_byname(pdev, "Hip");700 if (IS_ERR(pcie->hip_base))701 return PTR_ERR(pcie->hip_base);702 }703 704 /* setup IRQ */705 pcie->irq = platform_get_irq(pdev, 0);706 if (pcie->irq < 0)707 return pcie->irq;708 709 irq_set_chained_handler_and_data(pcie->irq, altera_pcie_isr, pcie);710 return 0;711}712 713static void altera_pcie_host_init(struct altera_pcie *pcie)714{715 altera_pcie_retrain(pcie);716}717 718static const struct altera_pcie_ops altera_pcie_ops_1_0 = {719 .tlp_read_pkt = tlp_read_packet,720 .tlp_write_pkt = tlp_write_packet,721 .get_link_status = altera_pcie_link_up,722};723 724static const struct altera_pcie_ops altera_pcie_ops_2_0 = {725 .tlp_read_pkt = s10_tlp_read_packet,726 .tlp_write_pkt = s10_tlp_write_packet,727 .get_link_status = s10_altera_pcie_link_up,728 .rp_read_cfg = s10_rp_read_cfg,729 .rp_write_cfg = s10_rp_write_cfg,730};731 732static const struct altera_pcie_data altera_pcie_1_0_data = {733 .ops = &altera_pcie_ops_1_0,734 .cap_offset = 0x80,735 .version = ALTERA_PCIE_V1,736 .cfgrd0 = TLP_FMTTYPE_CFGRD0,737 .cfgrd1 = TLP_FMTTYPE_CFGRD1,738 .cfgwr0 = TLP_FMTTYPE_CFGWR0,739 .cfgwr1 = TLP_FMTTYPE_CFGWR1,740};741 742static const struct altera_pcie_data altera_pcie_2_0_data = {743 .ops = &altera_pcie_ops_2_0,744 .version = ALTERA_PCIE_V2,745 .cap_offset = 0x70,746 .cfgrd0 = S10_TLP_FMTTYPE_CFGRD0,747 .cfgrd1 = S10_TLP_FMTTYPE_CFGRD1,748 .cfgwr0 = S10_TLP_FMTTYPE_CFGWR0,749 .cfgwr1 = S10_TLP_FMTTYPE_CFGWR1,750};751 752static const struct of_device_id altera_pcie_of_match[] = {753 {.compatible = "altr,pcie-root-port-1.0",754 .data = &altera_pcie_1_0_data },755 {.compatible = "altr,pcie-root-port-2.0",756 .data = &altera_pcie_2_0_data },757 {},758};759 760static int altera_pcie_probe(struct platform_device *pdev)761{762 struct device *dev = &pdev->dev;763 struct altera_pcie *pcie;764 struct pci_host_bridge *bridge;765 int ret;766 const struct altera_pcie_data *data;767 768 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));769 if (!bridge)770 return -ENOMEM;771 772 pcie = pci_host_bridge_priv(bridge);773 pcie->pdev = pdev;774 platform_set_drvdata(pdev, pcie);775 776 data = of_device_get_match_data(&pdev->dev);777 if (!data)778 return -ENODEV;779 780 pcie->pcie_data = data;781 782 ret = altera_pcie_parse_dt(pcie);783 if (ret) {784 dev_err(dev, "Parsing DT failed\n");785 return ret;786 }787 788 ret = altera_pcie_init_irq_domain(pcie);789 if (ret) {790 dev_err(dev, "Failed creating IRQ Domain\n");791 return ret;792 }793 794 /* clear all interrupts */795 cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS);796 /* enable all interrupts */797 cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE);798 altera_pcie_host_init(pcie);799 800 bridge->sysdata = pcie;801 bridge->busnr = pcie->root_bus_nr;802 bridge->ops = &altera_pcie_ops;803 804 return pci_host_probe(bridge);805}806 807static void altera_pcie_remove(struct platform_device *pdev)808{809 struct altera_pcie *pcie = platform_get_drvdata(pdev);810 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);811 812 pci_stop_root_bus(bridge->bus);813 pci_remove_root_bus(bridge->bus);814 altera_pcie_irq_teardown(pcie);815}816 817static struct platform_driver altera_pcie_driver = {818 .probe = altera_pcie_probe,819 .remove_new = altera_pcie_remove,820 .driver = {821 .name = "altera-pcie",822 .of_match_table = altera_pcie_of_match,823 },824};825 826MODULE_DEVICE_TABLE(of, altera_pcie_of_match);827module_platform_driver(altera_pcie_driver);828MODULE_DESCRIPTION("Altera PCIe host controller driver");829MODULE_LICENSE("GPL v2");830