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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * PCIe driver for Renesas R-Car SoCs4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd5 *6 * Author: Phil Edworthy <phil.edworthy@renesas.com>7 */8 9#ifndef _PCIE_RCAR_H10#define _PCIE_RCAR_H11 12#define PCIECAR 0x00001013#define PCIECCTLR 0x00001814#define PCIECCTLR_CCIE BIT(31)15#define TYPE0 (0 << 8)16#define TYPE1 BIT(8)17#define PCIECDR 0x00002018#define PCIEMSR 0x00002819#define PCIEINTXR 0x00040020#define ASTINTX BIT(16)21#define PCIEPHYSR 0x0007f022#define PHYRDY BIT(0)23#define PCIEMSITXR 0x00084024 25/* Transfer control */26#define PCIETCTLR 0x0200027#define DL_DOWN BIT(3)28#define CFINIT BIT(0)29#define PCIETSTR 0x0200430#define DATA_LINK_ACTIVE BIT(0)31#define PCIEERRFR 0x0202032#define UNSUPPORTED_REQUEST BIT(4)33#define PCIEMSIFR 0x0204434#define PCIEMSIALR 0x0204835#define MSIFE BIT(0)36#define PCIEMSIAUR 0x0204c37#define PCIEMSIIER 0x0205038 39/* root port address */40#define PCIEPRAR(x) (0x02080 + ((x) * 0x4))41 42/* local address reg & mask */43#define PCIELAR(x) (0x02200 + ((x) * 0x20))44#define PCIELAMR(x) (0x02208 + ((x) * 0x20))45#define LAM_PREFETCH BIT(3)46#define LAM_64BIT BIT(2)47#define LAR_ENABLE BIT(1)48 49/* PCIe address reg & mask */50#define PCIEPALR(x) (0x03400 + ((x) * 0x20))51#define PCIEPAUR(x) (0x03404 + ((x) * 0x20))52#define PCIEPAMR(x) (0x03408 + ((x) * 0x20))53#define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))54#define PAR_ENABLE BIT(31)55#define IO_SPACE BIT(8)56 57/* Configuration */58#define PCICONF(x) (0x010000 + ((x) * 0x4))59#define INTDIS BIT(10)60#define PMCAP(x) (0x010040 + ((x) * 0x4))61#define MSICAP(x) (0x010050 + ((x) * 0x4))62#define MSICAP0_MSIE BIT(16)63#define MSICAP0_MMESCAP_OFFSET 1764#define MSICAP0_MMESE_OFFSET 2065#define MSICAP0_MMESE_MASK GENMASK(22, 20)66#define EXPCAP(x) (0x010070 + ((x) * 0x4))67#define VCCAP(x) (0x010100 + ((x) * 0x4))68 69/* link layer */70#define IDSETR0 0x01100071#define IDSETR1 0x01100472#define SUBIDSETR 0x01102473#define TLCTLR 0x01104874#define MACSR 0x01105475#define SPCHGFIN BIT(4)76#define SPCHGFAIL BIT(6)77#define SPCHGSUC BIT(7)78#define LINK_SPEED (0xf << 16)79#define LINK_SPEED_2_5GTS (1 << 16)80#define LINK_SPEED_5_0GTS (2 << 16)81#define MACCTLR 0x01105882#define MACCTLR_NFTS_MASK GENMASK(23, 16) /* The name is from SH7786 */83#define SPEED_CHANGE BIT(24)84#define SCRAMBLE_DISABLE BIT(27)85#define LTSMDIS BIT(31)86#define MACCTLR_INIT_VAL (LTSMDIS | MACCTLR_NFTS_MASK)87#define PMSR 0x01105c88#define L1FAEG BIT(31)89#define PMEL1RX BIT(23)90#define PMSTATE GENMASK(18, 16)91#define PMSTATE_L1 (3 << 16)92#define PMCTLR 0x01106093#define L1IATN BIT(31)94 95#define MACS2R 0x01107896#define MACCGSPSETR 0x01108497#define SPCNGRSN BIT(31)98 99/* R-Car H1 PHY */100#define H1_PCIEPHYADRR 0x04000c101#define WRITE_CMD BIT(16)102#define PHY_ACK BIT(24)103#define RATE_POS 12104#define LANE_POS 8105#define ADR_POS 0106#define H1_PCIEPHYDOUTR 0x040014107 108/* R-Car Gen2 PHY */109#define GEN2_PCIEPHYADDR 0x780110#define GEN2_PCIEPHYDATA 0x784111#define GEN2_PCIEPHYCTRL 0x78c112 113#define INT_PCI_MSI_NR 32114 115#define RCONF(x) (PCICONF(0) + (x))116#define RPMCAP(x) (PMCAP(0) + (x))117#define REXPCAP(x) (EXPCAP(0) + (x))118#define RVCCAP(x) (VCCAP(0) + (x))119 120#define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)121#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)122#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)123 124#define RCAR_PCI_MAX_RESOURCES 4125#define MAX_NR_INBOUND_MAPS 6126 127struct rcar_pcie {128 struct device *dev;129 void __iomem *base;130};131 132enum {133 RCAR_PCI_ACCESS_READ,134 RCAR_PCI_ACCESS_WRITE,135};136 137void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg);138u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg);139void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data);140int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie);141int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie);142void rcar_pcie_set_outbound(struct rcar_pcie *pcie, int win,143 struct resource_entry *window);144void rcar_pcie_set_inbound(struct rcar_pcie *pcie, u64 cpu_addr,145 u64 pci_addr, u64 flags, int idx, bool host);146 147#endif148