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1// SPDX-License-Identifier: GPL-2.0+2/*3 * PCIe host controller driver for Xilinx AXI PCIe Bridge4 *5 * Copyright (c) 2012 - 2014 Xilinx, Inc.6 *7 * Based on the Tegra PCIe driver8 *9 * Bits taken from Synopsys DesignWare Host controller driver and10 * ARM PCI Host generic driver.11 */12 13#include <linux/interrupt.h>14#include <linux/irq.h>15#include <linux/irqdomain.h>16#include <linux/kernel.h>17#include <linux/init.h>18#include <linux/msi.h>19#include <linux/of_address.h>20#include <linux/of_pci.h>21#include <linux/of_platform.h>22#include <linux/of_irq.h>23#include <linux/pci.h>24#include <linux/pci-ecam.h>25#include <linux/platform_device.h>26 27#include "../pci.h"28 29/* Register definitions */30#define XILINX_PCIE_REG_BIR 0x0000013031#define XILINX_PCIE_REG_IDR 0x0000013832#define XILINX_PCIE_REG_IMR 0x0000013c33#define XILINX_PCIE_REG_PSCR 0x0000014434#define XILINX_PCIE_REG_RPSC 0x0000014835#define XILINX_PCIE_REG_MSIBASE1 0x0000014c36#define XILINX_PCIE_REG_MSIBASE2 0x0000015037#define XILINX_PCIE_REG_RPEFR 0x0000015438#define XILINX_PCIE_REG_RPIFR1 0x0000015839#define XILINX_PCIE_REG_RPIFR2 0x0000015c40 41/* Interrupt registers definitions */42#define XILINX_PCIE_INTR_LINK_DOWN BIT(0)43#define XILINX_PCIE_INTR_ECRC_ERR BIT(1)44#define XILINX_PCIE_INTR_STR_ERR BIT(2)45#define XILINX_PCIE_INTR_HOT_RESET BIT(3)46#define XILINX_PCIE_INTR_CFG_TIMEOUT BIT(8)47#define XILINX_PCIE_INTR_CORRECTABLE BIT(9)48#define XILINX_PCIE_INTR_NONFATAL BIT(10)49#define XILINX_PCIE_INTR_FATAL BIT(11)50#define XILINX_PCIE_INTR_INTX BIT(16)51#define XILINX_PCIE_INTR_MSI BIT(17)52#define XILINX_PCIE_INTR_SLV_UNSUPP BIT(20)53#define XILINX_PCIE_INTR_SLV_UNEXP BIT(21)54#define XILINX_PCIE_INTR_SLV_COMPL BIT(22)55#define XILINX_PCIE_INTR_SLV_ERRP BIT(23)56#define XILINX_PCIE_INTR_SLV_CMPABT BIT(24)57#define XILINX_PCIE_INTR_SLV_ILLBUR BIT(25)58#define XILINX_PCIE_INTR_MST_DECERR BIT(26)59#define XILINX_PCIE_INTR_MST_SLVERR BIT(27)60#define XILINX_PCIE_INTR_MST_ERRP BIT(28)61#define XILINX_PCIE_IMR_ALL_MASK 0x1FF30FED62#define XILINX_PCIE_IMR_ENABLE_MASK 0x1FF30F0D63#define XILINX_PCIE_IDR_ALL_MASK 0xFFFFFFFF64 65/* Root Port Error FIFO Read Register definitions */66#define XILINX_PCIE_RPEFR_ERR_VALID BIT(18)67#define XILINX_PCIE_RPEFR_REQ_ID GENMASK(15, 0)68#define XILINX_PCIE_RPEFR_ALL_MASK 0xFFFFFFFF69 70/* Root Port Interrupt FIFO Read Register 1 definitions */71#define XILINX_PCIE_RPIFR1_INTR_VALID BIT(31)72#define XILINX_PCIE_RPIFR1_MSI_INTR BIT(30)73#define XILINX_PCIE_RPIFR1_INTR_MASK GENMASK(28, 27)74#define XILINX_PCIE_RPIFR1_ALL_MASK 0xFFFFFFFF75#define XILINX_PCIE_RPIFR1_INTR_SHIFT 2776 77/* Bridge Info Register definitions */78#define XILINX_PCIE_BIR_ECAM_SZ_MASK GENMASK(18, 16)79#define XILINX_PCIE_BIR_ECAM_SZ_SHIFT 1680 81/* Root Port Interrupt FIFO Read Register 2 definitions */82#define XILINX_PCIE_RPIFR2_MSG_DATA GENMASK(15, 0)83 84/* Root Port Status/control Register definitions */85#define XILINX_PCIE_REG_RPSC_BEN BIT(0)86 87/* Phy Status/Control Register definitions */88#define XILINX_PCIE_REG_PSCR_LNKUP BIT(11)89 90/* Number of MSI IRQs */91#define XILINX_NUM_MSI_IRQS 12892 93/**94 * struct xilinx_pcie - PCIe port information95 * @dev: Device pointer96 * @reg_base: IO Mapped Register Base97 * @msi_map: Bitmap of allocated MSIs98 * @map_lock: Mutex protecting the MSI allocation99 * @msi_domain: MSI IRQ domain pointer100 * @leg_domain: Legacy IRQ domain pointer101 * @resources: Bus Resources102 */103struct xilinx_pcie {104 struct device *dev;105 void __iomem *reg_base;106 unsigned long msi_map[BITS_TO_LONGS(XILINX_NUM_MSI_IRQS)];107 struct mutex map_lock;108 struct irq_domain *msi_domain;109 struct irq_domain *leg_domain;110 struct list_head resources;111};112 113static inline u32 pcie_read(struct xilinx_pcie *pcie, u32 reg)114{115 return readl(pcie->reg_base + reg);116}117 118static inline void pcie_write(struct xilinx_pcie *pcie, u32 val, u32 reg)119{120 writel(val, pcie->reg_base + reg);121}122 123static inline bool xilinx_pcie_link_up(struct xilinx_pcie *pcie)124{125 return (pcie_read(pcie, XILINX_PCIE_REG_PSCR) &126 XILINX_PCIE_REG_PSCR_LNKUP) ? 1 : 0;127}128 129/**130 * xilinx_pcie_clear_err_interrupts - Clear Error Interrupts131 * @pcie: PCIe port information132 */133static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie *pcie)134{135 struct device *dev = pcie->dev;136 unsigned long val = pcie_read(pcie, XILINX_PCIE_REG_RPEFR);137 138 if (val & XILINX_PCIE_RPEFR_ERR_VALID) {139 dev_dbg(dev, "Requester ID %lu\n",140 val & XILINX_PCIE_RPEFR_REQ_ID);141 pcie_write(pcie, XILINX_PCIE_RPEFR_ALL_MASK,142 XILINX_PCIE_REG_RPEFR);143 }144}145 146/**147 * xilinx_pcie_valid_device - Check if a valid device is present on bus148 * @bus: PCI Bus structure149 * @devfn: device/function150 *151 * Return: 'true' on success and 'false' if invalid device is found152 */153static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)154{155 struct xilinx_pcie *pcie = bus->sysdata;156 157 /* Check if link is up when trying to access downstream pcie ports */158 if (!pci_is_root_bus(bus)) {159 if (!xilinx_pcie_link_up(pcie))160 return false;161 } else if (devfn > 0) {162 /* Only one device down on each root port */163 return false;164 }165 return true;166}167 168/**169 * xilinx_pcie_map_bus - Get configuration base170 * @bus: PCI Bus structure171 * @devfn: Device/function172 * @where: Offset from base173 *174 * Return: Base address of the configuration space needed to be175 * accessed.176 */177static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus,178 unsigned int devfn, int where)179{180 struct xilinx_pcie *pcie = bus->sysdata;181 182 if (!xilinx_pcie_valid_device(bus, devfn))183 return NULL;184 185 return pcie->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);186}187 188/* PCIe operations */189static struct pci_ops xilinx_pcie_ops = {190 .map_bus = xilinx_pcie_map_bus,191 .read = pci_generic_config_read,192 .write = pci_generic_config_write,193};194 195/* MSI functions */196 197static void xilinx_msi_top_irq_ack(struct irq_data *d)198{199 /*200 * xilinx_pcie_intr_handler() will have performed the Ack.201 * Eventually, this should be fixed and the Ack be moved in202 * the respective callbacks for INTx and MSI.203 */204}205 206static struct irq_chip xilinx_msi_top_chip = {207 .name = "PCIe MSI",208 .irq_ack = xilinx_msi_top_irq_ack,209};210 211static void xilinx_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)212{213 struct xilinx_pcie *pcie = irq_data_get_irq_chip_data(data);214 phys_addr_t pa = ALIGN_DOWN(virt_to_phys(pcie), SZ_4K);215 216 msg->address_lo = lower_32_bits(pa);217 msg->address_hi = upper_32_bits(pa);218 msg->data = data->hwirq;219}220 221static struct irq_chip xilinx_msi_bottom_chip = {222 .name = "Xilinx MSI",223 .irq_compose_msi_msg = xilinx_compose_msi_msg,224};225 226static int xilinx_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,227 unsigned int nr_irqs, void *args)228{229 struct xilinx_pcie *pcie = domain->host_data;230 int hwirq, i;231 232 mutex_lock(&pcie->map_lock);233 234 hwirq = bitmap_find_free_region(pcie->msi_map, XILINX_NUM_MSI_IRQS, order_base_2(nr_irqs));235 236 mutex_unlock(&pcie->map_lock);237 238 if (hwirq < 0)239 return -ENOSPC;240 241 for (i = 0; i < nr_irqs; i++)242 irq_domain_set_info(domain, virq + i, hwirq + i,243 &xilinx_msi_bottom_chip, domain->host_data,244 handle_edge_irq, NULL, NULL);245 246 return 0;247}248 249static void xilinx_msi_domain_free(struct irq_domain *domain, unsigned int virq,250 unsigned int nr_irqs)251{252 struct irq_data *d = irq_domain_get_irq_data(domain, virq);253 struct xilinx_pcie *pcie = domain->host_data;254 255 mutex_lock(&pcie->map_lock);256 257 bitmap_release_region(pcie->msi_map, d->hwirq, order_base_2(nr_irqs));258 259 mutex_unlock(&pcie->map_lock);260}261 262static const struct irq_domain_ops xilinx_msi_domain_ops = {263 .alloc = xilinx_msi_domain_alloc,264 .free = xilinx_msi_domain_free,265};266 267static struct msi_domain_info xilinx_msi_info = {268 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |269 MSI_FLAG_NO_AFFINITY,270 .chip = &xilinx_msi_top_chip,271};272 273static int xilinx_allocate_msi_domains(struct xilinx_pcie *pcie)274{275 struct fwnode_handle *fwnode = dev_fwnode(pcie->dev);276 struct irq_domain *parent;277 278 parent = irq_domain_create_linear(fwnode, XILINX_NUM_MSI_IRQS,279 &xilinx_msi_domain_ops, pcie);280 if (!parent) {281 dev_err(pcie->dev, "failed to create IRQ domain\n");282 return -ENOMEM;283 }284 irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS);285 286 pcie->msi_domain = pci_msi_create_irq_domain(fwnode, &xilinx_msi_info, parent);287 if (!pcie->msi_domain) {288 dev_err(pcie->dev, "failed to create MSI domain\n");289 irq_domain_remove(parent);290 return -ENOMEM;291 }292 293 return 0;294}295 296static void xilinx_free_msi_domains(struct xilinx_pcie *pcie)297{298 struct irq_domain *parent = pcie->msi_domain->parent;299 300 irq_domain_remove(pcie->msi_domain);301 irq_domain_remove(parent);302}303 304/* INTx Functions */305 306/**307 * xilinx_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid308 * @domain: IRQ domain309 * @irq: Virtual IRQ number310 * @hwirq: HW interrupt number311 *312 * Return: Always returns 0.313 */314static int xilinx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,315 irq_hw_number_t hwirq)316{317 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);318 irq_set_chip_data(irq, domain->host_data);319 320 return 0;321}322 323/* INTx IRQ Domain operations */324static const struct irq_domain_ops intx_domain_ops = {325 .map = xilinx_pcie_intx_map,326 .xlate = pci_irqd_intx_xlate,327};328 329/* PCIe HW Functions */330 331/**332 * xilinx_pcie_intr_handler - Interrupt Service Handler333 * @irq: IRQ number334 * @data: PCIe port information335 *336 * Return: IRQ_HANDLED on success and IRQ_NONE on failure337 */338static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)339{340 struct xilinx_pcie *pcie = (struct xilinx_pcie *)data;341 struct device *dev = pcie->dev;342 u32 val, mask, status;343 344 /* Read interrupt decode and mask registers */345 val = pcie_read(pcie, XILINX_PCIE_REG_IDR);346 mask = pcie_read(pcie, XILINX_PCIE_REG_IMR);347 348 status = val & mask;349 if (!status)350 return IRQ_NONE;351 352 if (status & XILINX_PCIE_INTR_LINK_DOWN)353 dev_warn(dev, "Link Down\n");354 355 if (status & XILINX_PCIE_INTR_ECRC_ERR)356 dev_warn(dev, "ECRC failed\n");357 358 if (status & XILINX_PCIE_INTR_STR_ERR)359 dev_warn(dev, "Streaming error\n");360 361 if (status & XILINX_PCIE_INTR_HOT_RESET)362 dev_info(dev, "Hot reset\n");363 364 if (status & XILINX_PCIE_INTR_CFG_TIMEOUT)365 dev_warn(dev, "ECAM access timeout\n");366 367 if (status & XILINX_PCIE_INTR_CORRECTABLE) {368 dev_warn(dev, "Correctable error message\n");369 xilinx_pcie_clear_err_interrupts(pcie);370 }371 372 if (status & XILINX_PCIE_INTR_NONFATAL) {373 dev_warn(dev, "Non fatal error message\n");374 xilinx_pcie_clear_err_interrupts(pcie);375 }376 377 if (status & XILINX_PCIE_INTR_FATAL) {378 dev_warn(dev, "Fatal error message\n");379 xilinx_pcie_clear_err_interrupts(pcie);380 }381 382 if (status & (XILINX_PCIE_INTR_INTX | XILINX_PCIE_INTR_MSI)) {383 struct irq_domain *domain;384 385 val = pcie_read(pcie, XILINX_PCIE_REG_RPIFR1);386 387 /* Check whether interrupt valid */388 if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {389 dev_warn(dev, "RP Intr FIFO1 read error\n");390 goto error;391 }392 393 /* Decode the IRQ number */394 if (val & XILINX_PCIE_RPIFR1_MSI_INTR) {395 val = pcie_read(pcie, XILINX_PCIE_REG_RPIFR2) &396 XILINX_PCIE_RPIFR2_MSG_DATA;397 domain = pcie->msi_domain->parent;398 } else {399 val = (val & XILINX_PCIE_RPIFR1_INTR_MASK) >>400 XILINX_PCIE_RPIFR1_INTR_SHIFT;401 domain = pcie->leg_domain;402 }403 404 /* Clear interrupt FIFO register 1 */405 pcie_write(pcie, XILINX_PCIE_RPIFR1_ALL_MASK,406 XILINX_PCIE_REG_RPIFR1);407 408 generic_handle_domain_irq(domain, val);409 }410 411 if (status & XILINX_PCIE_INTR_SLV_UNSUPP)412 dev_warn(dev, "Slave unsupported request\n");413 414 if (status & XILINX_PCIE_INTR_SLV_UNEXP)415 dev_warn(dev, "Slave unexpected completion\n");416 417 if (status & XILINX_PCIE_INTR_SLV_COMPL)418 dev_warn(dev, "Slave completion timeout\n");419 420 if (status & XILINX_PCIE_INTR_SLV_ERRP)421 dev_warn(dev, "Slave Error Poison\n");422 423 if (status & XILINX_PCIE_INTR_SLV_CMPABT)424 dev_warn(dev, "Slave Completer Abort\n");425 426 if (status & XILINX_PCIE_INTR_SLV_ILLBUR)427 dev_warn(dev, "Slave Illegal Burst\n");428 429 if (status & XILINX_PCIE_INTR_MST_DECERR)430 dev_warn(dev, "Master decode error\n");431 432 if (status & XILINX_PCIE_INTR_MST_SLVERR)433 dev_warn(dev, "Master slave error\n");434 435 if (status & XILINX_PCIE_INTR_MST_ERRP)436 dev_warn(dev, "Master error poison\n");437 438error:439 /* Clear the Interrupt Decode register */440 pcie_write(pcie, status, XILINX_PCIE_REG_IDR);441 442 return IRQ_HANDLED;443}444 445/**446 * xilinx_pcie_init_irq_domain - Initialize IRQ domain447 * @pcie: PCIe port information448 *449 * Return: '0' on success and error value on failure450 */451static int xilinx_pcie_init_irq_domain(struct xilinx_pcie *pcie)452{453 struct device *dev = pcie->dev;454 struct device_node *pcie_intc_node;455 int ret;456 457 /* Setup INTx */458 pcie_intc_node = of_get_next_child(dev->of_node, NULL);459 if (!pcie_intc_node) {460 dev_err(dev, "No PCIe Intc node found\n");461 return -ENODEV;462 }463 464 pcie->leg_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,465 &intx_domain_ops,466 pcie);467 of_node_put(pcie_intc_node);468 if (!pcie->leg_domain) {469 dev_err(dev, "Failed to get a INTx IRQ domain\n");470 return -ENODEV;471 }472 473 /* Setup MSI */474 if (IS_ENABLED(CONFIG_PCI_MSI)) {475 phys_addr_t pa = ALIGN_DOWN(virt_to_phys(pcie), SZ_4K);476 477 ret = xilinx_allocate_msi_domains(pcie);478 if (ret)479 return ret;480 481 pcie_write(pcie, upper_32_bits(pa), XILINX_PCIE_REG_MSIBASE1);482 pcie_write(pcie, lower_32_bits(pa), XILINX_PCIE_REG_MSIBASE2);483 }484 485 return 0;486}487 488/**489 * xilinx_pcie_init_port - Initialize hardware490 * @pcie: PCIe port information491 */492static void xilinx_pcie_init_port(struct xilinx_pcie *pcie)493{494 struct device *dev = pcie->dev;495 496 if (xilinx_pcie_link_up(pcie))497 dev_info(dev, "PCIe Link is UP\n");498 else499 dev_info(dev, "PCIe Link is DOWN\n");500 501 /* Disable all interrupts */502 pcie_write(pcie, ~XILINX_PCIE_IDR_ALL_MASK,503 XILINX_PCIE_REG_IMR);504 505 /* Clear pending interrupts */506 pcie_write(pcie, pcie_read(pcie, XILINX_PCIE_REG_IDR) &507 XILINX_PCIE_IMR_ALL_MASK,508 XILINX_PCIE_REG_IDR);509 510 /* Enable all interrupts we handle */511 pcie_write(pcie, XILINX_PCIE_IMR_ENABLE_MASK, XILINX_PCIE_REG_IMR);512 513 /* Enable the Bridge enable bit */514 pcie_write(pcie, pcie_read(pcie, XILINX_PCIE_REG_RPSC) |515 XILINX_PCIE_REG_RPSC_BEN,516 XILINX_PCIE_REG_RPSC);517}518 519/**520 * xilinx_pcie_parse_dt - Parse Device tree521 * @pcie: PCIe port information522 *523 * Return: '0' on success and error value on failure524 */525static int xilinx_pcie_parse_dt(struct xilinx_pcie *pcie)526{527 struct device *dev = pcie->dev;528 struct device_node *node = dev->of_node;529 struct resource regs;530 unsigned int irq;531 int err;532 533 err = of_address_to_resource(node, 0, ®s);534 if (err) {535 dev_err(dev, "missing \"reg\" property\n");536 return err;537 }538 539 pcie->reg_base = devm_pci_remap_cfg_resource(dev, ®s);540 if (IS_ERR(pcie->reg_base))541 return PTR_ERR(pcie->reg_base);542 543 irq = irq_of_parse_and_map(node, 0);544 err = devm_request_irq(dev, irq, xilinx_pcie_intr_handler,545 IRQF_SHARED | IRQF_NO_THREAD,546 "xilinx-pcie", pcie);547 if (err) {548 dev_err(dev, "unable to request irq %d\n", irq);549 return err;550 }551 552 return 0;553}554 555/**556 * xilinx_pcie_probe - Probe function557 * @pdev: Platform device pointer558 *559 * Return: '0' on success and error value on failure560 */561static int xilinx_pcie_probe(struct platform_device *pdev)562{563 struct device *dev = &pdev->dev;564 struct xilinx_pcie *pcie;565 struct pci_host_bridge *bridge;566 int err;567 568 if (!dev->of_node)569 return -ENODEV;570 571 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));572 if (!bridge)573 return -ENODEV;574 575 pcie = pci_host_bridge_priv(bridge);576 mutex_init(&pcie->map_lock);577 pcie->dev = dev;578 579 err = xilinx_pcie_parse_dt(pcie);580 if (err) {581 dev_err(dev, "Parsing DT failed\n");582 return err;583 }584 585 xilinx_pcie_init_port(pcie);586 587 err = xilinx_pcie_init_irq_domain(pcie);588 if (err) {589 dev_err(dev, "Failed creating IRQ Domain\n");590 return err;591 }592 593 bridge->sysdata = pcie;594 bridge->ops = &xilinx_pcie_ops;595 596 err = pci_host_probe(bridge);597 if (err)598 xilinx_free_msi_domains(pcie);599 600 return err;601}602 603static const struct of_device_id xilinx_pcie_of_match[] = {604 { .compatible = "xlnx,axi-pcie-host-1.00.a", },605 {}606};607 608static struct platform_driver xilinx_pcie_driver = {609 .driver = {610 .name = "xilinx-pcie",611 .of_match_table = xilinx_pcie_of_match,612 .suppress_bind_attrs = true,613 },614 .probe = xilinx_pcie_probe,615};616builtin_platform_driver(xilinx_pcie_driver);617