274 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * PLDA PCIe host controller driver4 */5 6#ifndef _PCIE_PLDA_H7#define _PCIE_PLDA_H8 9/* Number of MSI IRQs */10#define PLDA_MAX_NUM_MSI_IRQS 3211 12/* PCIe Bridge Phy Regs */13#define GEN_SETTINGS 0x8014#define RP_ENABLE 115#define PCIE_PCI_IDS_DW1 0x9c16#define IDS_CLASS_CODE_SHIFT 1617#define REVISION_ID_MASK GENMASK(7, 0)18#define CLASS_CODE_ID_MASK GENMASK(31, 8)19#define PCIE_PCI_IRQ_DW0 0xa820#define MSIX_CAP_MASK BIT(31)21#define NUM_MSI_MSGS_MASK GENMASK(6, 4)22#define NUM_MSI_MSGS_SHIFT 423#define PCI_MISC 0xb424#define PHY_FUNCTION_DIS BIT(15)25#define PCIE_WINROM 0xfc26#define PREF_MEM_WIN_64_SUPPORT BIT(3)27 28#define IMASK_LOCAL 0x18029#define DMA_END_ENGINE_0_MASK 0x00000000u30#define DMA_END_ENGINE_0_SHIFT 031#define DMA_END_ENGINE_1_MASK 0x00000000u32#define DMA_END_ENGINE_1_SHIFT 133#define DMA_ERROR_ENGINE_0_MASK 0x00000100u34#define DMA_ERROR_ENGINE_0_SHIFT 835#define DMA_ERROR_ENGINE_1_MASK 0x00000200u36#define DMA_ERROR_ENGINE_1_SHIFT 937#define A_ATR_EVT_POST_ERR_MASK 0x00010000u38#define A_ATR_EVT_POST_ERR_SHIFT 1639#define A_ATR_EVT_FETCH_ERR_MASK 0x00020000u40#define A_ATR_EVT_FETCH_ERR_SHIFT 1741#define A_ATR_EVT_DISCARD_ERR_MASK 0x00040000u42#define A_ATR_EVT_DISCARD_ERR_SHIFT 1843#define A_ATR_EVT_DOORBELL_MASK 0x00000000u44#define A_ATR_EVT_DOORBELL_SHIFT 1945#define P_ATR_EVT_POST_ERR_MASK 0x00100000u46#define P_ATR_EVT_POST_ERR_SHIFT 2047#define P_ATR_EVT_FETCH_ERR_MASK 0x00200000u48#define P_ATR_EVT_FETCH_ERR_SHIFT 2149#define P_ATR_EVT_DISCARD_ERR_MASK 0x00400000u50#define P_ATR_EVT_DISCARD_ERR_SHIFT 2251#define P_ATR_EVT_DOORBELL_MASK 0x00000000u52#define P_ATR_EVT_DOORBELL_SHIFT 2353#define PM_MSI_INT_INTA_MASK 0x01000000u54#define PM_MSI_INT_INTA_SHIFT 2455#define PM_MSI_INT_INTB_MASK 0x02000000u56#define PM_MSI_INT_INTB_SHIFT 2557#define PM_MSI_INT_INTC_MASK 0x04000000u58#define PM_MSI_INT_INTC_SHIFT 2659#define PM_MSI_INT_INTD_MASK 0x08000000u60#define PM_MSI_INT_INTD_SHIFT 2761#define PM_MSI_INT_INTX_MASK 0x0f000000u62#define PM_MSI_INT_INTX_SHIFT 2463#define PM_MSI_INT_MSI_MASK 0x10000000u64#define PM_MSI_INT_MSI_SHIFT 2865#define PM_MSI_INT_AER_EVT_MASK 0x20000000u66#define PM_MSI_INT_AER_EVT_SHIFT 2967#define PM_MSI_INT_EVENTS_MASK 0x40000000u68#define PM_MSI_INT_EVENTS_SHIFT 3069#define PM_MSI_INT_SYS_ERR_MASK 0x80000000u70#define PM_MSI_INT_SYS_ERR_SHIFT 3171#define SYS_AND_MSI_MASK GENMASK(31, 28)72#define NUM_LOCAL_EVENTS 1573#define ISTATUS_LOCAL 0x18474#define IMASK_HOST 0x18875#define ISTATUS_HOST 0x18c76#define IMSI_ADDR 0x19077#define ISTATUS_MSI 0x19478#define PMSG_SUPPORT_RX 0x3f079#define PMSG_LTR_SUPPORT BIT(2)80 81/* PCIe Master table init defines */82#define ATR0_PCIE_WIN0_SRCADDR_PARAM 0x600u83#define ATR0_PCIE_ATR_SIZE 0x2584#define ATR0_PCIE_ATR_SIZE_SHIFT 185#define ATR0_PCIE_WIN0_SRC_ADDR 0x604u86#define ATR0_PCIE_WIN0_TRSL_ADDR_LSB 0x608u87#define ATR0_PCIE_WIN0_TRSL_ADDR_UDW 0x60cu88#define ATR0_PCIE_WIN0_TRSL_PARAM 0x610u89 90/* PCIe AXI slave table init defines */91#define ATR0_AXI4_SLV0_SRCADDR_PARAM 0x800u92#define ATR_SIZE_SHIFT 193#define ATR_IMPL_ENABLE 194#define ATR0_AXI4_SLV0_SRC_ADDR 0x804u95#define ATR0_AXI4_SLV0_TRSL_ADDR_LSB 0x808u96#define ATR0_AXI4_SLV0_TRSL_ADDR_UDW 0x80cu97#define ATR0_AXI4_SLV0_TRSL_PARAM 0x810u98#define PCIE_TX_RX_INTERFACE 0x00000000u99#define PCIE_CONFIG_INTERFACE 0x00000001u100 101#define CONFIG_SPACE_ADDR_OFFSET 0x1000u102 103#define ATR_ENTRY_SIZE 32104 105enum plda_int_event {106 PLDA_AXI_POST_ERR,107 PLDA_AXI_FETCH_ERR,108 PLDA_AXI_DISCARD_ERR,109 PLDA_AXI_DOORBELL,110 PLDA_PCIE_POST_ERR,111 PLDA_PCIE_FETCH_ERR,112 PLDA_PCIE_DISCARD_ERR,113 PLDA_PCIE_DOORBELL,114 PLDA_INTX,115 PLDA_MSI,116 PLDA_AER_EVENT,117 PLDA_MISC_EVENTS,118 PLDA_SYS_ERR,119 PLDA_INT_EVENT_NUM120};121 122#define PLDA_NUM_DMA_EVENTS 16123 124#define EVENT_PM_MSI_INT_INTX (PLDA_NUM_DMA_EVENTS + PLDA_INTX)125#define EVENT_PM_MSI_INT_MSI (PLDA_NUM_DMA_EVENTS + PLDA_MSI)126#define PLDA_MAX_EVENT_NUM (PLDA_NUM_DMA_EVENTS + PLDA_INT_EVENT_NUM)127 128/*129 * PLDA interrupt register130 *131 * 31 27 23 15 7 0132 * +--+--+--+-+------+-+-+-+-+-+-+-+-+-----------+-----------+133 * |12|11|10|9| intx |7|6|5|4|3|2|1|0| DMA error | DMA end |134 * +--+--+--+-+------+-+-+-+-+-+-+-+-+-----------+-----------+135 * event bit136 * 0-7 (0-7) DMA interrupt end : reserved for vendor implement137 * 8-15 (8-15) DMA error : reserved for vendor implement138 * 16 (16) AXI post error (PLDA_AXI_POST_ERR)139 * 17 (17) AXI fetch error (PLDA_AXI_FETCH_ERR)140 * 18 (18) AXI discard error (PLDA_AXI_DISCARD_ERR)141 * 19 (19) AXI doorbell (PLDA_PCIE_DOORBELL)142 * 20 (20) PCIe post error (PLDA_PCIE_POST_ERR)143 * 21 (21) PCIe fetch error (PLDA_PCIE_FETCH_ERR)144 * 22 (22) PCIe discard error (PLDA_PCIE_DISCARD_ERR)145 * 23 (23) PCIe doorbell (PLDA_PCIE_DOORBELL)146 * 24 (27-24) INTx interruts (PLDA_INTX)147 * 25 (28): MSI interrupt (PLDA_MSI)148 * 26 (29): AER event (PLDA_AER_EVENT)149 * 27 (30): PM/LTR/Hotplug (PLDA_MISC_EVENTS)150 * 28 (31): System error (PLDA_SYS_ERR)151 */152 153struct plda_pcie_rp;154 155struct plda_event_ops {156 u32 (*get_events)(struct plda_pcie_rp *pcie);157};158 159struct plda_pcie_host_ops {160 int (*host_init)(struct plda_pcie_rp *pcie);161 void (*host_deinit)(struct plda_pcie_rp *pcie);162};163 164struct plda_msi {165 struct mutex lock; /* Protect used bitmap */166 struct irq_domain *msi_domain;167 struct irq_domain *dev_domain;168 u32 num_vectors;169 u64 vector_phy;170 DECLARE_BITMAP(used, PLDA_MAX_NUM_MSI_IRQS);171};172 173struct plda_pcie_rp {174 struct device *dev;175 struct pci_host_bridge *bridge;176 struct irq_domain *intx_domain;177 struct irq_domain *event_domain;178 raw_spinlock_t lock;179 struct plda_msi msi;180 const struct plda_event_ops *event_ops;181 const struct irq_chip *event_irq_chip;182 const struct plda_pcie_host_ops *host_ops;183 void __iomem *bridge_addr;184 void __iomem *config_base;185 unsigned long events_bitmap;186 int irq;187 int msi_irq;188 int intx_irq;189 int num_events;190};191 192struct plda_event {193 int (*request_event_irq)(struct plda_pcie_rp *pcie,194 int event_irq, int event);195 int intx_event;196 int msi_event;197};198 199void __iomem *plda_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,200 int where);201int plda_init_interrupts(struct platform_device *pdev,202 struct plda_pcie_rp *port,203 const struct plda_event *event);204void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index,205 phys_addr_t axi_addr, phys_addr_t pci_addr,206 size_t size);207int plda_pcie_setup_iomems(struct pci_host_bridge *bridge,208 struct plda_pcie_rp *port);209int plda_pcie_host_init(struct plda_pcie_rp *port, struct pci_ops *ops,210 const struct plda_event *plda_event);211void plda_pcie_host_deinit(struct plda_pcie_rp *pcie);212 213static inline void plda_set_default_msi(struct plda_msi *msi)214{215 msi->vector_phy = IMSI_ADDR;216 msi->num_vectors = PLDA_MAX_NUM_MSI_IRQS;217}218 219static inline void plda_pcie_enable_root_port(struct plda_pcie_rp *plda)220{221 u32 value;222 223 value = readl_relaxed(plda->bridge_addr + GEN_SETTINGS);224 value |= RP_ENABLE;225 writel_relaxed(value, plda->bridge_addr + GEN_SETTINGS);226}227 228static inline void plda_pcie_set_standard_class(struct plda_pcie_rp *plda)229{230 u32 value;231 232 /* set class code and reserve revision id */233 value = readl_relaxed(plda->bridge_addr + PCIE_PCI_IDS_DW1);234 value &= REVISION_ID_MASK;235 value |= (PCI_CLASS_BRIDGE_PCI << IDS_CLASS_CODE_SHIFT);236 writel_relaxed(value, plda->bridge_addr + PCIE_PCI_IDS_DW1);237}238 239static inline void plda_pcie_set_pref_win_64bit(struct plda_pcie_rp *plda)240{241 u32 value;242 243 value = readl_relaxed(plda->bridge_addr + PCIE_WINROM);244 value |= PREF_MEM_WIN_64_SUPPORT;245 writel_relaxed(value, plda->bridge_addr + PCIE_WINROM);246}247 248static inline void plda_pcie_disable_ltr(struct plda_pcie_rp *plda)249{250 u32 value;251 252 value = readl_relaxed(plda->bridge_addr + PMSG_SUPPORT_RX);253 value &= ~PMSG_LTR_SUPPORT;254 writel_relaxed(value, plda->bridge_addr + PMSG_SUPPORT_RX);255}256 257static inline void plda_pcie_disable_func(struct plda_pcie_rp *plda)258{259 u32 value;260 261 value = readl_relaxed(plda->bridge_addr + PCI_MISC);262 value |= PHY_FUNCTION_DIS;263 writel_relaxed(value, plda->bridge_addr + PCI_MISC);264}265 266static inline void plda_pcie_write_rc_bar(struct plda_pcie_rp *plda, u64 val)267{268 void __iomem *addr = plda->bridge_addr + CONFIG_SPACE_ADDR_OFFSET;269 270 writel_relaxed(lower_32_bits(val), addr + PCI_BASE_ADDRESS_0);271 writel_relaxed(upper_32_bits(val), addr + PCI_BASE_ADDRESS_1);272}273#endif /* _PCIE_PLDA_H */274