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1/* SPDX-License-Identifier: GPL-2.0+ */2#ifndef __IBMPHP_H3#define __IBMPHP_H4 5/*6 * IBM Hot Plug Controller Driver7 *8 * Written By: Jyoti Shah, Tong Yu, Irene Zubarev, IBM Corporation9 *10 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)11 * Copyright (C) 2001-2003 IBM Corp.12 *13 * All rights reserved.14 *15 * Send feedback to <gregkh@us.ibm.com>16 *17 */18 19#include <linux/pci_hotplug.h>20#include <linux/pci_regs.h>21 22extern int ibmphp_debug;23 24#if !defined(MODULE)25 #define MY_NAME "ibmphpd"26#else27 #define MY_NAME THIS_MODULE->name28#endif29#define debug(fmt, arg...) do { if (ibmphp_debug == 1) printk(KERN_DEBUG "%s: " fmt, MY_NAME, ## arg); } while (0)30#define debug_pci(fmt, arg...) do { if (ibmphp_debug) printk(KERN_DEBUG "%s: " fmt, MY_NAME, ## arg); } while (0)31#define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME, ## arg)32#define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME, ## arg)33#define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)34 35 36/* EBDA stuff */37 38/***********************************************************39* SLOT CAPABILITY *40***********************************************************/41 42#define EBDA_SLOT_133_MAX 0x2043#define EBDA_SLOT_100_MAX 0x1044#define EBDA_SLOT_66_MAX 0x0245#define EBDA_SLOT_PCIX_CAP 0x0846 47 48/************************************************************49* RESOURCE TYPE *50************************************************************/51 52#define EBDA_RSRC_TYPE_MASK 0x0353#define EBDA_IO_RSRC_TYPE 0x0054#define EBDA_MEM_RSRC_TYPE 0x0155#define EBDA_PFM_RSRC_TYPE 0x0356#define EBDA_RES_RSRC_TYPE 0x0257 58 59/*************************************************************60* IO RESTRICTION TYPE *61*************************************************************/62 63#define EBDA_IO_RESTRI_MASK 0x0c64#define EBDA_NO_RESTRI 0x0065#define EBDA_AVO_VGA_ADDR 0x0466#define EBDA_AVO_VGA_ADDR_AND_ALIA 0x0867#define EBDA_AVO_ISA_ADDR 0x0c68 69 70/**************************************************************71* DEVICE TYPE DEF *72**************************************************************/73 74#define EBDA_DEV_TYPE_MASK 0x1075#define EBDA_PCI_DEV 0x1076#define EBDA_NON_PCI_DEV 0x0077 78 79/***************************************************************80* PRIMARY DEF DEFINITION *81***************************************************************/82 83#define EBDA_PRI_DEF_MASK 0x2084#define EBDA_PRI_PCI_BUS_INFO 0x2085#define EBDA_NORM_DEV_RSRC_INFO 0x0086 87 88//--------------------------------------------------------------89// RIO TABLE DATA STRUCTURE90//--------------------------------------------------------------91 92struct rio_table_hdr {93 u8 ver_num;94 u8 scal_count;95 u8 riodev_count;96 u16 offset;97};98 99//-------------------------------------------------------------100// SCALABILITY DETAIL101//-------------------------------------------------------------102 103struct scal_detail {104 u8 node_id;105 u32 cbar;106 u8 port0_node_connect;107 u8 port0_port_connect;108 u8 port1_node_connect;109 u8 port1_port_connect;110 u8 port2_node_connect;111 u8 port2_port_connect;112 u8 chassis_num;113// struct list_head scal_detail_list;114};115 116//--------------------------------------------------------------117// RIO DETAIL118//--------------------------------------------------------------119 120struct rio_detail {121 u8 rio_node_id;122 u32 bbar;123 u8 rio_type;124 u8 owner_id;125 u8 port0_node_connect;126 u8 port0_port_connect;127 u8 port1_node_connect;128 u8 port1_port_connect;129 u8 first_slot_num;130 u8 status;131 u8 wpindex;132 u8 chassis_num;133 struct list_head rio_detail_list;134};135 136struct opt_rio {137 u8 rio_type;138 u8 chassis_num;139 u8 first_slot_num;140 u8 middle_num;141 struct list_head opt_rio_list;142};143 144struct opt_rio_lo {145 u8 rio_type;146 u8 chassis_num;147 u8 first_slot_num;148 u8 middle_num;149 u8 pack_count;150 struct list_head opt_rio_lo_list;151};152 153/****************************************************************154* HPC DESCRIPTOR NODE *155****************************************************************/156 157struct ebda_hpc_list {158 u8 format;159 u16 num_ctlrs;160 short phys_addr;161// struct list_head ebda_hpc_list;162};163/*****************************************************************164* IN HPC DATA STRUCTURE, THE ASSOCIATED SLOT AND BUS *165* STRUCTURE *166*****************************************************************/167 168struct ebda_hpc_slot {169 u8 slot_num;170 u32 slot_bus_num;171 u8 ctl_index;172 u8 slot_cap;173};174 175struct ebda_hpc_bus {176 u32 bus_num;177 u8 slots_at_33_conv;178 u8 slots_at_66_conv;179 u8 slots_at_66_pcix;180 u8 slots_at_100_pcix;181 u8 slots_at_133_pcix;182};183 184 185/********************************************************************186* THREE TYPE OF HOT PLUG CONTROLLER *187********************************************************************/188 189struct isa_ctlr_access {190 u16 io_start;191 u16 io_end;192};193 194struct pci_ctlr_access {195 u8 bus;196 u8 dev_fun;197};198 199struct wpeg_i2c_ctlr_access {200 ulong wpegbbar;201 u8 i2c_addr;202};203 204#define HPC_DEVICE_ID 0x0246205#define HPC_SUBSYSTEM_ID 0x0247206#define HPC_PCI_OFFSET 0x40207/*************************************************************************208* RSTC DESCRIPTOR NODE *209*************************************************************************/210 211struct ebda_rsrc_list {212 u8 format;213 u16 num_entries;214 u16 phys_addr;215 struct ebda_rsrc_list *next;216};217 218 219/***************************************************************************220* PCI RSRC NODE *221***************************************************************************/222 223struct ebda_pci_rsrc {224 u8 rsrc_type;225 u8 bus_num;226 u8 dev_fun;227 u32 start_addr;228 u32 end_addr;229 u8 marked; /* for NVRAM */230 struct list_head ebda_pci_rsrc_list;231};232 233 234/***********************************************************235* BUS_INFO DATE STRUCTURE *236***********************************************************/237 238struct bus_info {239 u8 slot_min;240 u8 slot_max;241 u8 slot_count;242 u8 busno;243 u8 controller_id;244 u8 current_speed;245 u8 current_bus_mode;246 u8 index;247 u8 slots_at_33_conv;248 u8 slots_at_66_conv;249 u8 slots_at_66_pcix;250 u8 slots_at_100_pcix;251 u8 slots_at_133_pcix;252 struct list_head bus_info_list;253};254 255 256/***********************************************************257* GLOBAL VARIABLES *258***********************************************************/259extern struct list_head ibmphp_ebda_pci_rsrc_head;260extern struct list_head ibmphp_slot_head;261/***********************************************************262* FUNCTION PROTOTYPES *263***********************************************************/264 265void ibmphp_free_ebda_hpc_queue(void);266int ibmphp_access_ebda(void);267struct slot *ibmphp_get_slot_from_physical_num(u8);268void ibmphp_free_bus_info_queue(void);269void ibmphp_free_ebda_pci_rsrc_queue(void);270struct bus_info *ibmphp_find_same_bus_num(u32);271int ibmphp_get_bus_index(u8);272u16 ibmphp_get_total_controllers(void);273int ibmphp_register_pci(void);274 275/* passed parameters */276#define MEM 0277#define IO 1278#define PFMEM 2279 280/* bit masks */281#define RESTYPE 0x03282#define IOMASK 0x00 /* will need to take its complement */283#define MMASK 0x01284#define PFMASK 0x03285#define PCIDEVMASK 0x10 /* we should always have PCI devices */286#define PRIMARYBUSMASK 0x20287 288/* pci specific defines */289#define PCI_VENDOR_ID_NOTVALID 0xFFFF290#define PCI_HEADER_TYPE_MULTIDEVICE (PCI_HEADER_TYPE_MFD|PCI_HEADER_TYPE_NORMAL)291#define PCI_HEADER_TYPE_MULTIBRIDGE (PCI_HEADER_TYPE_MFD|PCI_HEADER_TYPE_BRIDGE)292 293#define LATENCY 0x64294#define CACHE 64295#define DEVICEENABLE 0x015F /* CPQ has 0x0157 */296 297#define IOBRIDGE 0x1000 /* 4k */298#define MEMBRIDGE 0x100000 /* 1M */299 300/* irqs */301#define SCSI_IRQ 0x09302#define LAN_IRQ 0x0A303#define OTHER_IRQ 0x0B304 305/* Data Structures */306 307/* type is of the form x x xx xx308 * | | | |_ 00 - I/O, 01 - Memory, 11 - PFMemory309 * | | - 00 - No Restrictions, 01 - Avoid VGA, 10 - Avoid310 * | | VGA and their aliases, 11 - Avoid ISA311 * | - 1 - PCI device, 0 - non pci device312 * - 1 - Primary PCI Bus Information (0 if Normal device)313 * the IO restrictions [2:3] are only for primary buses314 */315 316 317/* we need this struct because there could be several resource blocks318 * allocated per primary bus in the EBDA319 */320struct range_node {321 int rangeno;322 u32 start;323 u32 end;324 struct range_node *next;325};326 327struct bus_node {328 u8 busno;329 int noIORanges;330 struct range_node *rangeIO;331 int noMemRanges;332 struct range_node *rangeMem;333 int noPFMemRanges;334 struct range_node *rangePFMem;335 int needIOUpdate;336 int needMemUpdate;337 int needPFMemUpdate;338 struct resource_node *firstIO; /* first IO resource on the Bus */339 struct resource_node *firstMem; /* first memory resource on the Bus */340 struct resource_node *firstPFMem; /* first prefetchable memory resource on the Bus */341 struct resource_node *firstPFMemFromMem; /* when run out of pfmem available, taking from Mem */342 struct list_head bus_list;343};344 345struct resource_node {346 int rangeno;347 u8 busno;348 u8 devfunc;349 u32 start;350 u32 end;351 u32 len;352 int type; /* MEM, IO, PFMEM */353 u8 fromMem; /* this is to indicate that the range is from354 * the Memory bucket rather than from PFMem */355 struct resource_node *next;356 struct resource_node *nextRange; /* for the other mem range on bus */357};358 359struct res_needed {360 u32 mem;361 u32 pfmem;362 u32 io;363 u8 not_correct; /* needed for return */364 int devices[32]; /* for device numbers behind this bridge */365};366 367/* functions */368 369int ibmphp_rsrc_init(void);370int ibmphp_add_resource(struct resource_node *);371int ibmphp_remove_resource(struct resource_node *);372int ibmphp_find_resource(struct bus_node *, u32, struct resource_node **, int);373int ibmphp_check_resource(struct resource_node *, u8);374int ibmphp_remove_bus(struct bus_node *, u8);375void ibmphp_free_resources(void);376int ibmphp_add_pfmem_from_mem(struct resource_node *);377struct bus_node *ibmphp_find_res_bus(u8);378void ibmphp_print_test(void); /* for debugging purposes */379 380int ibmphp_hpc_readslot(struct slot *, u8, u8 *);381int ibmphp_hpc_writeslot(struct slot *, u8);382void ibmphp_lock_operations(void);383void ibmphp_unlock_operations(void);384int ibmphp_hpc_start_poll_thread(void);385void ibmphp_hpc_stop_poll_thread(void);386 387//----------------------------------------------------------------------------388 389 390//----------------------------------------------------------------------------391// HPC return codes392//----------------------------------------------------------------------------393#define HPC_ERROR 0xFF394 395//-----------------------------------------------------------------------------396// BUS INFO397//-----------------------------------------------------------------------------398#define BUS_SPEED 0x30399#define BUS_MODE 0x40400#define BUS_MODE_PCIX 0x01401#define BUS_MODE_PCI 0x00402#define BUS_SPEED_2 0x20403#define BUS_SPEED_1 0x10404#define BUS_SPEED_33 0x00405#define BUS_SPEED_66 0x01406#define BUS_SPEED_100 0x02407#define BUS_SPEED_133 0x03408#define BUS_SPEED_66PCIX 0x04409#define BUS_SPEED_66UNKNOWN 0x05410#define BUS_STATUS_AVAILABLE 0x01411#define BUS_CONTROL_AVAILABLE 0x02412#define SLOT_LATCH_REGS_SUPPORTED 0x10413 414#define PRGM_MODEL_REV_LEVEL 0xF0415#define MAX_ADAPTER_NONE 0x09416 417//----------------------------------------------------------------------------418// HPC 'write' operations/commands419//----------------------------------------------------------------------------420// Command Code State Write to reg421// Machine at index422//------------------------- ---- ------- ------------423#define HPC_CTLR_ENABLEIRQ 0x00 // N 15424#define HPC_CTLR_DISABLEIRQ 0x01 // N 15425#define HPC_SLOT_OFF 0x02 // Y 0-14426#define HPC_SLOT_ON 0x03 // Y 0-14427#define HPC_SLOT_ATTNOFF 0x04 // N 0-14428#define HPC_SLOT_ATTNON 0x05 // N 0-14429#define HPC_CTLR_CLEARIRQ 0x06 // N 15430#define HPC_CTLR_RESET 0x07 // Y 15431#define HPC_CTLR_IRQSTEER 0x08 // N 15432#define HPC_BUS_33CONVMODE 0x09 // Y 31-34433#define HPC_BUS_66CONVMODE 0x0A // Y 31-34434#define HPC_BUS_66PCIXMODE 0x0B // Y 31-34435#define HPC_BUS_100PCIXMODE 0x0C // Y 31-34436#define HPC_BUS_133PCIXMODE 0x0D // Y 31-34437#define HPC_ALLSLOT_OFF 0x11 // Y 15438#define HPC_ALLSLOT_ON 0x12 // Y 15439#define HPC_SLOT_BLINKLED 0x13 // N 0-14440 441//----------------------------------------------------------------------------442// read commands443//----------------------------------------------------------------------------444#define READ_SLOTSTATUS 0x01445#define READ_EXTSLOTSTATUS 0x02446#define READ_BUSSTATUS 0x03447#define READ_CTLRSTATUS 0x04448#define READ_ALLSTAT 0x05449#define READ_ALLSLOT 0x06450#define READ_SLOTLATCHLOWREG 0x07451#define READ_REVLEVEL 0x08452#define READ_HPCOPTIONS 0x09453//----------------------------------------------------------------------------454// slot status455//----------------------------------------------------------------------------456#define HPC_SLOT_POWER 0x01457#define HPC_SLOT_CONNECT 0x02458#define HPC_SLOT_ATTN 0x04459#define HPC_SLOT_PRSNT2 0x08460#define HPC_SLOT_PRSNT1 0x10461#define HPC_SLOT_PWRGD 0x20462#define HPC_SLOT_BUS_SPEED 0x40463#define HPC_SLOT_LATCH 0x80464 465//----------------------------------------------------------------------------466// HPC_SLOT_POWER status return codes467//----------------------------------------------------------------------------468#define HPC_SLOT_POWER_OFF 0x00469#define HPC_SLOT_POWER_ON 0x01470 471//----------------------------------------------------------------------------472// HPC_SLOT_CONNECT status return codes473//----------------------------------------------------------------------------474#define HPC_SLOT_CONNECTED 0x00475#define HPC_SLOT_DISCONNECTED 0x01476 477//----------------------------------------------------------------------------478// HPC_SLOT_ATTN status return codes479//----------------------------------------------------------------------------480#define HPC_SLOT_ATTN_OFF 0x00481#define HPC_SLOT_ATTN_ON 0x01482#define HPC_SLOT_ATTN_BLINK 0x02483 484//----------------------------------------------------------------------------485// HPC_SLOT_PRSNT status return codes486//----------------------------------------------------------------------------487#define HPC_SLOT_EMPTY 0x00488#define HPC_SLOT_PRSNT_7 0x01489#define HPC_SLOT_PRSNT_15 0x02490#define HPC_SLOT_PRSNT_25 0x03491 492//----------------------------------------------------------------------------493// HPC_SLOT_PWRGD status return codes494//----------------------------------------------------------------------------495#define HPC_SLOT_PWRGD_FAULT_NONE 0x00496#define HPC_SLOT_PWRGD_GOOD 0x01497 498//----------------------------------------------------------------------------499// HPC_SLOT_BUS_SPEED status return codes500//----------------------------------------------------------------------------501#define HPC_SLOT_BUS_SPEED_OK 0x00502#define HPC_SLOT_BUS_SPEED_MISM 0x01503 504//----------------------------------------------------------------------------505// HPC_SLOT_LATCH status return codes506//----------------------------------------------------------------------------507#define HPC_SLOT_LATCH_OPEN 0x01 // NOTE : in PCI spec bit off = open508#define HPC_SLOT_LATCH_CLOSED 0x00 // NOTE : in PCI spec bit on = closed509 510 511//----------------------------------------------------------------------------512// extended slot status513//----------------------------------------------------------------------------514#define HPC_SLOT_PCIX 0x01515#define HPC_SLOT_SPEED1 0x02516#define HPC_SLOT_SPEED2 0x04517#define HPC_SLOT_BLINK_ATTN 0x08518#define HPC_SLOT_RSRVD1 0x10519#define HPC_SLOT_RSRVD2 0x20520#define HPC_SLOT_BUS_MODE 0x40521#define HPC_SLOT_RSRVD3 0x80522 523//----------------------------------------------------------------------------524// HPC_XSLOT_PCIX_CAP status return codes525//----------------------------------------------------------------------------526#define HPC_SLOT_PCIX_NO 0x00527#define HPC_SLOT_PCIX_YES 0x01528 529//----------------------------------------------------------------------------530// HPC_XSLOT_SPEED status return codes531//----------------------------------------------------------------------------532#define HPC_SLOT_SPEED_33 0x00533#define HPC_SLOT_SPEED_66 0x01534#define HPC_SLOT_SPEED_133 0x02535 536//----------------------------------------------------------------------------537// HPC_XSLOT_ATTN_BLINK status return codes538//----------------------------------------------------------------------------539#define HPC_SLOT_ATTN_BLINK_OFF 0x00540#define HPC_SLOT_ATTN_BLINK_ON 0x01541 542//----------------------------------------------------------------------------543// HPC_XSLOT_BUS_MODE status return codes544//----------------------------------------------------------------------------545#define HPC_SLOT_BUS_MODE_OK 0x00546#define HPC_SLOT_BUS_MODE_MISM 0x01547 548//----------------------------------------------------------------------------549// Controller status550//----------------------------------------------------------------------------551#define HPC_CTLR_WORKING 0x01552#define HPC_CTLR_FINISHED 0x02553#define HPC_CTLR_RESULT0 0x04554#define HPC_CTLR_RESULT1 0x08555#define HPC_CTLR_RESULE2 0x10556#define HPC_CTLR_RESULT3 0x20557#define HPC_CTLR_IRQ_ROUTG 0x40558#define HPC_CTLR_IRQ_PENDG 0x80559 560//----------------------------------------------------------------------------561// HPC_CTLR_WORKING status return codes562//----------------------------------------------------------------------------563#define HPC_CTLR_WORKING_NO 0x00564#define HPC_CTLR_WORKING_YES 0x01565 566//----------------------------------------------------------------------------567// HPC_CTLR_FINISHED status return codes568//----------------------------------------------------------------------------569#define HPC_CTLR_FINISHED_NO 0x00570#define HPC_CTLR_FINISHED_YES 0x01571 572//----------------------------------------------------------------------------573// HPC_CTLR_RESULT status return codes574//----------------------------------------------------------------------------575#define HPC_CTLR_RESULT_SUCCESS 0x00576#define HPC_CTLR_RESULT_FAILED 0x01577#define HPC_CTLR_RESULT_RSVD 0x02578#define HPC_CTLR_RESULT_NORESP 0x03579 580 581//----------------------------------------------------------------------------582// macro for slot info583//----------------------------------------------------------------------------584#define SLOT_POWER(s) ((u8) ((s & HPC_SLOT_POWER) \585 ? HPC_SLOT_POWER_ON : HPC_SLOT_POWER_OFF))586 587#define SLOT_CONNECT(s) ((u8) ((s & HPC_SLOT_CONNECT) \588 ? HPC_SLOT_DISCONNECTED : HPC_SLOT_CONNECTED))589 590#define SLOT_ATTN(s, es) ((u8) ((es & HPC_SLOT_BLINK_ATTN) \591 ? HPC_SLOT_ATTN_BLINK \592 : ((s & HPC_SLOT_ATTN) ? HPC_SLOT_ATTN_ON : HPC_SLOT_ATTN_OFF)))593 594#define SLOT_PRESENT(s) ((u8) ((s & HPC_SLOT_PRSNT1) \595 ? ((s & HPC_SLOT_PRSNT2) ? HPC_SLOT_EMPTY : HPC_SLOT_PRSNT_15) \596 : ((s & HPC_SLOT_PRSNT2) ? HPC_SLOT_PRSNT_25 : HPC_SLOT_PRSNT_7)))597 598#define SLOT_PWRGD(s) ((u8) ((s & HPC_SLOT_PWRGD) \599 ? HPC_SLOT_PWRGD_GOOD : HPC_SLOT_PWRGD_FAULT_NONE))600 601#define SLOT_BUS_SPEED(s) ((u8) ((s & HPC_SLOT_BUS_SPEED) \602 ? HPC_SLOT_BUS_SPEED_MISM : HPC_SLOT_BUS_SPEED_OK))603 604#define SLOT_LATCH(s) ((u8) ((s & HPC_SLOT_LATCH) \605 ? HPC_SLOT_LATCH_CLOSED : HPC_SLOT_LATCH_OPEN))606 607#define SLOT_PCIX(es) ((u8) ((es & HPC_SLOT_PCIX) \608 ? HPC_SLOT_PCIX_YES : HPC_SLOT_PCIX_NO))609 610#define SLOT_SPEED(es) ((u8) ((es & HPC_SLOT_SPEED2) \611 ? ((es & HPC_SLOT_SPEED1) ? HPC_SLOT_SPEED_133 \612 : HPC_SLOT_SPEED_66) \613 : HPC_SLOT_SPEED_33))614 615#define SLOT_BUS_MODE(es) ((u8) ((es & HPC_SLOT_BUS_MODE) \616 ? HPC_SLOT_BUS_MODE_MISM : HPC_SLOT_BUS_MODE_OK))617 618//--------------------------------------------------------------------------619// macro for bus info620//---------------------------------------------------------------------------621#define CURRENT_BUS_SPEED(s) ((u8) (s & BUS_SPEED_2) \622 ? ((s & BUS_SPEED_1) ? BUS_SPEED_133 : BUS_SPEED_100) \623 : ((s & BUS_SPEED_1) ? BUS_SPEED_66 : BUS_SPEED_33))624 625#define CURRENT_BUS_MODE(s) ((u8) (s & BUS_MODE) ? BUS_MODE_PCIX : BUS_MODE_PCI)626 627#define READ_BUS_STATUS(s) ((u8) (s->options & BUS_STATUS_AVAILABLE))628 629#define READ_BUS_MODE(s) ((s->revision & PRGM_MODEL_REV_LEVEL) >= 0x20)630 631#define SET_BUS_STATUS(s) ((u8) (s->options & BUS_CONTROL_AVAILABLE))632 633#define READ_SLOT_LATCH(s) ((u8) (s->options & SLOT_LATCH_REGS_SUPPORTED))634 635//----------------------------------------------------------------------------636// macro for controller info637//----------------------------------------------------------------------------638#define CTLR_WORKING(c) ((u8) ((c & HPC_CTLR_WORKING) \639 ? HPC_CTLR_WORKING_YES : HPC_CTLR_WORKING_NO))640#define CTLR_FINISHED(c) ((u8) ((c & HPC_CTLR_FINISHED) \641 ? HPC_CTLR_FINISHED_YES : HPC_CTLR_FINISHED_NO))642#define CTLR_RESULT(c) ((u8) ((c & HPC_CTLR_RESULT1) \643 ? ((c & HPC_CTLR_RESULT0) ? HPC_CTLR_RESULT_NORESP \644 : HPC_CTLR_RESULT_RSVD) \645 : ((c & HPC_CTLR_RESULT0) ? HPC_CTLR_RESULT_FAILED \646 : HPC_CTLR_RESULT_SUCCESS)))647 648// command that affect the state machine of HPC649#define NEEDTOCHECK_CMDSTATUS(c) ((c == HPC_SLOT_OFF) || \650 (c == HPC_SLOT_ON) || \651 (c == HPC_CTLR_RESET) || \652 (c == HPC_BUS_33CONVMODE) || \653 (c == HPC_BUS_66CONVMODE) || \654 (c == HPC_BUS_66PCIXMODE) || \655 (c == HPC_BUS_100PCIXMODE) || \656 (c == HPC_BUS_133PCIXMODE) || \657 (c == HPC_ALLSLOT_OFF) || \658 (c == HPC_ALLSLOT_ON))659 660 661/* Core part of the driver */662 663#define ENABLE 1664#define DISABLE 0665 666#define CARD_INFO 0x07667#define PCIX133 0x07668#define PCIX66 0x05669#define PCI66 0x04670 671extern struct pci_bus *ibmphp_pci_bus;672 673/* Variables */674 675struct pci_func {676 struct pci_dev *dev; /* from the OS */677 u8 busno;678 u8 device;679 u8 function;680 struct resource_node *io[6];681 struct resource_node *mem[6];682 struct resource_node *pfmem[6];683 struct pci_func *next;684 int devices[32]; /* for bridge config */685 u8 irq[4]; /* for interrupt config */686 u8 bus; /* flag for unconfiguring, to say if PPB */687};688 689struct slot {690 u8 bus;691 u8 device;692 u8 number;693 u8 real_physical_slot_num;694 u32 capabilities;695 u8 supported_speed;696 u8 supported_bus_mode;697 u8 flag; /* this is for disable slot and polling */698 u8 ctlr_index;699 struct hotplug_slot hotplug_slot;700 struct controller *ctrl;701 struct pci_func *func;702 u8 irq[4];703 int bit_mode; /* 0 = 32, 1 = 64 */704 struct bus_info *bus_on;705 struct list_head ibm_slot_list;706 u8 status;707 u8 ext_status;708 u8 busstatus;709};710 711struct controller {712 struct ebda_hpc_slot *slots;713 struct ebda_hpc_bus *buses;714 struct pci_dev *ctrl_dev; /* in case where controller is PCI */715 u8 starting_slot_num; /* starting and ending slot #'s this ctrl controls*/716 u8 ending_slot_num;717 u8 revision;718 u8 options; /* which options HPC supports */719 u8 status;720 u8 ctlr_id;721 u8 slot_count;722 u8 bus_count;723 u8 ctlr_relative_id;724 u32 irq;725 union {726 struct isa_ctlr_access isa_ctlr;727 struct pci_ctlr_access pci_ctlr;728 struct wpeg_i2c_ctlr_access wpeg_ctlr;729 } u;730 u8 ctlr_type;731 struct list_head ebda_hpc_list;732};733 734/* Functions */735 736int ibmphp_init_devno(struct slot **); /* This function is called from EBDA, so we need it not be static */737int ibmphp_do_disable_slot(struct slot *slot_cur);738int ibmphp_update_slot_info(struct slot *); /* This function is called from HPC, so we need it to not be static */739int ibmphp_configure_card(struct pci_func *, u8);740int ibmphp_unconfigure_card(struct slot **, int);741extern const struct hotplug_slot_ops ibmphp_hotplug_slot_ops;742 743static inline struct slot *to_slot(struct hotplug_slot *hotplug_slot)744{745 return container_of(hotplug_slot, struct slot, hotplug_slot);746}747 748#endif //__IBMPHP_H749 750