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1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * Standard Hot Plug Controller Driver4 *5 * Copyright (C) 1995,2001 Compaq Computer Corporation6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)7 * Copyright (C) 2001 IBM8 * Copyright (C) 2003-2004 Intel Corporation9 *10 * All rights reserved.11 *12 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>13 *14 */15#ifndef _SHPCHP_H16#define _SHPCHP_H17 18#include <linux/types.h>19#include <linux/pci.h>20#include <linux/pci_hotplug.h>21#include <linux/delay.h>22#include <linux/sched/signal.h> /* signal_pending(), struct timer_list */23#include <linux/mutex.h>24#include <linux/workqueue.h>25 26#if !defined(MODULE)27 #define MY_NAME "shpchp"28#else29 #define MY_NAME THIS_MODULE->name30#endif31 32extern bool shpchp_poll_mode;33extern int shpchp_poll_time;34extern bool shpchp_debug;35 36#define dbg(format, arg...) \37do { \38 if (shpchp_debug) \39 printk(KERN_DEBUG "%s: " format, MY_NAME, ## arg); \40} while (0)41#define err(format, arg...) \42 printk(KERN_ERR "%s: " format, MY_NAME, ## arg)43#define info(format, arg...) \44 printk(KERN_INFO "%s: " format, MY_NAME, ## arg)45#define warn(format, arg...) \46 printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)47 48#define ctrl_dbg(ctrl, format, arg...) \49 do { \50 if (shpchp_debug) \51 pci_printk(KERN_DEBUG, ctrl->pci_dev, \52 format, ## arg); \53 } while (0)54#define ctrl_err(ctrl, format, arg...) \55 pci_err(ctrl->pci_dev, format, ## arg)56#define ctrl_info(ctrl, format, arg...) \57 pci_info(ctrl->pci_dev, format, ## arg)58#define ctrl_warn(ctrl, format, arg...) \59 pci_warn(ctrl->pci_dev, format, ## arg)60 61 62#define SLOT_NAME_SIZE 1063struct slot {64 u8 bus;65 u8 device;66 u16 status;67 u32 number;68 u8 is_a_board;69 u8 state;70 u8 attention_save;71 u8 presence_save;72 u8 latch_save;73 u8 pwr_save;74 struct controller *ctrl;75 struct hotplug_slot hotplug_slot;76 struct list_head slot_list;77 struct delayed_work work; /* work for button event */78 struct mutex lock;79 struct workqueue_struct *wq;80 u8 hp_slot;81};82 83struct event_info {84 u32 event_type;85 struct slot *p_slot;86 struct work_struct work;87};88 89struct controller {90 struct mutex crit_sect; /* critical section mutex */91 struct mutex cmd_lock; /* command lock */92 int num_slots; /* Number of slots on ctlr */93 int slot_num_inc; /* 1 or -1 */94 struct pci_dev *pci_dev;95 struct list_head slot_list;96 wait_queue_head_t queue; /* sleep & wake process */97 u8 slot_device_offset;98 u32 pcix_misc2_reg; /* for amd pogo errata */99 u32 first_slot; /* First physical slot number */100 u32 cap_offset;101 unsigned long mmio_base;102 unsigned long mmio_size;103 void __iomem *creg;104 struct timer_list poll_timer;105};106 107/* Define AMD SHPC ID */108#define PCI_DEVICE_ID_AMD_POGO_7458 0x7458109 110/* AMD PCI-X bridge registers */111#define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C112#define PCIX_MISCII_OFFSET 0x48113#define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80114 115/* AMD PCIX_MISCII masks and offsets */116#define PERRNONFATALENABLE_MASK 0x00040000117#define PERRFATALENABLE_MASK 0x00080000118#define PERRFLOODENABLE_MASK 0x00100000119#define SERRNONFATALENABLE_MASK 0x00200000120#define SERRFATALENABLE_MASK 0x00400000121 122/* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */123#define PERR_OBSERVED_MASK 0x00000001124 125/* AMD PCIX_MEM_BASE_LIMIT masks */126#define RSE_MASK 0x40000000127 128#define INT_BUTTON_IGNORE 0129#define INT_PRESENCE_ON 1130#define INT_PRESENCE_OFF 2131#define INT_SWITCH_CLOSE 3132#define INT_SWITCH_OPEN 4133#define INT_POWER_FAULT 5134#define INT_POWER_FAULT_CLEAR 6135#define INT_BUTTON_PRESS 7136#define INT_BUTTON_RELEASE 8137#define INT_BUTTON_CANCEL 9138 139#define STATIC_STATE 0140#define BLINKINGON_STATE 1141#define BLINKINGOFF_STATE 2142#define POWERON_STATE 3143#define POWEROFF_STATE 4144 145/* Error messages */146#define INTERLOCK_OPEN 0x00000002147#define ADD_NOT_SUPPORTED 0x00000003148#define CARD_FUNCTIONING 0x00000005149#define ADAPTER_NOT_SAME 0x00000006150#define NO_ADAPTER_PRESENT 0x00000009151#define NOT_ENOUGH_RESOURCES 0x0000000B152#define DEVICE_TYPE_NOT_SUPPORTED 0x0000000C153#define WRONG_BUS_FREQUENCY 0x0000000D154#define POWER_FAILURE 0x0000000E155 156int __must_check shpchp_create_ctrl_files(struct controller *ctrl);157void shpchp_remove_ctrl_files(struct controller *ctrl);158int shpchp_sysfs_enable_slot(struct slot *slot);159int shpchp_sysfs_disable_slot(struct slot *slot);160u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);161u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);162u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);163u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);164int shpchp_configure_device(struct slot *p_slot);165void shpchp_unconfigure_device(struct slot *p_slot);166void cleanup_slots(struct controller *ctrl);167void shpchp_queue_pushbutton_work(struct work_struct *work);168int shpc_init(struct controller *ctrl, struct pci_dev *pdev);169 170static inline const char *slot_name(struct slot *slot)171{172 return hotplug_slot_name(&slot->hotplug_slot);173}174 175struct ctrl_reg {176 volatile u32 base_offset;177 volatile u32 slot_avail1;178 volatile u32 slot_avail2;179 volatile u32 slot_config;180 volatile u16 sec_bus_config;181 volatile u8 msi_ctrl;182 volatile u8 prog_interface;183 volatile u16 cmd;184 volatile u16 cmd_status;185 volatile u32 intr_loc;186 volatile u32 serr_loc;187 volatile u32 serr_intr_enable;188 volatile u32 slot1;189} __attribute__ ((packed));190 191/* offsets to the controller registers based on the above structure layout */192enum ctrl_offsets {193 BASE_OFFSET = offsetof(struct ctrl_reg, base_offset),194 SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),195 SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),196 SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),197 SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),198 MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),199 PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),200 CMD = offsetof(struct ctrl_reg, cmd),201 CMD_STATUS = offsetof(struct ctrl_reg, cmd_status),202 INTR_LOC = offsetof(struct ctrl_reg, intr_loc),203 SERR_LOC = offsetof(struct ctrl_reg, serr_loc),204 SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable),205 SLOT1 = offsetof(struct ctrl_reg, slot1),206};207 208static inline struct slot *get_slot(struct hotplug_slot *hotplug_slot)209{210 return container_of(hotplug_slot, struct slot, hotplug_slot);211}212 213static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device)214{215 struct slot *slot;216 217 list_for_each_entry(slot, &ctrl->slot_list, slot_list) {218 if (slot->device == device)219 return slot;220 }221 222 ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device);223 return NULL;224}225 226static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)227{228 u32 pcix_misc2_temp;229 230 /* save MiscII register */231 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);232 233 p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;234 235 /* clear SERR/PERR enable bits */236 pcix_misc2_temp &= ~SERRFATALENABLE_MASK;237 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;238 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;239 pcix_misc2_temp &= ~PERRFATALENABLE_MASK;240 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;241 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);242}243 244static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)245{246 u32 pcix_misc2_temp;247 u32 pcix_bridge_errors_reg;248 u32 pcix_mem_base_reg;249 u8 perr_set;250 u8 rse_set;251 252 /* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */253 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);254 perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;255 if (perr_set) {256 ctrl_dbg(p_slot->ctrl,257 "Bridge_Errors[ PERR_OBSERVED = %08X] (W1C)\n",258 perr_set);259 260 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);261 }262 263 /* write-one-to-clear Memory_Base_Limit[ RSE ] */264 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);265 rse_set = pcix_mem_base_reg & RSE_MASK;266 if (rse_set) {267 ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");268 269 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);270 }271 /* restore MiscII register */272 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);273 274 if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)275 pcix_misc2_temp |= SERRFATALENABLE_MASK;276 else277 pcix_misc2_temp &= ~SERRFATALENABLE_MASK;278 279 if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)280 pcix_misc2_temp |= SERRNONFATALENABLE_MASK;281 else282 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;283 284 if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)285 pcix_misc2_temp |= PERRFLOODENABLE_MASK;286 else287 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;288 289 if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)290 pcix_misc2_temp |= PERRFATALENABLE_MASK;291 else292 pcix_misc2_temp &= ~PERRFATALENABLE_MASK;293 294 if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)295 pcix_misc2_temp |= PERRNONFATALENABLE_MASK;296 else297 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;298 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);299}300 301int shpchp_power_on_slot(struct slot *slot);302int shpchp_slot_enable(struct slot *slot);303int shpchp_slot_disable(struct slot *slot);304int shpchp_set_bus_speed_mode(struct slot *slot, enum pci_bus_speed speed);305int shpchp_get_power_status(struct slot *slot, u8 *status);306int shpchp_get_attention_status(struct slot *slot, u8 *status);307int shpchp_set_attention_status(struct slot *slot, u8 status);308int shpchp_get_latch_status(struct slot *slot, u8 *status);309int shpchp_get_adapter_status(struct slot *slot, u8 *status);310int shpchp_get_adapter_speed(struct slot *slot, enum pci_bus_speed *speed);311int shpchp_get_prog_int(struct slot *slot, u8 *prog_int);312int shpchp_query_power_fault(struct slot *slot);313void shpchp_green_led_on(struct slot *slot);314void shpchp_green_led_off(struct slot *slot);315void shpchp_green_led_blink(struct slot *slot);316void shpchp_release_ctlr(struct controller *ctrl);317int shpchp_check_cmd_status(struct controller *ctrl);318 319#endif /* _SHPCHP_H */320