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1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef __PCI_BRIDGE_EMUL_H__3#define __PCI_BRIDGE_EMUL_H__4 5#include <linux/kernel.h>6 7/* PCI configuration space of a PCI-to-PCI bridge. */8struct pci_bridge_emul_conf {9 __le16 vendor;10 __le16 device;11 __le16 command;12 __le16 status;13 __le32 class_revision;14 u8 cache_line_size;15 u8 latency_timer;16 u8 header_type;17 u8 bist;18 __le32 bar[2];19 u8 primary_bus;20 u8 secondary_bus;21 u8 subordinate_bus;22 u8 secondary_latency_timer;23 u8 iobase;24 u8 iolimit;25 __le16 secondary_status;26 __le16 membase;27 __le16 memlimit;28 __le16 pref_mem_base;29 __le16 pref_mem_limit;30 __le32 prefbaseupper;31 __le32 preflimitupper;32 __le16 iobaseupper;33 __le16 iolimitupper;34 u8 capabilities_pointer;35 u8 reserve[3];36 __le32 romaddr;37 u8 intline;38 u8 intpin;39 __le16 bridgectrl;40};41 42/* PCI configuration space of the PCIe capabilities */43struct pci_bridge_emul_pcie_conf {44 u8 cap_id;45 u8 next;46 __le16 cap;47 __le32 devcap;48 __le16 devctl;49 __le16 devsta;50 __le32 lnkcap;51 __le16 lnkctl;52 __le16 lnksta;53 __le32 slotcap;54 __le16 slotctl;55 __le16 slotsta;56 __le16 rootctl;57 __le16 rootcap;58 __le32 rootsta;59 __le32 devcap2;60 __le16 devctl2;61 __le16 devsta2;62 __le32 lnkcap2;63 __le16 lnkctl2;64 __le16 lnksta2;65 __le32 slotcap2;66 __le16 slotctl2;67 __le16 slotsta2;68};69 70struct pci_bridge_emul;71 72typedef enum { PCI_BRIDGE_EMUL_HANDLED,73 PCI_BRIDGE_EMUL_NOT_HANDLED } pci_bridge_emul_read_status_t;74 75struct pci_bridge_emul_ops {76 /*77 * Called when reading from the regular PCI bridge78 * configuration space. Return PCI_BRIDGE_EMUL_HANDLED when the79 * operation has handled the read operation and filled in the80 * *value, or PCI_BRIDGE_EMUL_NOT_HANDLED when the read should81 * be emulated by the common code by reading from the82 * in-memory copy of the configuration space.83 */84 pci_bridge_emul_read_status_t (*read_base)(struct pci_bridge_emul *bridge,85 int reg, u32 *value);86 87 /*88 * Same as ->read_base(), except it is for reading from the89 * PCIe capability configuration space.90 */91 pci_bridge_emul_read_status_t (*read_pcie)(struct pci_bridge_emul *bridge,92 int reg, u32 *value);93 94 /*95 * Same as ->read_base(), except it is for reading from the96 * PCIe extended capability configuration space.97 */98 pci_bridge_emul_read_status_t (*read_ext)(struct pci_bridge_emul *bridge,99 int reg, u32 *value);100 101 /*102 * Called when writing to the regular PCI bridge configuration103 * space. old is the current value, new is the new value being104 * written, and mask indicates which parts of the value are105 * being changed.106 */107 void (*write_base)(struct pci_bridge_emul *bridge, int reg,108 u32 old, u32 new, u32 mask);109 110 /*111 * Same as ->write_base(), except it is for writing from the112 * PCIe capability configuration space.113 */114 void (*write_pcie)(struct pci_bridge_emul *bridge, int reg,115 u32 old, u32 new, u32 mask);116 117 /*118 * Same as ->write_base(), except it is for writing from the119 * PCIe extended capability configuration space.120 */121 void (*write_ext)(struct pci_bridge_emul *bridge, int reg,122 u32 old, u32 new, u32 mask);123};124 125struct pci_bridge_reg_behavior;126 127struct pci_bridge_emul {128 struct pci_bridge_emul_conf conf;129 struct pci_bridge_emul_pcie_conf pcie_conf;130 const struct pci_bridge_emul_ops *ops;131 struct pci_bridge_reg_behavior *pci_regs_behavior;132 struct pci_bridge_reg_behavior *pcie_cap_regs_behavior;133 void *data;134 u8 pcie_start;135 u8 ssid_start;136 bool has_pcie;137 u16 subsystem_vendor_id;138 u16 subsystem_id;139};140 141enum {142 /*143 * PCI bridge does not support forwarding of prefetchable memory144 * requests between primary and secondary buses.145 */146 PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD = BIT(0),147 148 /*149 * PCI bridge does not support forwarding of IO requests between150 * primary and secondary buses.151 */152 PCI_BRIDGE_EMUL_NO_IO_FORWARD = BIT(1),153};154 155int pci_bridge_emul_init(struct pci_bridge_emul *bridge,156 unsigned int flags);157void pci_bridge_emul_cleanup(struct pci_bridge_emul *bridge);158 159int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,160 int size, u32 *value);161int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,162 int size, u32 value);163 164#endif /* __PCI_BRIDGE_EMUL_H__ */165