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1/* SPDX-License-Identifier: GPL-2.0 */2#ifndef DRIVERS_PCI_H3#define DRIVERS_PCI_H4 5#include <linux/pci.h>6 7/* Number of possible devfns: 0.0 to 1f.7 inclusive */8#define MAX_NR_DEVFNS 2569 10#define PCI_FIND_CAP_TTL 4811 12#define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */13 14#define PCIE_LINK_RETRAIN_TIMEOUT_MS 100015 16/*17 * Power stable to PERST# inactive.18 *19 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express20 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol21 * "T_PVPERL".22 */23#define PCIE_T_PVPERL_MS 10024 25/*26 * REFCLK stable before PERST# inactive.27 *28 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express29 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol30 * "T_PERST-CLK".31 */32#define PCIE_T_PERST_CLK_US 10033 34/*35 * End of conventional reset (PERST# de-asserted) to first configuration36 * request (device able to respond with a "Request Retry Status" completion),37 * from PCIe r6.0, sec 6.6.1.38 */39#define PCIE_T_RRS_READY_MS 10040 41/*42 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>43 * Recommends 1ms to 10ms timeout to check L2 ready.44 */45#define PCIE_PME_TO_L2_TIMEOUT_US 1000046 47/*48 * PCIe r6.0, sec 6.6.1 <Conventional Reset>49 *50 * - "With a Downstream Port that does not support Link speeds greater51 * than 5.0 GT/s, software must wait a minimum of 100 ms following exit52 * from a Conventional Reset before sending a Configuration Request to53 * the device immediately below that Port."54 *55 * - "With a Downstream Port that supports Link speeds greater than56 * 5.0 GT/s, software must wait a minimum of 100 ms after Link training57 * completes before sending a Configuration Request to the device58 * immediately below that Port."59 */60#define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 10061 62/* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */63#define PCIE_MSG_TYPE_R_RC 064#define PCIE_MSG_TYPE_R_ADDR 165#define PCIE_MSG_TYPE_R_ID 266#define PCIE_MSG_TYPE_R_BC 367#define PCIE_MSG_TYPE_R_LOCAL 468#define PCIE_MSG_TYPE_R_GATHER 569 70/* Power Management Messages; PCIe r6.0, sec 2.2.8.2 */71#define PCIE_MSG_CODE_PME_TURN_OFF 0x1972 73/* INTx Mechanism Messages; PCIe r6.0, sec 2.2.8.1 */74#define PCIE_MSG_CODE_ASSERT_INTA 0x2075#define PCIE_MSG_CODE_ASSERT_INTB 0x2176#define PCIE_MSG_CODE_ASSERT_INTC 0x2277#define PCIE_MSG_CODE_ASSERT_INTD 0x2378#define PCIE_MSG_CODE_DEASSERT_INTA 0x2479#define PCIE_MSG_CODE_DEASSERT_INTB 0x2580#define PCIE_MSG_CODE_DEASSERT_INTC 0x2681#define PCIE_MSG_CODE_DEASSERT_INTD 0x2782 83extern const unsigned char pcie_link_speed[];84extern bool pci_early_dump;85 86bool pcie_cap_has_lnkctl(const struct pci_dev *dev);87bool pcie_cap_has_lnkctl2(const struct pci_dev *dev);88bool pcie_cap_has_rtctl(const struct pci_dev *dev);89 90/* Functions internal to the PCI core code */91 92#ifdef CONFIG_DMI93extern const struct attribute_group pci_dev_smbios_attr_group;94#endif95 96enum pci_mmap_api {97 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */98 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */99};100int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,101 enum pci_mmap_api mmap_api);102 103bool pci_reset_supported(struct pci_dev *dev);104void pci_init_reset_methods(struct pci_dev *dev);105int pci_bridge_secondary_bus_reset(struct pci_dev *dev);106int pci_bus_error_reset(struct pci_dev *dev);107 108struct pci_cap_saved_data {109 u16 cap_nr;110 bool cap_extended;111 unsigned int size;112 u32 data[];113};114 115struct pci_cap_saved_state {116 struct hlist_node next;117 struct pci_cap_saved_data cap;118};119 120void pci_allocate_cap_save_buffers(struct pci_dev *dev);121void pci_free_cap_save_buffers(struct pci_dev *dev);122int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);123int pci_add_ext_cap_save_buffer(struct pci_dev *dev,124 u16 cap, unsigned int size);125struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);126struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,127 u16 cap);128 129#define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */130#define PCI_PM_D3HOT_WAIT 10 /* msec */131#define PCI_PM_D3COLD_WAIT 100 /* msec */132 133void pci_update_current_state(struct pci_dev *dev, pci_power_t state);134void pci_refresh_power_state(struct pci_dev *dev);135int pci_power_up(struct pci_dev *dev);136void pci_disable_enabled_device(struct pci_dev *dev);137int pci_finish_runtime_suspend(struct pci_dev *dev);138void pcie_clear_device_status(struct pci_dev *dev);139void pcie_clear_root_pme_status(struct pci_dev *dev);140bool pci_check_pme_status(struct pci_dev *dev);141void pci_pme_wakeup_bus(struct pci_bus *bus);142void pci_pme_restore(struct pci_dev *dev);143bool pci_dev_need_resume(struct pci_dev *dev);144void pci_dev_adjust_pme(struct pci_dev *dev);145void pci_dev_complete_resume(struct pci_dev *pci_dev);146void pci_config_pm_runtime_get(struct pci_dev *dev);147void pci_config_pm_runtime_put(struct pci_dev *dev);148void pci_pm_init(struct pci_dev *dev);149void pci_ea_init(struct pci_dev *dev);150void pci_msi_init(struct pci_dev *dev);151void pci_msix_init(struct pci_dev *dev);152bool pci_bridge_d3_possible(struct pci_dev *dev);153void pci_bridge_d3_update(struct pci_dev *dev);154int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type);155 156static inline bool pci_bus_rrs_vendor_id(u32 l)157{158 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG;159}160 161static inline void pci_wakeup_event(struct pci_dev *dev)162{163 /* Wait 100 ms before the system can be put into a sleep state. */164 pm_wakeup_event(&dev->dev, 100);165}166 167static inline bool pci_has_subordinate(struct pci_dev *pci_dev)168{169 return !!(pci_dev->subordinate);170}171 172static inline bool pci_power_manageable(struct pci_dev *pci_dev)173{174 /*175 * Currently we allow normal PCI devices and PCI bridges transition176 * into D3 if their bridge_d3 is set.177 */178 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;179}180 181static inline bool pcie_downstream_port(const struct pci_dev *dev)182{183 int type = pci_pcie_type(dev);184 185 return type == PCI_EXP_TYPE_ROOT_PORT ||186 type == PCI_EXP_TYPE_DOWNSTREAM ||187 type == PCI_EXP_TYPE_PCIE_BRIDGE;188}189 190void pci_vpd_init(struct pci_dev *dev);191extern const struct attribute_group pci_dev_vpd_attr_group;192 193/* PCI Virtual Channel */194int pci_save_vc_state(struct pci_dev *dev);195void pci_restore_vc_state(struct pci_dev *dev);196void pci_allocate_vc_save_buffers(struct pci_dev *dev);197 198/* PCI /proc functions */199#ifdef CONFIG_PROC_FS200int pci_proc_attach_device(struct pci_dev *dev);201int pci_proc_detach_device(struct pci_dev *dev);202int pci_proc_detach_bus(struct pci_bus *bus);203#else204static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }205static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }206static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }207#endif208 209/* Functions for PCI Hotplug drivers to use */210int pci_hp_add_bridge(struct pci_dev *dev);211 212#if defined(CONFIG_SYSFS) && defined(HAVE_PCI_LEGACY)213void pci_create_legacy_files(struct pci_bus *bus);214void pci_remove_legacy_files(struct pci_bus *bus);215#else216static inline void pci_create_legacy_files(struct pci_bus *bus) { }217static inline void pci_remove_legacy_files(struct pci_bus *bus) { }218#endif219 220/* Lock for read/write access to pci device and bus lists */221extern struct rw_semaphore pci_bus_sem;222extern struct mutex pci_slot_mutex;223 224extern raw_spinlock_t pci_lock;225 226extern unsigned int pci_pm_d3hot_delay;227 228#ifdef CONFIG_PCI_MSI229void pci_no_msi(void);230#else231static inline void pci_no_msi(void) { }232#endif233 234void pci_realloc_get_opt(char *);235 236static inline int pci_no_d1d2(struct pci_dev *dev)237{238 unsigned int parent_dstates = 0;239 240 if (dev->bus->self)241 parent_dstates = dev->bus->self->no_d1d2;242 return (dev->no_d1d2 || parent_dstates);243 244}245 246#ifdef CONFIG_SYSFS247int pci_create_sysfs_dev_files(struct pci_dev *pdev);248void pci_remove_sysfs_dev_files(struct pci_dev *pdev);249extern const struct attribute_group *pci_dev_groups[];250extern const struct attribute_group *pci_dev_attr_groups[];251extern const struct attribute_group *pcibus_groups[];252extern const struct attribute_group *pci_bus_groups[];253#else254static inline int pci_create_sysfs_dev_files(struct pci_dev *pdev) { return 0; }255static inline void pci_remove_sysfs_dev_files(struct pci_dev *pdev) { }256#define pci_dev_groups NULL257#define pci_dev_attr_groups NULL258#define pcibus_groups NULL259#define pci_bus_groups NULL260#endif261 262extern unsigned long pci_hotplug_io_size;263extern unsigned long pci_hotplug_mmio_size;264extern unsigned long pci_hotplug_mmio_pref_size;265extern unsigned long pci_hotplug_bus_size;266 267/**268 * pci_match_one_device - Tell if a PCI device structure has a matching269 * PCI device id structure270 * @id: single PCI device id structure to match271 * @dev: the PCI device structure to match against272 *273 * Returns the matching pci_device_id structure or %NULL if there is no match.274 */275static inline const struct pci_device_id *276pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)277{278 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&279 (id->device == PCI_ANY_ID || id->device == dev->device) &&280 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&281 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&282 !((id->class ^ dev->class) & id->class_mask))283 return id;284 return NULL;285}286 287/* PCI slot sysfs helper code */288#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)289 290extern struct kset *pci_slots_kset;291 292struct pci_slot_attribute {293 struct attribute attr;294 ssize_t (*show)(struct pci_slot *, char *);295 ssize_t (*store)(struct pci_slot *, const char *, size_t);296};297#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)298 299enum pci_bar_type {300 pci_bar_unknown, /* Standard PCI BAR probe */301 pci_bar_io, /* An I/O port BAR */302 pci_bar_mem32, /* A 32-bit memory BAR */303 pci_bar_mem64, /* A 64-bit memory BAR */304};305 306struct device *pci_get_host_bridge_device(struct pci_dev *dev);307void pci_put_host_bridge_device(struct device *dev);308 309int pci_configure_extended_tags(struct pci_dev *dev, void *ign);310bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,311 int rrs_timeout);312bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,313 int rrs_timeout);314int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int rrs_timeout);315 316int pci_setup_device(struct pci_dev *dev);317int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,318 struct resource *res, unsigned int reg);319void pci_configure_ari(struct pci_dev *dev);320void __pci_bus_size_bridges(struct pci_bus *bus,321 struct list_head *realloc_head);322void __pci_bus_assign_resources(const struct pci_bus *bus,323 struct list_head *realloc_head,324 struct list_head *fail_head);325bool pci_bus_clip_resource(struct pci_dev *dev, int idx);326 327const char *pci_resource_name(struct pci_dev *dev, unsigned int i);328 329void pci_reassigndev_resource_alignment(struct pci_dev *dev);330void pci_disable_bridge_window(struct pci_dev *dev);331struct pci_bus *pci_bus_get(struct pci_bus *bus);332void pci_bus_put(struct pci_bus *bus);333 334/* PCIe link information from Link Capabilities 2 */335#define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \336 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \337 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \338 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \339 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \340 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \341 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \342 PCI_SPEED_UNKNOWN)343 344/* PCIe speed to Mb/s reduced by encoding overhead */345#define PCIE_SPEED2MBS_ENC(speed) \346 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \347 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \348 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \349 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \350 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \351 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \352 0)353 354static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed)355{356 switch (speed) {357 case PCIE_SPEED_2_5GT:358 return 2500;359 case PCIE_SPEED_5_0GT:360 return 5000;361 case PCIE_SPEED_8_0GT:362 return 8000;363 case PCIE_SPEED_16_0GT:364 return 16000;365 case PCIE_SPEED_32_0GT:366 return 32000;367 case PCIE_SPEED_64_0GT:368 return 64000;369 default:370 break;371 }372 373 return -EINVAL;374}375 376const char *pci_speed_string(enum pci_bus_speed speed);377enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);378enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);379void __pcie_print_link_status(struct pci_dev *dev, bool verbose);380void pcie_report_downtraining(struct pci_dev *dev);381void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);382 383/* Single Root I/O Virtualization */384struct pci_sriov {385 int pos; /* Capability position */386 int nres; /* Number of resources */387 u32 cap; /* SR-IOV Capabilities */388 u16 ctrl; /* SR-IOV Control */389 u16 total_VFs; /* Total VFs associated with the PF */390 u16 initial_VFs; /* Initial VFs associated with the PF */391 u16 num_VFs; /* Number of VFs available */392 u16 offset; /* First VF Routing ID offset */393 u16 stride; /* Following VF stride */394 u16 vf_device; /* VF device ID */395 u32 pgsz; /* Page size for BAR alignment */396 u8 link; /* Function Dependency Link */397 u8 max_VF_buses; /* Max buses consumed by VFs */398 u16 driver_max_VFs; /* Max num VFs driver supports */399 struct pci_dev *dev; /* Lowest numbered PF */400 struct pci_dev *self; /* This PF */401 u32 class; /* VF device */402 u8 hdr_type; /* VF header type */403 u16 subsystem_vendor; /* VF subsystem vendor */404 u16 subsystem_device; /* VF subsystem device */405 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */406 bool drivers_autoprobe; /* Auto probing of VFs by driver */407};408 409#ifdef CONFIG_PCI_DOE410void pci_doe_init(struct pci_dev *pdev);411void pci_doe_destroy(struct pci_dev *pdev);412void pci_doe_disconnected(struct pci_dev *pdev);413#else414static inline void pci_doe_init(struct pci_dev *pdev) { }415static inline void pci_doe_destroy(struct pci_dev *pdev) { }416static inline void pci_doe_disconnected(struct pci_dev *pdev) { }417#endif418 419#ifdef CONFIG_PCI_NPEM420void pci_npem_create(struct pci_dev *dev);421void pci_npem_remove(struct pci_dev *dev);422#else423static inline void pci_npem_create(struct pci_dev *dev) { }424static inline void pci_npem_remove(struct pci_dev *dev) { }425#endif426 427/**428 * pci_dev_set_io_state - Set the new error state if possible.429 *430 * @dev: PCI device to set new error_state431 * @new: the state we want dev to be in432 *433 * If the device is experiencing perm_failure, it has to remain in that state.434 * Any other transition is allowed.435 *436 * Returns true if state has been changed to the requested state.437 */438static inline bool pci_dev_set_io_state(struct pci_dev *dev,439 pci_channel_state_t new)440{441 pci_channel_state_t old;442 443 switch (new) {444 case pci_channel_io_perm_failure:445 xchg(&dev->error_state, pci_channel_io_perm_failure);446 return true;447 case pci_channel_io_frozen:448 old = cmpxchg(&dev->error_state, pci_channel_io_normal,449 pci_channel_io_frozen);450 return old != pci_channel_io_perm_failure;451 case pci_channel_io_normal:452 old = cmpxchg(&dev->error_state, pci_channel_io_frozen,453 pci_channel_io_normal);454 return old != pci_channel_io_perm_failure;455 default:456 return false;457 }458}459 460static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)461{462 pci_dev_set_io_state(dev, pci_channel_io_perm_failure);463 pci_doe_disconnected(dev);464 465 return 0;466}467 468/* pci_dev priv_flags */469#define PCI_DEV_ADDED 0470#define PCI_DPC_RECOVERED 1471#define PCI_DPC_RECOVERING 2472 473static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)474{475 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);476}477 478static inline bool pci_dev_is_added(const struct pci_dev *dev)479{480 return test_bit(PCI_DEV_ADDED, &dev->priv_flags);481}482 483#ifdef CONFIG_PCIEAER484#include <linux/aer.h>485 486#define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */487 488struct aer_err_info {489 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];490 int error_dev_num;491 492 unsigned int id:16;493 494 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */495 unsigned int __pad1:5;496 unsigned int multi_error_valid:1;497 498 unsigned int first_error:5;499 unsigned int __pad2:2;500 unsigned int tlp_header_valid:1;501 502 unsigned int status; /* COR/UNCOR Error Status */503 unsigned int mask; /* COR/UNCOR Error Mask */504 struct pcie_tlp_log tlp; /* TLP Header */505};506 507int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);508void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);509#endif /* CONFIG_PCIEAER */510 511#ifdef CONFIG_PCIEPORTBUS512/* Cached RCEC Endpoint Association */513struct rcec_ea {514 u8 nextbusn;515 u8 lastbusn;516 u32 bitmap;517};518#endif519 520#ifdef CONFIG_PCIE_DPC521void pci_save_dpc_state(struct pci_dev *dev);522void pci_restore_dpc_state(struct pci_dev *dev);523void pci_dpc_init(struct pci_dev *pdev);524void dpc_process_error(struct pci_dev *pdev);525pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);526bool pci_dpc_recovered(struct pci_dev *pdev);527#else528static inline void pci_save_dpc_state(struct pci_dev *dev) { }529static inline void pci_restore_dpc_state(struct pci_dev *dev) { }530static inline void pci_dpc_init(struct pci_dev *pdev) { }531static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }532#endif533 534#ifdef CONFIG_PCIEPORTBUS535void pci_rcec_init(struct pci_dev *dev);536void pci_rcec_exit(struct pci_dev *dev);537void pcie_link_rcec(struct pci_dev *rcec);538void pcie_walk_rcec(struct pci_dev *rcec,539 int (*cb)(struct pci_dev *, void *),540 void *userdata);541#else542static inline void pci_rcec_init(struct pci_dev *dev) { }543static inline void pci_rcec_exit(struct pci_dev *dev) { }544static inline void pcie_link_rcec(struct pci_dev *rcec) { }545static inline void pcie_walk_rcec(struct pci_dev *rcec,546 int (*cb)(struct pci_dev *, void *),547 void *userdata) { }548#endif549 550#ifdef CONFIG_PCI_ATS551/* Address Translation Service */552void pci_ats_init(struct pci_dev *dev);553void pci_restore_ats_state(struct pci_dev *dev);554#else555static inline void pci_ats_init(struct pci_dev *d) { }556static inline void pci_restore_ats_state(struct pci_dev *dev) { }557#endif /* CONFIG_PCI_ATS */558 559#ifdef CONFIG_PCI_PRI560void pci_pri_init(struct pci_dev *dev);561void pci_restore_pri_state(struct pci_dev *pdev);562#else563static inline void pci_pri_init(struct pci_dev *dev) { }564static inline void pci_restore_pri_state(struct pci_dev *pdev) { }565#endif566 567#ifdef CONFIG_PCI_PASID568void pci_pasid_init(struct pci_dev *dev);569void pci_restore_pasid_state(struct pci_dev *pdev);570#else571static inline void pci_pasid_init(struct pci_dev *dev) { }572static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }573#endif574 575#ifdef CONFIG_PCI_IOV576int pci_iov_init(struct pci_dev *dev);577void pci_iov_release(struct pci_dev *dev);578void pci_iov_remove(struct pci_dev *dev);579void pci_iov_update_resource(struct pci_dev *dev, int resno);580resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);581void pci_restore_iov_state(struct pci_dev *dev);582int pci_iov_bus_range(struct pci_bus *bus);583extern const struct attribute_group sriov_pf_dev_attr_group;584extern const struct attribute_group sriov_vf_dev_attr_group;585#else586static inline int pci_iov_init(struct pci_dev *dev)587{588 return -ENODEV;589}590static inline void pci_iov_release(struct pci_dev *dev) { }591static inline void pci_iov_remove(struct pci_dev *dev) { }592static inline void pci_restore_iov_state(struct pci_dev *dev) { }593static inline int pci_iov_bus_range(struct pci_bus *bus)594{595 return 0;596}597 598#endif /* CONFIG_PCI_IOV */599 600#ifdef CONFIG_PCIE_PTM601void pci_ptm_init(struct pci_dev *dev);602void pci_save_ptm_state(struct pci_dev *dev);603void pci_restore_ptm_state(struct pci_dev *dev);604void pci_suspend_ptm(struct pci_dev *dev);605void pci_resume_ptm(struct pci_dev *dev);606#else607static inline void pci_ptm_init(struct pci_dev *dev) { }608static inline void pci_save_ptm_state(struct pci_dev *dev) { }609static inline void pci_restore_ptm_state(struct pci_dev *dev) { }610static inline void pci_suspend_ptm(struct pci_dev *dev) { }611static inline void pci_resume_ptm(struct pci_dev *dev) { }612#endif613 614unsigned long pci_cardbus_resource_alignment(struct resource *);615 616static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,617 struct resource *res)618{619#ifdef CONFIG_PCI_IOV620 int resno = res - dev->resource;621 622 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)623 return pci_sriov_resource_alignment(dev, resno);624#endif625 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)626 return pci_cardbus_resource_alignment(res);627 return resource_alignment(res);628}629 630void pci_acs_init(struct pci_dev *dev);631#ifdef CONFIG_PCI_QUIRKS632int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);633int pci_dev_specific_enable_acs(struct pci_dev *dev);634int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);635int pcie_failed_link_retrain(struct pci_dev *dev);636#else637static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,638 u16 acs_flags)639{640 return -ENOTTY;641}642static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)643{644 return -ENOTTY;645}646static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)647{648 return -ENOTTY;649}650static inline int pcie_failed_link_retrain(struct pci_dev *dev)651{652 return -ENOTTY;653}654#endif655 656/* PCI error reporting and recovery */657pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,658 pci_channel_state_t state,659 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));660 661bool pcie_wait_for_link(struct pci_dev *pdev, bool active);662int pcie_retrain_link(struct pci_dev *pdev, bool use_lt);663 664/* ASPM-related functionality we need even without CONFIG_PCIEASPM */665void pci_save_ltr_state(struct pci_dev *dev);666void pci_restore_ltr_state(struct pci_dev *dev);667void pci_configure_aspm_l1ss(struct pci_dev *dev);668void pci_save_aspm_l1ss_state(struct pci_dev *dev);669void pci_restore_aspm_l1ss_state(struct pci_dev *dev);670 671#ifdef CONFIG_PCIEASPM672void pcie_aspm_init_link_state(struct pci_dev *pdev);673void pcie_aspm_exit_link_state(struct pci_dev *pdev);674void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked);675void pcie_aspm_powersave_config_link(struct pci_dev *pdev);676void pci_configure_ltr(struct pci_dev *pdev);677void pci_bridge_reconfigure_ltr(struct pci_dev *pdev);678#else679static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }680static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }681static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { }682static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }683static inline void pci_configure_ltr(struct pci_dev *pdev) { }684static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { }685#endif686 687#ifdef CONFIG_PCIE_ECRC688void pcie_set_ecrc_checking(struct pci_dev *dev);689void pcie_ecrc_get_policy(char *str);690#else691static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }692static inline void pcie_ecrc_get_policy(char *str) { }693#endif694 695struct pci_dev_reset_methods {696 u16 vendor;697 u16 device;698 int (*reset)(struct pci_dev *dev, bool probe);699};700 701struct pci_reset_fn_method {702 int (*reset_fn)(struct pci_dev *pdev, bool probe);703 char *name;704};705 706#ifdef CONFIG_PCI_QUIRKS707int pci_dev_specific_reset(struct pci_dev *dev, bool probe);708#else709static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe)710{711 return -ENOTTY;712}713#endif714 715#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)716int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,717 struct resource *res);718#else719static inline int acpi_get_rc_resources(struct device *dev, const char *hid,720 u16 segment, struct resource *res)721{722 return -ENODEV;723}724#endif725 726int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);727int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);728static inline u64 pci_rebar_size_to_bytes(int size)729{730 return 1ULL << (size + 20);731}732 733struct device_node;734 735#ifdef CONFIG_OF736int of_pci_parse_bus_range(struct device_node *node, struct resource *res);737int of_get_pci_domain_nr(struct device_node *node);738int of_pci_get_max_link_speed(struct device_node *node);739u32 of_pci_get_slot_power_limit(struct device_node *node,740 u8 *slot_power_limit_value,741 u8 *slot_power_limit_scale);742bool of_pci_preserve_config(struct device_node *node);743int pci_set_of_node(struct pci_dev *dev);744void pci_release_of_node(struct pci_dev *dev);745void pci_set_bus_of_node(struct pci_bus *bus);746void pci_release_bus_of_node(struct pci_bus *bus);747 748int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);749 750#else751static inline int752of_pci_parse_bus_range(struct device_node *node, struct resource *res)753{754 return -EINVAL;755}756 757static inline int758of_get_pci_domain_nr(struct device_node *node)759{760 return -1;761}762 763static inline int764of_pci_get_max_link_speed(struct device_node *node)765{766 return -EINVAL;767}768 769static inline u32770of_pci_get_slot_power_limit(struct device_node *node,771 u8 *slot_power_limit_value,772 u8 *slot_power_limit_scale)773{774 if (slot_power_limit_value)775 *slot_power_limit_value = 0;776 if (slot_power_limit_scale)777 *slot_power_limit_scale = 0;778 return 0;779}780 781static inline bool of_pci_preserve_config(struct device_node *node)782{783 return false;784}785 786static inline int pci_set_of_node(struct pci_dev *dev) { return 0; }787static inline void pci_release_of_node(struct pci_dev *dev) { }788static inline void pci_set_bus_of_node(struct pci_bus *bus) { }789static inline void pci_release_bus_of_node(struct pci_bus *bus) { }790 791static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)792{793 return 0;794}795 796#endif /* CONFIG_OF */797 798struct of_changeset;799 800#ifdef CONFIG_PCI_DYNAMIC_OF_NODES801void of_pci_make_dev_node(struct pci_dev *pdev);802void of_pci_remove_node(struct pci_dev *pdev);803int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs,804 struct device_node *np);805#else806static inline void of_pci_make_dev_node(struct pci_dev *pdev) { }807static inline void of_pci_remove_node(struct pci_dev *pdev) { }808#endif809 810#ifdef CONFIG_PCIEAER811void pci_no_aer(void);812void pci_aer_init(struct pci_dev *dev);813void pci_aer_exit(struct pci_dev *dev);814extern const struct attribute_group aer_stats_attr_group;815void pci_aer_clear_fatal_status(struct pci_dev *dev);816int pci_aer_clear_status(struct pci_dev *dev);817int pci_aer_raw_clear_status(struct pci_dev *dev);818void pci_save_aer_state(struct pci_dev *dev);819void pci_restore_aer_state(struct pci_dev *dev);820#else821static inline void pci_no_aer(void) { }822static inline void pci_aer_init(struct pci_dev *d) { }823static inline void pci_aer_exit(struct pci_dev *d) { }824static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }825static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }826static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }827static inline void pci_save_aer_state(struct pci_dev *dev) { }828static inline void pci_restore_aer_state(struct pci_dev *dev) { }829#endif830 831#ifdef CONFIG_ACPI832bool pci_acpi_preserve_config(struct pci_host_bridge *bridge);833int pci_acpi_program_hp_params(struct pci_dev *dev);834extern const struct attribute_group pci_dev_acpi_attr_group;835void pci_set_acpi_fwnode(struct pci_dev *dev);836int pci_dev_acpi_reset(struct pci_dev *dev, bool probe);837bool acpi_pci_power_manageable(struct pci_dev *dev);838bool acpi_pci_bridge_d3(struct pci_dev *dev);839int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state);840pci_power_t acpi_pci_get_power_state(struct pci_dev *dev);841void acpi_pci_refresh_power_state(struct pci_dev *dev);842int acpi_pci_wakeup(struct pci_dev *dev, bool enable);843bool acpi_pci_need_resume(struct pci_dev *dev);844pci_power_t acpi_pci_choose_state(struct pci_dev *pdev);845#else846static inline bool pci_acpi_preserve_config(struct pci_host_bridge *bridge)847{848 return false;849}850static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)851{852 return -ENOTTY;853}854static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { }855static inline int pci_acpi_program_hp_params(struct pci_dev *dev)856{857 return -ENODEV;858}859static inline bool acpi_pci_power_manageable(struct pci_dev *dev)860{861 return false;862}863static inline bool acpi_pci_bridge_d3(struct pci_dev *dev)864{865 return false;866}867static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)868{869 return -ENODEV;870}871static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)872{873 return PCI_UNKNOWN;874}875static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { }876static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable)877{878 return -ENODEV;879}880static inline bool acpi_pci_need_resume(struct pci_dev *dev)881{882 return false;883}884static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)885{886 return PCI_POWER_ERROR;887}888#endif889 890#ifdef CONFIG_PCIEASPM891extern const struct attribute_group aspm_ctrl_attr_group;892#endif893 894extern const struct attribute_group pci_dev_reset_method_attr_group;895 896#ifdef CONFIG_X86_INTEL_MID897bool pci_use_mid_pm(void);898int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);899pci_power_t mid_pci_get_power_state(struct pci_dev *pdev);900#else901static inline bool pci_use_mid_pm(void)902{903 return false;904}905static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)906{907 return -ENODEV;908}909static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)910{911 return PCI_UNKNOWN;912}913#endif914 915int pcim_intx(struct pci_dev *dev, int enable);916int pcim_request_region_exclusive(struct pci_dev *pdev, int bar,917 const char *name);918void pcim_release_region(struct pci_dev *pdev, int bar);919 920/*921 * Config Address for PCI Configuration Mechanism #1922 *923 * See PCI Local Bus Specification, Revision 3.0,924 * Section 3.2.2.3.2, Figure 3-2, p. 50.925 */926 927#define PCI_CONF1_BUS_SHIFT 16 /* Bus number */928#define PCI_CONF1_DEV_SHIFT 11 /* Device number */929#define PCI_CONF1_FUNC_SHIFT 8 /* Function number */930 931#define PCI_CONF1_BUS_MASK 0xff932#define PCI_CONF1_DEV_MASK 0x1f933#define PCI_CONF1_FUNC_MASK 0x7934#define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */935 936#define PCI_CONF1_ENABLE BIT(31)937#define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT)938#define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT)939#define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT)940#define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK)941 942#define PCI_CONF1_ADDRESS(bus, dev, func, reg) \943 (PCI_CONF1_ENABLE | \944 PCI_CONF1_BUS(bus) | \945 PCI_CONF1_DEV(dev) | \946 PCI_CONF1_FUNC(func) | \947 PCI_CONF1_REG(reg))948 949/*950 * Extension of PCI Config Address for accessing extended PCIe registers951 *952 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs953 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address954 * are used for specifying additional 4 high bits of PCI Express register.955 */956 957#define PCI_CONF1_EXT_REG_SHIFT 16958#define PCI_CONF1_EXT_REG_MASK 0xf00959#define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT)960 961#define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \962 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \963 PCI_CONF1_EXT_REG(reg))964 965#endif /* DRIVERS_PCI_H */966