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1# SPDX-License-Identifier: GPL-2.02#3# PCI Express Port Bus Configuration4#5config PCIEPORTBUS6 bool "PCI Express Port Bus support"7 default y if USB48 help9 This enables PCI Express Port Bus support. Users can then enable10 support for Native Hot-Plug, Advanced Error Reporting, Power11 Management Events, and Downstream Port Containment.12 13#14# Include service Kconfig here15#16config HOTPLUG_PCI_PCIE17 bool "PCI Express Hotplug driver"18 depends on HOTPLUG_PCI && PCIEPORTBUS19 default y if USB420 help21 Say Y here if you have a motherboard that supports PCIe native22 hotplug.23 24 Thunderbolt/USB4 PCIe tunneling depends on native PCIe hotplug.25 26 When in doubt, say N.27 28config PCIEAER29 bool "PCI Express Advanced Error Reporting support"30 depends on PCIEPORTBUS31 select RAS32 help33 This enables PCI Express Root Port Advanced Error Reporting34 (AER) driver support. Error reporting messages sent to Root35 Port will be handled by PCI Express AER driver.36 37config PCIEAER_INJECT38 tristate "PCI Express error injection support"39 depends on PCIEAER40 select GENERIC_IRQ_INJECTION41 help42 This enables PCI Express Root Port Advanced Error Reporting43 (AER) software error injector.44 45 Debugging AER code is quite difficult because it is hard46 to trigger various real hardware errors. Software-based47 error injection can fake almost all kinds of errors with the48 help of a user space helper tool aer-inject, which can be49 gotten from:50 https://github.com/intel/aer-inject.git51 52config PCIEAER_CXL53 bool "PCI Express CXL RAS support"54 default y55 depends on PCIEAER && CXL_PCI56 help57 Enables CXL error handling.58 59 If unsure, say Y.60 61#62# PCI Express ECRC63#64config PCIE_ECRC65 bool "PCI Express ECRC settings control"66 depends on PCIEAER67 help68 Used to override firmware/bios settings for PCI Express ECRC69 (transaction layer end-to-end CRC checking).70 71 When in doubt, say N.72 73#74# PCI Express ASPM75#76config PCIEASPM77 bool "PCI Express ASPM control" if EXPERT78 default y79 help80 This enables OS control over PCI Express ASPM (Active State81 Power Management) and Clock Power Management. ASPM supports82 state L0/L0s/L1.83 84 ASPM is initially set up by the firmware. With this option enabled,85 Linux can modify this state in order to disable ASPM on known-bad86 hardware or configurations and enable it when known-safe.87 88 ASPM can be disabled or enabled at runtime via89 /sys/module/pcie_aspm/parameters/policy90 91 When in doubt, say Y.92 93choice94 prompt "Default ASPM policy"95 default PCIEASPM_DEFAULT96 depends on PCIEASPM97 98config PCIEASPM_DEFAULT99 bool "BIOS default"100 depends on PCIEASPM101 help102 Use the BIOS defaults for PCI Express ASPM.103 104config PCIEASPM_POWERSAVE105 bool "Powersave"106 depends on PCIEASPM107 help108 Enable PCI Express ASPM L0s and L1 where possible, even if the109 BIOS did not.110 111config PCIEASPM_POWER_SUPERSAVE112 bool "Power Supersave"113 depends on PCIEASPM114 help115 Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where116 possible. This would result in higher power savings while staying in L1117 where the components support it.118 119config PCIEASPM_PERFORMANCE120 bool "Performance"121 depends on PCIEASPM122 help123 Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them.124endchoice125 126config PCIE_PME127 def_bool y128 depends on PCIEPORTBUS && PM129 130config PCIE_DPC131 bool "PCI Express Downstream Port Containment support"132 depends on PCIEPORTBUS && PCIEAER133 help134 This enables PCI Express Downstream Port Containment (DPC)135 driver support. DPC events from Root and Downstream ports136 will be handled by the DPC driver. If your system doesn't137 have this capability or you do not want to use this feature,138 it is safe to answer N.139 140config PCIE_PTM141 bool "PCI Express Precision Time Measurement support"142 help143 This enables PCI Express Precision Time Measurement (PTM)144 support.145 146 This is only useful if you have devices that support PTM, but it147 is safe to enable even if you don't.148 149config PCIE_EDR150 bool "PCI Express Error Disconnect Recover support"151 depends on PCIE_DPC && ACPI152 help153 This option adds Error Disconnect Recover support as specified154 in the Downstream Port Containment Related Enhancements ECN to155 the PCI Firmware Specification r3.2. Enable this if you want to156 support hybrid DPC model which uses both firmware and OS to157 implement DPC.158