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1// SPDX-License-Identifier: GPL-2.02/*3 * PCI detection and setup code4 */5 6#include <linux/kernel.h>7#include <linux/delay.h>8#include <linux/init.h>9#include <linux/pci.h>10#include <linux/msi.h>11#include <linux/of_pci.h>12#include <linux/pci_hotplug.h>13#include <linux/slab.h>14#include <linux/module.h>15#include <linux/cpumask.h>16#include <linux/aer.h>17#include <linux/acpi.h>18#include <linux/hypervisor.h>19#include <linux/irqdomain.h>20#include <linux/pm_runtime.h>21#include <linux/bitfield.h>22#include "pci.h"23 24#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */25#define CARDBUS_RESERVE_BUSNR 326 27static struct resource busn_resource = {28 .name = "PCI busn",29 .start = 0,30 .end = 255,31 .flags = IORESOURCE_BUS,32};33 34/* Ugh. Need to stop exporting this to modules. */35LIST_HEAD(pci_root_buses);36EXPORT_SYMBOL(pci_root_buses);37 38static LIST_HEAD(pci_domain_busn_res_list);39 40struct pci_domain_busn_res {41 struct list_head list;42 struct resource res;43 int domain_nr;44};45 46static struct resource *get_pci_domain_busn_res(int domain_nr)47{48 struct pci_domain_busn_res *r;49 50 list_for_each_entry(r, &pci_domain_busn_res_list, list)51 if (r->domain_nr == domain_nr)52 return &r->res;53 54 r = kzalloc(sizeof(*r), GFP_KERNEL);55 if (!r)56 return NULL;57 58 r->domain_nr = domain_nr;59 r->res.start = 0;60 r->res.end = 0xff;61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;62 63 list_add_tail(&r->list, &pci_domain_busn_res_list);64 65 return &r->res;66}67 68/*69 * Some device drivers need know if PCI is initiated.70 * Basically, we think PCI is not initiated when there71 * is no device to be found on the pci_bus_type.72 */73int no_pci_devices(void)74{75 struct device *dev;76 int no_devices;77 78 dev = bus_find_next_device(&pci_bus_type, NULL);79 no_devices = (dev == NULL);80 put_device(dev);81 return no_devices;82}83EXPORT_SYMBOL(no_pci_devices);84 85/*86 * PCI Bus Class87 */88static void release_pcibus_dev(struct device *dev)89{90 struct pci_bus *pci_bus = to_pci_bus(dev);91 92 put_device(pci_bus->bridge);93 pci_bus_remove_resources(pci_bus);94 pci_release_bus_of_node(pci_bus);95 kfree(pci_bus);96}97 98static const struct class pcibus_class = {99 .name = "pci_bus",100 .dev_release = &release_pcibus_dev,101 .dev_groups = pcibus_groups,102};103 104static int __init pcibus_class_init(void)105{106 return class_register(&pcibus_class);107}108postcore_initcall(pcibus_class_init);109 110static u64 pci_size(u64 base, u64 maxbase, u64 mask)111{112 u64 size = mask & maxbase; /* Find the significant bits */113 if (!size)114 return 0;115 116 /*117 * Get the lowest of them to find the decode size, and from that118 * the extent.119 */120 size = size & ~(size-1);121 122 /*123 * base == maxbase can be valid only if the BAR has already been124 * programmed with all 1s.125 */126 if (base == maxbase && ((base | (size - 1)) & mask) != mask)127 return 0;128 129 return size;130}131 132static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)133{134 u32 mem_type;135 unsigned long flags;136 137 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {138 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;139 flags |= IORESOURCE_IO;140 return flags;141 }142 143 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;144 flags |= IORESOURCE_MEM;145 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)146 flags |= IORESOURCE_PREFETCH;147 148 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;149 switch (mem_type) {150 case PCI_BASE_ADDRESS_MEM_TYPE_32:151 break;152 case PCI_BASE_ADDRESS_MEM_TYPE_1M:153 /* 1M mem BAR treated as 32-bit BAR */154 break;155 case PCI_BASE_ADDRESS_MEM_TYPE_64:156 flags |= IORESOURCE_MEM_64;157 break;158 default:159 /* mem unknown type treated as 32-bit BAR */160 break;161 }162 return flags;163}164 165#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)166 167/**168 * __pci_read_base - Read a PCI BAR169 * @dev: the PCI device170 * @type: type of the BAR171 * @res: resource buffer to be filled in172 * @pos: BAR position in the config space173 *174 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.175 */176int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,177 struct resource *res, unsigned int pos)178{179 u32 l = 0, sz = 0, mask;180 u64 l64, sz64, mask64;181 u16 orig_cmd;182 struct pci_bus_region region, inverted_region;183 const char *res_name = pci_resource_name(dev, res - dev->resource);184 185 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;186 187 /* No printks while decoding is disabled! */188 if (!dev->mmio_always_on) {189 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);190 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {191 pci_write_config_word(dev, PCI_COMMAND,192 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);193 }194 }195 196 res->name = pci_name(dev);197 198 pci_read_config_dword(dev, pos, &l);199 pci_write_config_dword(dev, pos, l | mask);200 pci_read_config_dword(dev, pos, &sz);201 pci_write_config_dword(dev, pos, l);202 203 /*204 * All bits set in sz means the device isn't working properly.205 * If the BAR isn't implemented, all bits must be 0. If it's a206 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit207 * 1 must be clear.208 */209 if (PCI_POSSIBLE_ERROR(sz))210 sz = 0;211 212 /*213 * I don't know how l can have all bits set. Copied from old code.214 * Maybe it fixes a bug on some ancient platform.215 */216 if (PCI_POSSIBLE_ERROR(l))217 l = 0;218 219 if (type == pci_bar_unknown) {220 res->flags = decode_bar(dev, l);221 res->flags |= IORESOURCE_SIZEALIGN;222 if (res->flags & IORESOURCE_IO) {223 l64 = l & PCI_BASE_ADDRESS_IO_MASK;224 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;225 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;226 } else {227 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;228 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;229 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;230 }231 } else {232 if (l & PCI_ROM_ADDRESS_ENABLE)233 res->flags |= IORESOURCE_ROM_ENABLE;234 l64 = l & PCI_ROM_ADDRESS_MASK;235 sz64 = sz & PCI_ROM_ADDRESS_MASK;236 mask64 = PCI_ROM_ADDRESS_MASK;237 }238 239 if (res->flags & IORESOURCE_MEM_64) {240 pci_read_config_dword(dev, pos + 4, &l);241 pci_write_config_dword(dev, pos + 4, ~0);242 pci_read_config_dword(dev, pos + 4, &sz);243 pci_write_config_dword(dev, pos + 4, l);244 245 l64 |= ((u64)l << 32);246 sz64 |= ((u64)sz << 32);247 mask64 |= ((u64)~0 << 32);248 }249 250 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))251 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);252 253 if (!sz64)254 goto fail;255 256 sz64 = pci_size(l64, sz64, mask64);257 if (!sz64) {258 pci_info(dev, FW_BUG "%s: invalid; can't size\n", res_name);259 goto fail;260 }261 262 if (res->flags & IORESOURCE_MEM_64) {263 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)264 && sz64 > 0x100000000ULL) {265 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;266 res->start = 0;267 res->end = 0;268 pci_err(dev, "%s: can't handle BAR larger than 4GB (size %#010llx)\n",269 res_name, (unsigned long long)sz64);270 goto out;271 }272 273 if ((sizeof(pci_bus_addr_t) < 8) && l) {274 /* Above 32-bit boundary; try to reallocate */275 res->flags |= IORESOURCE_UNSET;276 res->start = 0;277 res->end = sz64 - 1;278 pci_info(dev, "%s: can't handle BAR above 4GB (bus address %#010llx)\n",279 res_name, (unsigned long long)l64);280 goto out;281 }282 }283 284 region.start = l64;285 region.end = l64 + sz64 - 1;286 287 pcibios_bus_to_resource(dev->bus, res, ®ion);288 pcibios_resource_to_bus(dev->bus, &inverted_region, res);289 290 /*291 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is292 * the corresponding resource address (the physical address used by293 * the CPU. Converting that resource address back to a bus address294 * should yield the original BAR value:295 *296 * resource_to_bus(bus_to_resource(A)) == A297 *298 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not299 * be claimed by the device.300 */301 if (inverted_region.start != region.start) {302 res->flags |= IORESOURCE_UNSET;303 res->start = 0;304 res->end = region.end - region.start;305 pci_info(dev, "%s: initial BAR value %#010llx invalid\n",306 res_name, (unsigned long long)region.start);307 }308 309 goto out;310 311 312fail:313 res->flags = 0;314out:315 if (res->flags)316 pci_info(dev, "%s %pR\n", res_name, res);317 318 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;319}320 321static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)322{323 unsigned int pos, reg;324 325 if (dev->non_compliant_bars)326 return;327 328 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */329 if (dev->is_virtfn)330 return;331 332 for (pos = 0; pos < howmany; pos++) {333 struct resource *res = &dev->resource[pos];334 reg = PCI_BASE_ADDRESS_0 + (pos << 2);335 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);336 }337 338 if (rom) {339 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];340 dev->rom_base_reg = rom;341 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |342 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;343 __pci_read_base(dev, pci_bar_mem32, res, rom);344 }345}346 347static void pci_read_bridge_io(struct pci_dev *dev, struct resource *res,348 bool log)349{350 u8 io_base_lo, io_limit_lo;351 unsigned long io_mask, io_granularity, base, limit;352 struct pci_bus_region region;353 354 io_mask = PCI_IO_RANGE_MASK;355 io_granularity = 0x1000;356 if (dev->io_window_1k) {357 /* Support 1K I/O space granularity */358 io_mask = PCI_IO_1K_RANGE_MASK;359 io_granularity = 0x400;360 }361 362 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);363 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);364 base = (io_base_lo & io_mask) << 8;365 limit = (io_limit_lo & io_mask) << 8;366 367 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {368 u16 io_base_hi, io_limit_hi;369 370 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);371 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);372 base |= ((unsigned long) io_base_hi << 16);373 limit |= ((unsigned long) io_limit_hi << 16);374 }375 376 if (base <= limit) {377 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;378 region.start = base;379 region.end = limit + io_granularity - 1;380 pcibios_bus_to_resource(dev->bus, res, ®ion);381 if (log)382 pci_info(dev, " bridge window %pR\n", res);383 }384}385 386static void pci_read_bridge_mmio(struct pci_dev *dev, struct resource *res,387 bool log)388{389 u16 mem_base_lo, mem_limit_lo;390 unsigned long base, limit;391 struct pci_bus_region region;392 393 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);394 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);395 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;396 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;397 if (base <= limit) {398 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;399 region.start = base;400 region.end = limit + 0xfffff;401 pcibios_bus_to_resource(dev->bus, res, ®ion);402 if (log)403 pci_info(dev, " bridge window %pR\n", res);404 }405}406 407static void pci_read_bridge_mmio_pref(struct pci_dev *dev, struct resource *res,408 bool log)409{410 u16 mem_base_lo, mem_limit_lo;411 u64 base64, limit64;412 pci_bus_addr_t base, limit;413 struct pci_bus_region region;414 415 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);416 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);417 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;418 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;419 420 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {421 u32 mem_base_hi, mem_limit_hi;422 423 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);424 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);425 426 /*427 * Some bridges set the base > limit by default, and some428 * (broken) BIOSes do not initialize them. If we find429 * this, just assume they are not being used.430 */431 if (mem_base_hi <= mem_limit_hi) {432 base64 |= (u64) mem_base_hi << 32;433 limit64 |= (u64) mem_limit_hi << 32;434 }435 }436 437 base = (pci_bus_addr_t) base64;438 limit = (pci_bus_addr_t) limit64;439 440 if (base != base64) {441 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",442 (unsigned long long) base64);443 return;444 }445 446 if (base <= limit) {447 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |448 IORESOURCE_MEM | IORESOURCE_PREFETCH;449 if (res->flags & PCI_PREF_RANGE_TYPE_64)450 res->flags |= IORESOURCE_MEM_64;451 region.start = base;452 region.end = limit + 0xfffff;453 pcibios_bus_to_resource(dev->bus, res, ®ion);454 if (log)455 pci_info(dev, " bridge window %pR\n", res);456 }457}458 459static void pci_read_bridge_windows(struct pci_dev *bridge)460{461 u32 buses;462 u16 io;463 u32 pmem, tmp;464 struct resource res;465 466 pci_read_config_dword(bridge, PCI_PRIMARY_BUS, &buses);467 res.flags = IORESOURCE_BUS;468 res.start = (buses >> 8) & 0xff;469 res.end = (buses >> 16) & 0xff;470 pci_info(bridge, "PCI bridge to %pR%s\n", &res,471 bridge->transparent ? " (subtractive decode)" : "");472 473 pci_read_config_word(bridge, PCI_IO_BASE, &io);474 if (!io) {475 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);476 pci_read_config_word(bridge, PCI_IO_BASE, &io);477 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);478 }479 if (io) {480 bridge->io_window = 1;481 pci_read_bridge_io(bridge, &res, true);482 }483 484 pci_read_bridge_mmio(bridge, &res, true);485 486 /*487 * DECchip 21050 pass 2 errata: the bridge may miss an address488 * disconnect boundary by one PCI data phase. Workaround: do not489 * use prefetching on this device.490 */491 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)492 return;493 494 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);495 if (!pmem) {496 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,497 0xffe0fff0);498 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);499 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);500 }501 if (!pmem)502 return;503 504 bridge->pref_window = 1;505 506 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {507 508 /*509 * Bridge claims to have a 64-bit prefetchable memory510 * window; verify that the upper bits are actually511 * writable.512 */513 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);514 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,515 0xffffffff);516 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);517 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);518 if (tmp)519 bridge->pref_64_window = 1;520 }521 522 pci_read_bridge_mmio_pref(bridge, &res, true);523}524 525void pci_read_bridge_bases(struct pci_bus *child)526{527 struct pci_dev *dev = child->self;528 struct resource *res;529 int i;530 531 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */532 return;533 534 pci_info(dev, "PCI bridge to %pR%s\n",535 &child->busn_res,536 dev->transparent ? " (subtractive decode)" : "");537 538 pci_bus_remove_resources(child);539 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)540 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];541 542 pci_read_bridge_io(child->self, child->resource[0], false);543 pci_read_bridge_mmio(child->self, child->resource[1], false);544 pci_read_bridge_mmio_pref(child->self, child->resource[2], false);545 546 if (dev->transparent) {547 pci_bus_for_each_resource(child->parent, res) {548 if (res && res->flags) {549 pci_bus_add_resource(child, res,550 PCI_SUBTRACTIVE_DECODE);551 pci_info(dev, " bridge window %pR (subtractive decode)\n",552 res);553 }554 }555 }556}557 558static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)559{560 struct pci_bus *b;561 562 b = kzalloc(sizeof(*b), GFP_KERNEL);563 if (!b)564 return NULL;565 566 INIT_LIST_HEAD(&b->node);567 INIT_LIST_HEAD(&b->children);568 INIT_LIST_HEAD(&b->devices);569 INIT_LIST_HEAD(&b->slots);570 INIT_LIST_HEAD(&b->resources);571 b->max_bus_speed = PCI_SPEED_UNKNOWN;572 b->cur_bus_speed = PCI_SPEED_UNKNOWN;573#ifdef CONFIG_PCI_DOMAINS_GENERIC574 if (parent)575 b->domain_nr = parent->domain_nr;576#endif577 return b;578}579 580static void pci_release_host_bridge_dev(struct device *dev)581{582 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);583 584 if (bridge->release_fn)585 bridge->release_fn(bridge);586 587 pci_free_resource_list(&bridge->windows);588 pci_free_resource_list(&bridge->dma_ranges);589 kfree(bridge);590}591 592static void pci_init_host_bridge(struct pci_host_bridge *bridge)593{594 INIT_LIST_HEAD(&bridge->windows);595 INIT_LIST_HEAD(&bridge->dma_ranges);596 597 /*598 * We assume we can manage these PCIe features. Some systems may599 * reserve these for use by the platform itself, e.g., an ACPI BIOS600 * may implement its own AER handling and use _OSC to prevent the601 * OS from interfering.602 */603 bridge->native_aer = 1;604 bridge->native_pcie_hotplug = 1;605 bridge->native_shpc_hotplug = 1;606 bridge->native_pme = 1;607 bridge->native_ltr = 1;608 bridge->native_dpc = 1;609 bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET;610 bridge->native_cxl_error = 1;611 612 device_initialize(&bridge->dev);613}614 615struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)616{617 struct pci_host_bridge *bridge;618 619 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);620 if (!bridge)621 return NULL;622 623 pci_init_host_bridge(bridge);624 bridge->dev.release = pci_release_host_bridge_dev;625 626 return bridge;627}628EXPORT_SYMBOL(pci_alloc_host_bridge);629 630static void devm_pci_alloc_host_bridge_release(void *data)631{632 pci_free_host_bridge(data);633}634 635struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,636 size_t priv)637{638 int ret;639 struct pci_host_bridge *bridge;640 641 bridge = pci_alloc_host_bridge(priv);642 if (!bridge)643 return NULL;644 645 bridge->dev.parent = dev;646 647 ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release,648 bridge);649 if (ret)650 return NULL;651 652 ret = devm_of_pci_bridge_init(dev, bridge);653 if (ret)654 return NULL;655 656 return bridge;657}658EXPORT_SYMBOL(devm_pci_alloc_host_bridge);659 660void pci_free_host_bridge(struct pci_host_bridge *bridge)661{662 put_device(&bridge->dev);663}664EXPORT_SYMBOL(pci_free_host_bridge);665 666/* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */667static const unsigned char pcix_bus_speed[] = {668 PCI_SPEED_UNKNOWN, /* 0 */669 PCI_SPEED_66MHz_PCIX, /* 1 */670 PCI_SPEED_100MHz_PCIX, /* 2 */671 PCI_SPEED_133MHz_PCIX, /* 3 */672 PCI_SPEED_UNKNOWN, /* 4 */673 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */674 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */675 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */676 PCI_SPEED_UNKNOWN, /* 8 */677 PCI_SPEED_66MHz_PCIX_266, /* 9 */678 PCI_SPEED_100MHz_PCIX_266, /* A */679 PCI_SPEED_133MHz_PCIX_266, /* B */680 PCI_SPEED_UNKNOWN, /* C */681 PCI_SPEED_66MHz_PCIX_533, /* D */682 PCI_SPEED_100MHz_PCIX_533, /* E */683 PCI_SPEED_133MHz_PCIX_533 /* F */684};685 686/* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */687const unsigned char pcie_link_speed[] = {688 PCI_SPEED_UNKNOWN, /* 0 */689 PCIE_SPEED_2_5GT, /* 1 */690 PCIE_SPEED_5_0GT, /* 2 */691 PCIE_SPEED_8_0GT, /* 3 */692 PCIE_SPEED_16_0GT, /* 4 */693 PCIE_SPEED_32_0GT, /* 5 */694 PCIE_SPEED_64_0GT, /* 6 */695 PCI_SPEED_UNKNOWN, /* 7 */696 PCI_SPEED_UNKNOWN, /* 8 */697 PCI_SPEED_UNKNOWN, /* 9 */698 PCI_SPEED_UNKNOWN, /* A */699 PCI_SPEED_UNKNOWN, /* B */700 PCI_SPEED_UNKNOWN, /* C */701 PCI_SPEED_UNKNOWN, /* D */702 PCI_SPEED_UNKNOWN, /* E */703 PCI_SPEED_UNKNOWN /* F */704};705EXPORT_SYMBOL_GPL(pcie_link_speed);706 707const char *pci_speed_string(enum pci_bus_speed speed)708{709 /* Indexed by the pci_bus_speed enum */710 static const char *speed_strings[] = {711 "33 MHz PCI", /* 0x00 */712 "66 MHz PCI", /* 0x01 */713 "66 MHz PCI-X", /* 0x02 */714 "100 MHz PCI-X", /* 0x03 */715 "133 MHz PCI-X", /* 0x04 */716 NULL, /* 0x05 */717 NULL, /* 0x06 */718 NULL, /* 0x07 */719 NULL, /* 0x08 */720 "66 MHz PCI-X 266", /* 0x09 */721 "100 MHz PCI-X 266", /* 0x0a */722 "133 MHz PCI-X 266", /* 0x0b */723 "Unknown AGP", /* 0x0c */724 "1x AGP", /* 0x0d */725 "2x AGP", /* 0x0e */726 "4x AGP", /* 0x0f */727 "8x AGP", /* 0x10 */728 "66 MHz PCI-X 533", /* 0x11 */729 "100 MHz PCI-X 533", /* 0x12 */730 "133 MHz PCI-X 533", /* 0x13 */731 "2.5 GT/s PCIe", /* 0x14 */732 "5.0 GT/s PCIe", /* 0x15 */733 "8.0 GT/s PCIe", /* 0x16 */734 "16.0 GT/s PCIe", /* 0x17 */735 "32.0 GT/s PCIe", /* 0x18 */736 "64.0 GT/s PCIe", /* 0x19 */737 };738 739 if (speed < ARRAY_SIZE(speed_strings))740 return speed_strings[speed];741 return "Unknown";742}743EXPORT_SYMBOL_GPL(pci_speed_string);744 745void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)746{747 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];748}749EXPORT_SYMBOL_GPL(pcie_update_link_speed);750 751static unsigned char agp_speeds[] = {752 AGP_UNKNOWN,753 AGP_1X,754 AGP_2X,755 AGP_4X,756 AGP_8X757};758 759static enum pci_bus_speed agp_speed(int agp3, int agpstat)760{761 int index = 0;762 763 if (agpstat & 4)764 index = 3;765 else if (agpstat & 2)766 index = 2;767 else if (agpstat & 1)768 index = 1;769 else770 goto out;771 772 if (agp3) {773 index += 2;774 if (index == 5)775 index = 0;776 }777 778 out:779 return agp_speeds[index];780}781 782static void pci_set_bus_speed(struct pci_bus *bus)783{784 struct pci_dev *bridge = bus->self;785 int pos;786 787 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);788 if (!pos)789 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);790 if (pos) {791 u32 agpstat, agpcmd;792 793 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);794 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);795 796 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);797 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);798 }799 800 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);801 if (pos) {802 u16 status;803 enum pci_bus_speed max;804 805 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,806 &status);807 808 if (status & PCI_X_SSTATUS_533MHZ) {809 max = PCI_SPEED_133MHz_PCIX_533;810 } else if (status & PCI_X_SSTATUS_266MHZ) {811 max = PCI_SPEED_133MHz_PCIX_266;812 } else if (status & PCI_X_SSTATUS_133MHZ) {813 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)814 max = PCI_SPEED_133MHz_PCIX_ECC;815 else816 max = PCI_SPEED_133MHz_PCIX;817 } else {818 max = PCI_SPEED_66MHz_PCIX;819 }820 821 bus->max_bus_speed = max;822 bus->cur_bus_speed =823 pcix_bus_speed[FIELD_GET(PCI_X_SSTATUS_FREQ, status)];824 825 return;826 }827 828 if (pci_is_pcie(bridge)) {829 u32 linkcap;830 u16 linksta;831 832 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);833 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];834 835 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);836 pcie_update_link_speed(bus, linksta);837 }838}839 840static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)841{842 struct irq_domain *d;843 844 /* If the host bridge driver sets a MSI domain of the bridge, use it */845 d = dev_get_msi_domain(bus->bridge);846 847 /*848 * Any firmware interface that can resolve the msi_domain849 * should be called from here.850 */851 if (!d)852 d = pci_host_bridge_of_msi_domain(bus);853 if (!d)854 d = pci_host_bridge_acpi_msi_domain(bus);855 856 /*857 * If no IRQ domain was found via the OF tree, try looking it up858 * directly through the fwnode_handle.859 */860 if (!d) {861 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);862 863 if (fwnode)864 d = irq_find_matching_fwnode(fwnode,865 DOMAIN_BUS_PCI_MSI);866 }867 868 return d;869}870 871static void pci_set_bus_msi_domain(struct pci_bus *bus)872{873 struct irq_domain *d;874 struct pci_bus *b;875 876 /*877 * The bus can be a root bus, a subordinate bus, or a virtual bus878 * created by an SR-IOV device. Walk up to the first bridge device879 * found or derive the domain from the host bridge.880 */881 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {882 if (b->self)883 d = dev_get_msi_domain(&b->self->dev);884 }885 886 if (!d)887 d = pci_host_bridge_msi_domain(b);888 889 dev_set_msi_domain(&bus->dev, d);890}891 892static bool pci_preserve_config(struct pci_host_bridge *host_bridge)893{894 if (pci_acpi_preserve_config(host_bridge))895 return true;896 897 if (host_bridge->dev.parent && host_bridge->dev.parent->of_node)898 return of_pci_preserve_config(host_bridge->dev.parent->of_node);899 900 return false;901}902 903static int pci_register_host_bridge(struct pci_host_bridge *bridge)904{905 struct device *parent = bridge->dev.parent;906 struct resource_entry *window, *next, *n;907 struct pci_bus *bus, *b;908 resource_size_t offset, next_offset;909 LIST_HEAD(resources);910 struct resource *res, *next_res;911 char addr[64], *fmt;912 const char *name;913 int err;914 915 bus = pci_alloc_bus(NULL);916 if (!bus)917 return -ENOMEM;918 919 bridge->bus = bus;920 921 bus->sysdata = bridge->sysdata;922 bus->ops = bridge->ops;923 bus->number = bus->busn_res.start = bridge->busnr;924#ifdef CONFIG_PCI_DOMAINS_GENERIC925 if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET)926 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);927 else928 bus->domain_nr = bridge->domain_nr;929 if (bus->domain_nr < 0) {930 err = bus->domain_nr;931 goto free;932 }933#endif934 935 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);936 if (b) {937 /* Ignore it if we already got here via a different bridge */938 dev_dbg(&b->dev, "bus already known\n");939 err = -EEXIST;940 goto free;941 }942 943 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),944 bridge->busnr);945 946 err = pcibios_root_bridge_prepare(bridge);947 if (err)948 goto free;949 950 /* Temporarily move resources off the list */951 list_splice_init(&bridge->windows, &resources);952 err = device_add(&bridge->dev);953 if (err) {954 put_device(&bridge->dev);955 goto free;956 }957 bus->bridge = get_device(&bridge->dev);958 device_enable_async_suspend(bus->bridge);959 pci_set_bus_of_node(bus);960 pci_set_bus_msi_domain(bus);961 if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) &&962 !pci_host_of_has_msi_map(parent))963 bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI;964 965 if (!parent)966 set_dev_node(bus->bridge, pcibus_to_node(bus));967 968 bus->dev.class = &pcibus_class;969 bus->dev.parent = bus->bridge;970 971 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);972 name = dev_name(&bus->dev);973 974 err = device_register(&bus->dev);975 if (err)976 goto unregister;977 978 pcibios_add_bus(bus);979 980 if (bus->ops->add_bus) {981 err = bus->ops->add_bus(bus);982 if (WARN_ON(err < 0))983 dev_err(&bus->dev, "failed to add bus: %d\n", err);984 }985 986 /* Create legacy_io and legacy_mem files for this bus */987 pci_create_legacy_files(bus);988 989 if (parent)990 dev_info(parent, "PCI host bridge to bus %s\n", name);991 else992 pr_info("PCI host bridge to bus %s\n", name);993 994 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE)995 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n");996 997 /* Check if the boot configuration by FW needs to be preserved */998 bridge->preserve_config = pci_preserve_config(bridge);999 1000 /* Coalesce contiguous windows */1001 resource_list_for_each_entry_safe(window, n, &resources) {1002 if (list_is_last(&window->node, &resources))1003 break;1004 1005 next = list_next_entry(window, node);1006 offset = window->offset;1007 res = window->res;1008 next_offset = next->offset;1009 next_res = next->res;1010 1011 if (res->flags != next_res->flags || offset != next_offset)1012 continue;1013 1014 if (res->end + 1 == next_res->start) {1015 next_res->start = res->start;1016 res->flags = res->start = res->end = 0;1017 }1018 }1019 1020 /* Add initial resources to the bus */1021 resource_list_for_each_entry_safe(window, n, &resources) {1022 offset = window->offset;1023 res = window->res;1024 if (!res->flags && !res->start && !res->end) {1025 release_resource(res);1026 resource_list_destroy_entry(window);1027 continue;1028 }1029 1030 list_move_tail(&window->node, &bridge->windows);1031 1032 if (res->flags & IORESOURCE_BUS)1033 pci_bus_insert_busn_res(bus, bus->number, res->end);1034 else1035 pci_bus_add_resource(bus, res, 0);1036 1037 if (offset) {1038 if (resource_type(res) == IORESOURCE_IO)1039 fmt = " (bus address [%#06llx-%#06llx])";1040 else1041 fmt = " (bus address [%#010llx-%#010llx])";1042 1043 snprintf(addr, sizeof(addr), fmt,1044 (unsigned long long)(res->start - offset),1045 (unsigned long long)(res->end - offset));1046 } else1047 addr[0] = '\0';1048 1049 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);1050 }1051 1052 down_write(&pci_bus_sem);1053 list_add_tail(&bus->node, &pci_root_buses);1054 up_write(&pci_bus_sem);1055 1056 return 0;1057 1058unregister:1059 put_device(&bridge->dev);1060 device_del(&bridge->dev);1061 1062free:1063#ifdef CONFIG_PCI_DOMAINS_GENERIC1064 pci_bus_release_domain_nr(parent, bus->domain_nr);1065#endif1066 kfree(bus);1067 return err;1068}1069 1070static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)1071{1072 int pos;1073 u32 status;1074 1075 /*1076 * If extended config space isn't accessible on a bridge's primary1077 * bus, we certainly can't access it on the secondary bus.1078 */1079 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)1080 return false;1081 1082 /*1083 * PCIe Root Ports and switch ports are PCIe on both sides, so if1084 * extended config space is accessible on the primary, it's also1085 * accessible on the secondary.1086 */1087 if (pci_is_pcie(bridge) &&1088 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||1089 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||1090 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))1091 return true;1092 1093 /*1094 * For the other bridge types:1095 * - PCI-to-PCI bridges1096 * - PCIe-to-PCI/PCI-X forward bridges1097 * - PCI/PCI-X-to-PCIe reverse bridges1098 * extended config space on the secondary side is only accessible1099 * if the bridge supports PCI-X Mode 2.1100 */1101 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);1102 if (!pos)1103 return false;1104 1105 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);1106 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);1107}1108 1109static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,1110 struct pci_dev *bridge, int busnr)1111{1112 struct pci_bus *child;1113 struct pci_host_bridge *host;1114 int i;1115 int ret;1116 1117 /* Allocate a new bus and inherit stuff from the parent */1118 child = pci_alloc_bus(parent);1119 if (!child)1120 return NULL;1121 1122 child->parent = parent;1123 child->sysdata = parent->sysdata;1124 child->bus_flags = parent->bus_flags;1125 1126 host = pci_find_host_bridge(parent);1127 if (host->child_ops)1128 child->ops = host->child_ops;1129 else1130 child->ops = parent->ops;1131 1132 /*1133 * Initialize some portions of the bus device, but don't register1134 * it now as the parent is not properly set up yet.1135 */1136 child->dev.class = &pcibus_class;1137 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);1138 1139 /* Set up the primary, secondary and subordinate bus numbers */1140 child->number = child->busn_res.start = busnr;1141 child->primary = parent->busn_res.start;1142 child->busn_res.end = 0xff;1143 1144 if (!bridge) {1145 child->dev.parent = parent->bridge;1146 goto add_dev;1147 }1148 1149 child->self = bridge;1150 child->bridge = get_device(&bridge->dev);1151 child->dev.parent = child->bridge;1152 pci_set_bus_of_node(child);1153 pci_set_bus_speed(child);1154 1155 /*1156 * Check whether extended config space is accessible on the child1157 * bus. Note that we currently assume it is always accessible on1158 * the root bus.1159 */1160 if (!pci_bridge_child_ext_cfg_accessible(bridge)) {1161 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;1162 pci_info(child, "extended config space not accessible\n");1163 }1164 1165 /* Set up default resource pointers and names */1166 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {1167 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];1168 child->resource[i]->name = child->name;1169 }1170 bridge->subordinate = child;1171 1172add_dev:1173 pci_set_bus_msi_domain(child);1174 ret = device_register(&child->dev);1175 WARN_ON(ret < 0);1176 1177 pcibios_add_bus(child);1178 1179 if (child->ops->add_bus) {1180 ret = child->ops->add_bus(child);1181 if (WARN_ON(ret < 0))1182 dev_err(&child->dev, "failed to add bus: %d\n", ret);1183 }1184 1185 /* Create legacy_io and legacy_mem files for this bus */1186 pci_create_legacy_files(child);1187 1188 return child;1189}1190 1191struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,1192 int busnr)1193{1194 struct pci_bus *child;1195 1196 child = pci_alloc_child_bus(parent, dev, busnr);1197 if (child) {1198 down_write(&pci_bus_sem);1199 list_add_tail(&child->node, &parent->children);1200 up_write(&pci_bus_sem);1201 }1202 return child;1203}1204EXPORT_SYMBOL(pci_add_new_bus);1205 1206static void pci_enable_rrs_sv(struct pci_dev *pdev)1207{1208 u16 root_cap = 0;1209 1210 /* Enable Configuration RRS Software Visibility if supported */1211 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);1212 if (root_cap & PCI_EXP_RTCAP_RRS_SV) {1213 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,1214 PCI_EXP_RTCTL_RRS_SVE);1215 pdev->config_rrs_sv = 1;1216 }1217}1218 1219static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,1220 unsigned int available_buses);1221/**1222 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus1223 * numbers from EA capability.1224 * @dev: Bridge1225 * @sec: updated with secondary bus number from EA1226 * @sub: updated with subordinate bus number from EA1227 *1228 * If @dev is a bridge with EA capability that specifies valid secondary1229 * and subordinate bus numbers, return true with the bus numbers in @sec1230 * and @sub. Otherwise return false.1231 */1232static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub)1233{1234 int ea, offset;1235 u32 dw;1236 u8 ea_sec, ea_sub;1237 1238 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)1239 return false;1240 1241 /* find PCI EA capability in list */1242 ea = pci_find_capability(dev, PCI_CAP_ID_EA);1243 if (!ea)1244 return false;1245 1246 offset = ea + PCI_EA_FIRST_ENT;1247 pci_read_config_dword(dev, offset, &dw);1248 ea_sec = FIELD_GET(PCI_EA_SEC_BUS_MASK, dw);1249 ea_sub = FIELD_GET(PCI_EA_SUB_BUS_MASK, dw);1250 if (ea_sec == 0 || ea_sub < ea_sec)1251 return false;1252 1253 *sec = ea_sec;1254 *sub = ea_sub;1255 return true;1256}1257 1258/*1259 * pci_scan_bridge_extend() - Scan buses behind a bridge1260 * @bus: Parent bus the bridge is on1261 * @dev: Bridge itself1262 * @max: Starting subordinate number of buses behind this bridge1263 * @available_buses: Total number of buses available for this bridge and1264 * the devices below. After the minimal bus space has1265 * been allocated the remaining buses will be1266 * distributed equally between hotplug-capable bridges.1267 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges1268 * that need to be reconfigured.1269 *1270 * If it's a bridge, configure it and scan the bus behind it.1271 * For CardBus bridges, we don't scan behind as the devices will1272 * be handled by the bridge driver itself.1273 *1274 * We need to process bridges in two passes -- first we scan those1275 * already configured by the BIOS and after we are done with all of1276 * them, we proceed to assigning numbers to the remaining buses in1277 * order to avoid overlaps between old and new bus numbers.1278 *1279 * Return: New subordinate number covering all buses behind this bridge.1280 */1281static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,1282 int max, unsigned int available_buses,1283 int pass)1284{1285 struct pci_bus *child;1286 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);1287 u32 buses, i, j = 0;1288 u16 bctl;1289 u8 primary, secondary, subordinate;1290 int broken = 0;1291 bool fixed_buses;1292 u8 fixed_sec, fixed_sub;1293 int next_busnr;1294 1295 /*1296 * Make sure the bridge is powered on to be able to access config1297 * space of devices below it.1298 */1299 pm_runtime_get_sync(&dev->dev);1300 1301 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);1302 primary = buses & 0xFF;1303 secondary = (buses >> 8) & 0xFF;1304 subordinate = (buses >> 16) & 0xFF;1305 1306 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",1307 secondary, subordinate, pass);1308 1309 if (!primary && (primary != bus->number) && secondary && subordinate) {1310 pci_warn(dev, "Primary bus is hard wired to 0\n");1311 primary = bus->number;1312 }1313 1314 /* Check if setup is sensible at all */1315 if (!pass &&1316 (primary != bus->number || secondary <= bus->number ||1317 secondary > subordinate)) {1318 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",1319 secondary, subordinate);1320 broken = 1;1321 }1322 1323 /*1324 * Disable Master-Abort Mode during probing to avoid reporting of1325 * bus errors in some architectures.1326 */1327 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);1328 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,1329 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);1330 1331 pci_enable_rrs_sv(dev);1332 1333 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&1334 !is_cardbus && !broken) {1335 unsigned int cmax, buses;1336 1337 /*1338 * Bus already configured by firmware, process it in the1339 * first pass and just note the configuration.1340 */1341 if (pass)1342 goto out;1343 1344 /*1345 * The bus might already exist for two reasons: Either we1346 * are rescanning the bus or the bus is reachable through1347 * more than one bridge. The second case can happen with1348 * the i450NX chipset.1349 */1350 child = pci_find_bus(pci_domain_nr(bus), secondary);1351 if (!child) {1352 child = pci_add_new_bus(bus, dev, secondary);1353 if (!child)1354 goto out;1355 child->primary = primary;1356 pci_bus_insert_busn_res(child, secondary, subordinate);1357 child->bridge_ctl = bctl;1358 }1359 1360 buses = subordinate - secondary;1361 cmax = pci_scan_child_bus_extend(child, buses);1362 if (cmax > subordinate)1363 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",1364 subordinate, cmax);1365 1366 /* Subordinate should equal child->busn_res.end */1367 if (subordinate > max)1368 max = subordinate;1369 } else {1370 1371 /*1372 * We need to assign a number to this bus which we always1373 * do in the second pass.1374 */1375 if (!pass) {1376 if (pcibios_assign_all_busses() || broken || is_cardbus)1377 1378 /*1379 * Temporarily disable forwarding of the1380 * configuration cycles on all bridges in1381 * this bus segment to avoid possible1382 * conflicts in the second pass between two1383 * bridges programmed with overlapping bus1384 * ranges.1385 */1386 pci_write_config_dword(dev, PCI_PRIMARY_BUS,1387 buses & ~0xffffff);1388 goto out;1389 }1390 1391 /* Clear errors */1392 pci_write_config_word(dev, PCI_STATUS, 0xffff);1393 1394 /* Read bus numbers from EA Capability (if present) */1395 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub);1396 if (fixed_buses)1397 next_busnr = fixed_sec;1398 else1399 next_busnr = max + 1;1400 1401 /*1402 * Prevent assigning a bus number that already exists.1403 * This can happen when a bridge is hot-plugged, so in this1404 * case we only re-scan this bus.1405 */1406 child = pci_find_bus(pci_domain_nr(bus), next_busnr);1407 if (!child) {1408 child = pci_add_new_bus(bus, dev, next_busnr);1409 if (!child)1410 goto out;1411 pci_bus_insert_busn_res(child, next_busnr,1412 bus->busn_res.end);1413 }1414 max++;1415 if (available_buses)1416 available_buses--;1417 1418 buses = (buses & 0xff000000)1419 | ((unsigned int)(child->primary) << 0)1420 | ((unsigned int)(child->busn_res.start) << 8)1421 | ((unsigned int)(child->busn_res.end) << 16);1422 1423 /*1424 * yenta.c forces a secondary latency timer of 176.1425 * Copy that behaviour here.1426 */1427 if (is_cardbus) {1428 buses &= ~0xff000000;1429 buses |= CARDBUS_LATENCY_TIMER << 24;1430 }1431 1432 /* We need to blast all three values with a single write */1433 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);1434 1435 if (!is_cardbus) {1436 child->bridge_ctl = bctl;1437 max = pci_scan_child_bus_extend(child, available_buses);1438 } else {1439 1440 /*1441 * For CardBus bridges, we leave 4 bus numbers as1442 * cards with a PCI-to-PCI bridge can be inserted1443 * later.1444 */1445 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {1446 struct pci_bus *parent = bus;1447 if (pci_find_bus(pci_domain_nr(bus),1448 max+i+1))1449 break;1450 while (parent->parent) {1451 if ((!pcibios_assign_all_busses()) &&1452 (parent->busn_res.end > max) &&1453 (parent->busn_res.end <= max+i)) {1454 j = 1;1455 }1456 parent = parent->parent;1457 }1458 if (j) {1459 1460 /*1461 * Often, there are two CardBus1462 * bridges -- try to leave one1463 * valid bus number for each one.1464 */1465 i /= 2;1466 break;1467 }1468 }1469 max += i;1470 }1471 1472 /*1473 * Set subordinate bus number to its real value.1474 * If fixed subordinate bus number exists from EA1475 * capability then use it.1476 */1477 if (fixed_buses)1478 max = fixed_sub;1479 pci_bus_update_busn_res_end(child, max);1480 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);1481 }1482 1483 sprintf(child->name,1484 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),1485 pci_domain_nr(bus), child->number);1486 1487 /* Check that all devices are accessible */1488 while (bus->parent) {1489 if ((child->busn_res.end > bus->busn_res.end) ||1490 (child->number > bus->busn_res.end) ||1491 (child->number < bus->number) ||1492 (child->busn_res.end < bus->number)) {1493 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n",1494 &child->busn_res);1495 break;1496 }1497 bus = bus->parent;1498 }1499 1500out:1501 /* Clear errors in the Secondary Status Register */1502 pci_write_config_word(dev, PCI_SEC_STATUS, 0xffff);1503 1504 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);1505 1506 pm_runtime_put(&dev->dev);1507 1508 return max;1509}1510 1511/*1512 * pci_scan_bridge() - Scan buses behind a bridge1513 * @bus: Parent bus the bridge is on1514 * @dev: Bridge itself1515 * @max: Starting subordinate number of buses behind this bridge1516 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges1517 * that need to be reconfigured.1518 *1519 * If it's a bridge, configure it and scan the bus behind it.1520 * For CardBus bridges, we don't scan behind as the devices will1521 * be handled by the bridge driver itself.1522 *1523 * We need to process bridges in two passes -- first we scan those1524 * already configured by the BIOS and after we are done with all of1525 * them, we proceed to assigning numbers to the remaining buses in1526 * order to avoid overlaps between old and new bus numbers.1527 *1528 * Return: New subordinate number covering all buses behind this bridge.1529 */1530int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)1531{1532 return pci_scan_bridge_extend(bus, dev, max, 0, pass);1533}1534EXPORT_SYMBOL(pci_scan_bridge);1535 1536/*1537 * Read interrupt line and base address registers.1538 * The architecture-dependent code can tweak these, of course.1539 */1540static void pci_read_irq(struct pci_dev *dev)1541{1542 unsigned char irq;1543 1544 /* VFs are not allowed to use INTx, so skip the config reads */1545 if (dev->is_virtfn) {1546 dev->pin = 0;1547 dev->irq = 0;1548 return;1549 }1550 1551 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);1552 dev->pin = irq;1553 if (irq)1554 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);1555 dev->irq = irq;1556}1557 1558void set_pcie_port_type(struct pci_dev *pdev)1559{1560 int pos;1561 u16 reg16;1562 u32 reg32;1563 int type;1564 struct pci_dev *parent;1565 1566 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);1567 if (!pos)1568 return;1569 1570 pdev->pcie_cap = pos;1571 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);1572 pdev->pcie_flags_reg = reg16;1573 pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap);1574 pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap);1575 1576 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32);1577 if (reg32 & PCI_EXP_LNKCAP_DLLLARC)1578 pdev->link_active_reporting = 1;1579 1580 parent = pci_upstream_bridge(pdev);1581 if (!parent)1582 return;1583 1584 /*1585 * Some systems do not identify their upstream/downstream ports1586 * correctly so detect impossible configurations here and correct1587 * the port type accordingly.1588 */1589 type = pci_pcie_type(pdev);1590 if (type == PCI_EXP_TYPE_DOWNSTREAM) {1591 /*1592 * If pdev claims to be downstream port but the parent1593 * device is also downstream port assume pdev is actually1594 * upstream port.1595 */1596 if (pcie_downstream_port(parent)) {1597 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n");1598 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;1599 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM;1600 }1601 } else if (type == PCI_EXP_TYPE_UPSTREAM) {1602 /*1603 * If pdev claims to be upstream port but the parent1604 * device is also upstream port assume pdev is actually1605 * downstream port.1606 */1607 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) {1608 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n");1609 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;1610 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM;1611 }1612 }1613}1614 1615void set_pcie_hotplug_bridge(struct pci_dev *pdev)1616{1617 u32 reg32;1618 1619 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);1620 if (reg32 & PCI_EXP_SLTCAP_HPC)1621 pdev->is_hotplug_bridge = 1;1622}1623 1624static void set_pcie_thunderbolt(struct pci_dev *dev)1625{1626 u16 vsec;1627 1628 /* Is the device part of a Thunderbolt controller? */1629 vsec = pci_find_vsec_capability(dev, PCI_VENDOR_ID_INTEL, PCI_VSEC_ID_INTEL_TBT);1630 if (vsec)1631 dev->is_thunderbolt = 1;1632}1633 1634static void set_pcie_untrusted(struct pci_dev *dev)1635{1636 struct pci_dev *parent;1637 1638 /*1639 * If the upstream bridge is untrusted we treat this device1640 * untrusted as well.1641 */1642 parent = pci_upstream_bridge(dev);1643 if (parent && (parent->untrusted || parent->external_facing))1644 dev->untrusted = true;1645}1646 1647static void pci_set_removable(struct pci_dev *dev)1648{1649 struct pci_dev *parent = pci_upstream_bridge(dev);1650 1651 /*1652 * We (only) consider everything downstream from an external_facing1653 * device to be removable by the user. We're mainly concerned with1654 * consumer platforms with user accessible thunderbolt ports that are1655 * vulnerable to DMA attacks, and we expect those ports to be marked by1656 * the firmware as external_facing. Devices in traditional hotplug1657 * slots can technically be removed, but the expectation is that unless1658 * the port is marked with external_facing, such devices are less1659 * accessible to user / may not be removed by end user, and thus not1660 * exposed as "removable" to userspace.1661 */1662 if (parent &&1663 (parent->external_facing || dev_is_removable(&parent->dev)))1664 dev_set_removable(&dev->dev, DEVICE_REMOVABLE);1665}1666 1667/**1668 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?1669 * @dev: PCI device1670 *1671 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that1672 * when forwarding a type1 configuration request the bridge must check that1673 * the extended register address field is zero. The bridge is not permitted1674 * to forward the transactions and must handle it as an Unsupported Request.1675 * Some bridges do not follow this rule and simply drop the extended register1676 * bits, resulting in the standard config space being aliased, every 2561677 * bytes across the entire configuration space. Test for this condition by1678 * comparing the first dword of each potential alias to the vendor/device ID.1679 * Known offenders:1680 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)1681 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)1682 */1683static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)1684{1685#ifdef CONFIG_PCI_QUIRKS1686 int pos, ret;1687 u32 header, tmp;1688 1689 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);1690 1691 for (pos = PCI_CFG_SPACE_SIZE;1692 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {1693 ret = pci_read_config_dword(dev, pos, &tmp);1694 if ((ret != PCIBIOS_SUCCESSFUL) || (header != tmp))1695 return false;1696 }1697 1698 return true;1699#else1700 return false;1701#endif1702}1703 1704/**1705 * pci_cfg_space_size_ext - Get the configuration space size of the PCI device1706 * @dev: PCI device1707 *1708 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices1709 * have 4096 bytes. Even if the device is capable, that doesn't mean we can1710 * access it. Maybe we don't have a way to generate extended config space1711 * accesses, or the device is behind a reverse Express bridge. So we try1712 * reading the dword at 0x100 which must either be 0 or a valid extended1713 * capability header.1714 */1715static int pci_cfg_space_size_ext(struct pci_dev *dev)1716{1717 u32 status;1718 int pos = PCI_CFG_SPACE_SIZE;1719 1720 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)1721 return PCI_CFG_SPACE_SIZE;1722 if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev))1723 return PCI_CFG_SPACE_SIZE;1724 1725 return PCI_CFG_SPACE_EXP_SIZE;1726}1727 1728int pci_cfg_space_size(struct pci_dev *dev)1729{1730 int pos;1731 u32 status;1732 u16 class;1733 1734#ifdef CONFIG_PCI_IOV1735 /*1736 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to1737 * implement a PCIe capability and therefore must implement extended1738 * config space. We can skip the NO_EXTCFG test below and the1739 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of1740 * the fact that the SR-IOV capability on the PF resides in extended1741 * config space and must be accessible and non-aliased to have enabled1742 * support for this VF. This is a micro performance optimization for1743 * systems supporting many VFs.1744 */1745 if (dev->is_virtfn)1746 return PCI_CFG_SPACE_EXP_SIZE;1747#endif1748 1749 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)1750 return PCI_CFG_SPACE_SIZE;1751 1752 class = dev->class >> 8;1753 if (class == PCI_CLASS_BRIDGE_HOST)1754 return pci_cfg_space_size_ext(dev);1755 1756 if (pci_is_pcie(dev))1757 return pci_cfg_space_size_ext(dev);1758 1759 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);1760 if (!pos)1761 return PCI_CFG_SPACE_SIZE;1762 1763 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);1764 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))1765 return pci_cfg_space_size_ext(dev);1766 1767 return PCI_CFG_SPACE_SIZE;1768}1769 1770static u32 pci_class(struct pci_dev *dev)1771{1772 u32 class;1773 1774#ifdef CONFIG_PCI_IOV1775 if (dev->is_virtfn)1776 return dev->physfn->sriov->class;1777#endif1778 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);1779 return class;1780}1781 1782static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)1783{1784#ifdef CONFIG_PCI_IOV1785 if (dev->is_virtfn) {1786 *vendor = dev->physfn->sriov->subsystem_vendor;1787 *device = dev->physfn->sriov->subsystem_device;1788 return;1789 }1790#endif1791 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor);1792 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device);1793}1794 1795static u8 pci_hdr_type(struct pci_dev *dev)1796{1797 u8 hdr_type;1798 1799#ifdef CONFIG_PCI_IOV1800 if (dev->is_virtfn)1801 return dev->physfn->sriov->hdr_type;1802#endif1803 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);1804 return hdr_type;1805}1806 1807#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)1808 1809/**1810 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability1811 * @dev: PCI device1812 *1813 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this1814 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.1815 */1816static int pci_intx_mask_broken(struct pci_dev *dev)1817{1818 u16 orig, toggle, new;1819 1820 pci_read_config_word(dev, PCI_COMMAND, &orig);1821 toggle = orig ^ PCI_COMMAND_INTX_DISABLE;1822 pci_write_config_word(dev, PCI_COMMAND, toggle);1823 pci_read_config_word(dev, PCI_COMMAND, &new);1824 1825 pci_write_config_word(dev, PCI_COMMAND, orig);1826 1827 /*1828 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI1829 * r2.3, so strictly speaking, a device is not *broken* if it's not1830 * writable. But we'll live with the misnomer for now.1831 */1832 if (new != toggle)1833 return 1;1834 return 0;1835}1836 1837static void early_dump_pci_device(struct pci_dev *pdev)1838{1839 u32 value[256 / 4];1840 int i;1841 1842 pci_info(pdev, "config space:\n");1843 1844 for (i = 0; i < 256; i += 4)1845 pci_read_config_dword(pdev, i, &value[i / 4]);1846 1847 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,1848 value, 256, false);1849}1850 1851static const char *pci_type_str(struct pci_dev *dev)1852{1853 static const char * const str[] = {1854 "PCIe Endpoint",1855 "PCIe Legacy Endpoint",1856 "PCIe unknown",1857 "PCIe unknown",1858 "PCIe Root Port",1859 "PCIe Switch Upstream Port",1860 "PCIe Switch Downstream Port",1861 "PCIe to PCI/PCI-X bridge",1862 "PCI/PCI-X to PCIe bridge",1863 "PCIe Root Complex Integrated Endpoint",1864 "PCIe Root Complex Event Collector",1865 };1866 int type;1867 1868 if (pci_is_pcie(dev)) {1869 type = pci_pcie_type(dev);1870 if (type < ARRAY_SIZE(str))1871 return str[type];1872 1873 return "PCIe unknown";1874 }1875 1876 switch (dev->hdr_type) {1877 case PCI_HEADER_TYPE_NORMAL:1878 return "conventional PCI endpoint";1879 case PCI_HEADER_TYPE_BRIDGE:1880 return "conventional PCI bridge";1881 case PCI_HEADER_TYPE_CARDBUS:1882 return "CardBus bridge";1883 default:1884 return "conventional PCI";1885 }1886}1887 1888/**1889 * pci_setup_device - Fill in class and map information of a device1890 * @dev: the device structure to fill1891 *1892 * Initialize the device structure with information about the device's1893 * vendor,class,memory and IO-space addresses, IRQ lines etc.1894 * Called at initialisation of the PCI subsystem and by CardBus services.1895 * Returns 0 on success and negative if unknown type of device (not normal,1896 * bridge or CardBus).1897 */1898int pci_setup_device(struct pci_dev *dev)1899{1900 u32 class;1901 u16 cmd;1902 u8 hdr_type;1903 int err, pos = 0;1904 struct pci_bus_region region;1905 struct resource *res;1906 1907 hdr_type = pci_hdr_type(dev);1908 1909 dev->sysdata = dev->bus->sysdata;1910 dev->dev.parent = dev->bus->bridge;1911 dev->dev.bus = &pci_bus_type;1912 dev->hdr_type = hdr_type & 0x7f;1913 dev->multifunction = !!(hdr_type & 0x80);1914 dev->error_state = pci_channel_io_normal;1915 set_pcie_port_type(dev);1916 1917 err = pci_set_of_node(dev);1918 if (err)1919 return err;1920 pci_set_acpi_fwnode(dev);1921 1922 pci_dev_assign_slot(dev);1923 1924 /*1925 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)1926 * set this higher, assuming the system even supports it.1927 */1928 dev->dma_mask = 0xffffffff;1929 1930 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),1931 dev->bus->number, PCI_SLOT(dev->devfn),1932 PCI_FUNC(dev->devfn));1933 1934 class = pci_class(dev);1935 1936 dev->revision = class & 0xff;1937 dev->class = class >> 8; /* upper 3 bytes */1938 1939 if (pci_early_dump)1940 early_dump_pci_device(dev);1941 1942 /* Need to have dev->class ready */1943 dev->cfg_size = pci_cfg_space_size(dev);1944 1945 /* Need to have dev->cfg_size ready */1946 set_pcie_thunderbolt(dev);1947 1948 set_pcie_untrusted(dev);1949 1950 /* "Unknown power state" */1951 dev->current_state = PCI_UNKNOWN;1952 1953 /* Early fixups, before probing the BARs */1954 pci_fixup_device(pci_fixup_early, dev);1955 1956 pci_set_removable(dev);1957 1958 pci_info(dev, "[%04x:%04x] type %02x class %#08x %s\n",1959 dev->vendor, dev->device, dev->hdr_type, dev->class,1960 pci_type_str(dev));1961 1962 /* Device class may be changed after fixup */1963 class = dev->class >> 8;1964 1965 if (dev->non_compliant_bars && !dev->mmio_always_on) {1966 pci_read_config_word(dev, PCI_COMMAND, &cmd);1967 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {1968 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");1969 cmd &= ~PCI_COMMAND_IO;1970 cmd &= ~PCI_COMMAND_MEMORY;1971 pci_write_config_word(dev, PCI_COMMAND, cmd);1972 }1973 }1974 1975 dev->broken_intx_masking = pci_intx_mask_broken(dev);1976 1977 switch (dev->hdr_type) { /* header type */1978 case PCI_HEADER_TYPE_NORMAL: /* standard header */1979 if (class == PCI_CLASS_BRIDGE_PCI)1980 goto bad;1981 pci_read_irq(dev);1982 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);1983 1984 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device);1985 1986 /*1987 * Do the ugly legacy mode stuff here rather than broken chip1988 * quirk code. Legacy mode ATA controllers have fixed1989 * addresses. These are not always echoed in BAR0-3, and1990 * BAR0-3 in a few cases contain junk!1991 */1992 if (class == PCI_CLASS_STORAGE_IDE) {1993 u8 progif;1994 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);1995 if ((progif & 1) == 0) {1996 region.start = 0x1F0;1997 region.end = 0x1F7;1998 res = &dev->resource[0];1999 res->flags = LEGACY_IO_RESOURCE;2000 pcibios_bus_to_resource(dev->bus, res, ®ion);2001 pci_info(dev, "BAR 0 %pR: legacy IDE quirk\n",2002 res);2003 region.start = 0x3F6;2004 region.end = 0x3F6;2005 res = &dev->resource[1];2006 res->flags = LEGACY_IO_RESOURCE;2007 pcibios_bus_to_resource(dev->bus, res, ®ion);2008 pci_info(dev, "BAR 1 %pR: legacy IDE quirk\n",2009 res);2010 }2011 if ((progif & 4) == 0) {2012 region.start = 0x170;2013 region.end = 0x177;2014 res = &dev->resource[2];2015 res->flags = LEGACY_IO_RESOURCE;2016 pcibios_bus_to_resource(dev->bus, res, ®ion);2017 pci_info(dev, "BAR 2 %pR: legacy IDE quirk\n",2018 res);2019 region.start = 0x376;2020 region.end = 0x376;2021 res = &dev->resource[3];2022 res->flags = LEGACY_IO_RESOURCE;2023 pcibios_bus_to_resource(dev->bus, res, ®ion);2024 pci_info(dev, "BAR 3 %pR: legacy IDE quirk\n",2025 res);2026 }2027 }2028 break;2029 2030 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */2031 /*2032 * The PCI-to-PCI bridge spec requires that subtractive2033 * decoding (i.e. transparent) bridge must have programming2034 * interface code of 0x01.2035 */2036 pci_read_irq(dev);2037 dev->transparent = ((dev->class & 0xff) == 1);2038 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);2039 pci_read_bridge_windows(dev);2040 set_pcie_hotplug_bridge(dev);2041 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);2042 if (pos) {2043 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);2044 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);2045 }2046 break;2047 2048 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */2049 if (class != PCI_CLASS_BRIDGE_CARDBUS)2050 goto bad;2051 pci_read_irq(dev);2052 pci_read_bases(dev, 1, 0);2053 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);2054 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);2055 break;2056 2057 default: /* unknown header */2058 pci_err(dev, "unknown header type %02x, ignoring device\n",2059 dev->hdr_type);2060 pci_release_of_node(dev);2061 return -EIO;2062 2063 bad:2064 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",2065 dev->class, dev->hdr_type);2066 dev->class = PCI_CLASS_NOT_DEFINED << 8;2067 }2068 2069 /* We found a fine healthy device, go go go... */2070 return 0;2071}2072 2073static void pci_configure_mps(struct pci_dev *dev)2074{2075 struct pci_dev *bridge = pci_upstream_bridge(dev);2076 int mps, mpss, p_mps, rc;2077 2078 if (!pci_is_pcie(dev))2079 return;2080 2081 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */2082 if (dev->is_virtfn)2083 return;2084 2085 /*2086 * For Root Complex Integrated Endpoints, program the maximum2087 * supported value unless limited by the PCIE_BUS_PEER2PEER case.2088 */2089 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {2090 if (pcie_bus_config == PCIE_BUS_PEER2PEER)2091 mps = 128;2092 else2093 mps = 128 << dev->pcie_mpss;2094 rc = pcie_set_mps(dev, mps);2095 if (rc) {2096 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",2097 mps);2098 }2099 return;2100 }2101 2102 if (!bridge || !pci_is_pcie(bridge))2103 return;2104 2105 mps = pcie_get_mps(dev);2106 p_mps = pcie_get_mps(bridge);2107 2108 if (mps == p_mps)2109 return;2110 2111 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {2112 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",2113 mps, pci_name(bridge), p_mps);2114 return;2115 }2116 2117 /*2118 * Fancier MPS configuration is done later by2119 * pcie_bus_configure_settings()2120 */2121 if (pcie_bus_config != PCIE_BUS_DEFAULT)2122 return;2123 2124 mpss = 128 << dev->pcie_mpss;2125 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {2126 pcie_set_mps(bridge, mpss);2127 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",2128 mpss, p_mps, 128 << bridge->pcie_mpss);2129 p_mps = pcie_get_mps(bridge);2130 }2131 2132 rc = pcie_set_mps(dev, p_mps);2133 if (rc) {2134 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",2135 p_mps);2136 return;2137 }2138 2139 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",2140 p_mps, mps, mpss);2141}2142 2143int pci_configure_extended_tags(struct pci_dev *dev, void *ign)2144{2145 struct pci_host_bridge *host;2146 u32 cap;2147 u16 ctl;2148 int ret;2149 2150 if (!pci_is_pcie(dev))2151 return 0;2152 2153 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);2154 if (ret)2155 return 0;2156 2157 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))2158 return 0;2159 2160 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);2161 if (ret)2162 return 0;2163 2164 host = pci_find_host_bridge(dev->bus);2165 if (!host)2166 return 0;2167 2168 /*2169 * If some device in the hierarchy doesn't handle Extended Tags2170 * correctly, make sure they're disabled.2171 */2172 if (host->no_ext_tags) {2173 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {2174 pci_info(dev, "disabling Extended Tags\n");2175 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,2176 PCI_EXP_DEVCTL_EXT_TAG);2177 }2178 return 0;2179 }2180 2181 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {2182 pci_info(dev, "enabling Extended Tags\n");2183 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,2184 PCI_EXP_DEVCTL_EXT_TAG);2185 }2186 return 0;2187}2188 2189/**2190 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable2191 * @dev: PCI device to query2192 *2193 * Returns true if the device has enabled relaxed ordering attribute.2194 */2195bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)2196{2197 u16 v;2198 2199 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);2200 2201 return !!(v & PCI_EXP_DEVCTL_RELAX_EN);2202}2203EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);2204 2205static void pci_configure_relaxed_ordering(struct pci_dev *dev)2206{2207 struct pci_dev *root;2208 2209 /* PCI_EXP_DEVCTL_RELAX_EN is RsvdP in VFs */2210 if (dev->is_virtfn)2211 return;2212 2213 if (!pcie_relaxed_ordering_enabled(dev))2214 return;2215 2216 /*2217 * For now, we only deal with Relaxed Ordering issues with Root2218 * Ports. Peer-to-Peer DMA is another can of worms.2219 */2220 root = pcie_find_root_port(dev);2221 if (!root)2222 return;2223 2224 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {2225 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,2226 PCI_EXP_DEVCTL_RELAX_EN);2227 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");2228 }2229}2230 2231static void pci_configure_eetlp_prefix(struct pci_dev *dev)2232{2233#ifdef CONFIG_PCI_PASID2234 struct pci_dev *bridge;2235 int pcie_type;2236 u32 cap;2237 2238 if (!pci_is_pcie(dev))2239 return;2240 2241 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);2242 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))2243 return;2244 2245 pcie_type = pci_pcie_type(dev);2246 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||2247 pcie_type == PCI_EXP_TYPE_RC_END)2248 dev->eetlp_prefix_path = 1;2249 else {2250 bridge = pci_upstream_bridge(dev);2251 if (bridge && bridge->eetlp_prefix_path)2252 dev->eetlp_prefix_path = 1;2253 }2254#endif2255}2256 2257static void pci_configure_serr(struct pci_dev *dev)2258{2259 u16 control;2260 2261 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {2262 2263 /*2264 * A bridge will not forward ERR_ messages coming from an2265 * endpoint unless SERR# forwarding is enabled.2266 */2267 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control);2268 if (!(control & PCI_BRIDGE_CTL_SERR)) {2269 control |= PCI_BRIDGE_CTL_SERR;2270 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control);2271 }2272 }2273}2274 2275static void pci_configure_device(struct pci_dev *dev)2276{2277 pci_configure_mps(dev);2278 pci_configure_extended_tags(dev, NULL);2279 pci_configure_relaxed_ordering(dev);2280 pci_configure_ltr(dev);2281 pci_configure_aspm_l1ss(dev);2282 pci_configure_eetlp_prefix(dev);2283 pci_configure_serr(dev);2284 2285 pci_acpi_program_hp_params(dev);2286}2287 2288static void pci_release_capabilities(struct pci_dev *dev)2289{2290 pci_aer_exit(dev);2291 pci_rcec_exit(dev);2292 pci_iov_release(dev);2293 pci_free_cap_save_buffers(dev);2294}2295 2296/**2297 * pci_release_dev - Free a PCI device structure when all users of it are2298 * finished2299 * @dev: device that's been disconnected2300 *2301 * Will be called only by the device core when all users of this PCI device are2302 * done.2303 */2304static void pci_release_dev(struct device *dev)2305{2306 struct pci_dev *pci_dev;2307 2308 pci_dev = to_pci_dev(dev);2309 pci_release_capabilities(pci_dev);2310 pci_release_of_node(pci_dev);2311 pcibios_release_device(pci_dev);2312 pci_bus_put(pci_dev->bus);2313 kfree(pci_dev->driver_override);2314 bitmap_free(pci_dev->dma_alias_mask);2315 dev_dbg(dev, "device released\n");2316 kfree(pci_dev);2317}2318 2319static const struct device_type pci_dev_type = {2320 .groups = pci_dev_attr_groups,2321};2322 2323struct pci_dev *pci_alloc_dev(struct pci_bus *bus)2324{2325 struct pci_dev *dev;2326 2327 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);2328 if (!dev)2329 return NULL;2330 2331 INIT_LIST_HEAD(&dev->bus_list);2332 dev->dev.type = &pci_dev_type;2333 dev->bus = pci_bus_get(bus);2334 dev->driver_exclusive_resource = (struct resource) {2335 .name = "PCI Exclusive",2336 .start = 0,2337 .end = -1,2338 };2339 2340 spin_lock_init(&dev->pcie_cap_lock);2341#ifdef CONFIG_PCI_MSI2342 raw_spin_lock_init(&dev->msi_lock);2343#endif2344 return dev;2345}2346EXPORT_SYMBOL(pci_alloc_dev);2347 2348static bool pci_bus_wait_rrs(struct pci_bus *bus, int devfn, u32 *l,2349 int timeout)2350{2351 int delay = 1;2352 2353 if (!pci_bus_rrs_vendor_id(*l))2354 return true; /* not a Configuration RRS completion */2355 2356 if (!timeout)2357 return false; /* RRS, but caller doesn't want to wait */2358 2359 /*2360 * We got the reserved Vendor ID that indicates a completion with2361 * Configuration Request Retry Status (RRS). Retry until we get a2362 * valid Vendor ID or we time out.2363 */2364 while (pci_bus_rrs_vendor_id(*l)) {2365 if (delay > timeout) {2366 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",2367 pci_domain_nr(bus), bus->number,2368 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);2369 2370 return false;2371 }2372 if (delay >= 1000)2373 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",2374 pci_domain_nr(bus), bus->number,2375 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);2376 2377 msleep(delay);2378 delay *= 2;2379 2380 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))2381 return false;2382 }2383 2384 if (delay >= 1000)2385 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",2386 pci_domain_nr(bus), bus->number,2387 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);2388 2389 return true;2390}2391 2392bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,2393 int timeout)2394{2395 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))2396 return false;2397 2398 /* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */2399 if (PCI_POSSIBLE_ERROR(*l) || *l == 0x00000000 ||2400 *l == 0x0000ffff || *l == 0xffff0000)2401 return false;2402 2403 if (pci_bus_rrs_vendor_id(*l))2404 return pci_bus_wait_rrs(bus, devfn, l, timeout);2405 2406 return true;2407}2408 2409bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,2410 int timeout)2411{2412#ifdef CONFIG_PCI_QUIRKS2413 struct pci_dev *bridge = bus->self;2414 2415 /*2416 * Certain IDT switches have an issue where they improperly trigger2417 * ACS Source Validation errors on completions for config reads.2418 */2419 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT &&2420 bridge->device == 0x80b5)2421 return pci_idt_bus_quirk(bus, devfn, l, timeout);2422#endif2423 2424 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);2425}2426EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);2427 2428/*2429 * Read the config data for a PCI device, sanity-check it,2430 * and fill in the dev structure.2431 */2432static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)2433{2434 struct pci_dev *dev;2435 u32 l;2436 2437 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))2438 return NULL;2439 2440 dev = pci_alloc_dev(bus);2441 if (!dev)2442 return NULL;2443 2444 dev->devfn = devfn;2445 dev->vendor = l & 0xffff;2446 dev->device = (l >> 16) & 0xffff;2447 2448 if (pci_setup_device(dev)) {2449 pci_bus_put(dev->bus);2450 kfree(dev);2451 return NULL;2452 }2453 2454 return dev;2455}2456 2457void pcie_report_downtraining(struct pci_dev *dev)2458{2459 if (!pci_is_pcie(dev))2460 return;2461 2462 /* Look from the device up to avoid downstream ports with no devices */2463 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) &&2464 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) &&2465 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM))2466 return;2467 2468 /* Multi-function PCIe devices share the same link/status */2469 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn)2470 return;2471 2472 /* Print link status only if the device is constrained by the fabric */2473 __pcie_print_link_status(dev, false);2474}2475 2476static void pci_init_capabilities(struct pci_dev *dev)2477{2478 pci_ea_init(dev); /* Enhanced Allocation */2479 pci_msi_init(dev); /* Disable MSI */2480 pci_msix_init(dev); /* Disable MSI-X */2481 2482 /* Buffers for saving PCIe and PCI-X capabilities */2483 pci_allocate_cap_save_buffers(dev);2484 2485 pci_pm_init(dev); /* Power Management */2486 pci_vpd_init(dev); /* Vital Product Data */2487 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */2488 pci_iov_init(dev); /* Single Root I/O Virtualization */2489 pci_ats_init(dev); /* Address Translation Services */2490 pci_pri_init(dev); /* Page Request Interface */2491 pci_pasid_init(dev); /* Process Address Space ID */2492 pci_acs_init(dev); /* Access Control Services */2493 pci_ptm_init(dev); /* Precision Time Measurement */2494 pci_aer_init(dev); /* Advanced Error Reporting */2495 pci_dpc_init(dev); /* Downstream Port Containment */2496 pci_rcec_init(dev); /* Root Complex Event Collector */2497 pci_doe_init(dev); /* Data Object Exchange */2498 2499 pcie_report_downtraining(dev);2500 pci_init_reset_methods(dev);2501}2502 2503/*2504 * This is the equivalent of pci_host_bridge_msi_domain() that acts on2505 * devices. Firmware interfaces that can select the MSI domain on a2506 * per-device basis should be called from here.2507 */2508static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)2509{2510 struct irq_domain *d;2511 2512 /*2513 * If a domain has been set through the pcibios_device_add()2514 * callback, then this is the one (platform code knows best).2515 */2516 d = dev_get_msi_domain(&dev->dev);2517 if (d)2518 return d;2519 2520 /*2521 * Let's see if we have a firmware interface able to provide2522 * the domain.2523 */2524 d = pci_msi_get_device_domain(dev);2525 if (d)2526 return d;2527 2528 return NULL;2529}2530 2531static void pci_set_msi_domain(struct pci_dev *dev)2532{2533 struct irq_domain *d;2534 2535 /*2536 * If the platform or firmware interfaces cannot supply a2537 * device-specific MSI domain, then inherit the default domain2538 * from the host bridge itself.2539 */2540 d = pci_dev_msi_domain(dev);2541 if (!d)2542 d = dev_get_msi_domain(&dev->bus->dev);2543 2544 dev_set_msi_domain(&dev->dev, d);2545}2546 2547void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)2548{2549 int ret;2550 2551 pci_configure_device(dev);2552 2553 device_initialize(&dev->dev);2554 dev->dev.release = pci_release_dev;2555 2556 set_dev_node(&dev->dev, pcibus_to_node(bus));2557 dev->dev.dma_mask = &dev->dma_mask;2558 dev->dev.dma_parms = &dev->dma_parms;2559 dev->dev.coherent_dma_mask = 0xffffffffull;2560 2561 dma_set_max_seg_size(&dev->dev, 65536);2562 dma_set_seg_boundary(&dev->dev, 0xffffffff);2563 2564 pcie_failed_link_retrain(dev);2565 2566 /* Fix up broken headers */2567 pci_fixup_device(pci_fixup_header, dev);2568 2569 pci_reassigndev_resource_alignment(dev);2570 2571 dev->state_saved = false;2572 2573 pci_init_capabilities(dev);2574 2575 /*2576 * Add the device to our list of discovered devices2577 * and the bus list for fixup functions, etc.2578 */2579 down_write(&pci_bus_sem);2580 list_add_tail(&dev->bus_list, &bus->devices);2581 up_write(&pci_bus_sem);2582 2583 ret = pcibios_device_add(dev);2584 WARN_ON(ret < 0);2585 2586 /* Set up MSI IRQ domain */2587 pci_set_msi_domain(dev);2588 2589 /* Notifier could use PCI capabilities */2590 dev->match_driver = false;2591 ret = device_add(&dev->dev);2592 WARN_ON(ret < 0);2593 2594 pci_npem_create(dev);2595}2596 2597struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)2598{2599 struct pci_dev *dev;2600 2601 dev = pci_get_slot(bus, devfn);2602 if (dev) {2603 pci_dev_put(dev);2604 return dev;2605 }2606 2607 dev = pci_scan_device(bus, devfn);2608 if (!dev)2609 return NULL;2610 2611 pci_device_add(dev, bus);2612 2613 return dev;2614}2615EXPORT_SYMBOL(pci_scan_single_device);2616 2617static int next_ari_fn(struct pci_bus *bus, struct pci_dev *dev, int fn)2618{2619 int pos;2620 u16 cap = 0;2621 unsigned int next_fn;2622 2623 if (!dev)2624 return -ENODEV;2625 2626 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);2627 if (!pos)2628 return -ENODEV;2629 2630 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);2631 next_fn = PCI_ARI_CAP_NFN(cap);2632 if (next_fn <= fn)2633 return -ENODEV; /* protect against malformed list */2634 2635 return next_fn;2636}2637 2638static int next_fn(struct pci_bus *bus, struct pci_dev *dev, int fn)2639{2640 if (pci_ari_enabled(bus))2641 return next_ari_fn(bus, dev, fn);2642 2643 if (fn >= 7)2644 return -ENODEV;2645 /* only multifunction devices may have more functions */2646 if (dev && !dev->multifunction)2647 return -ENODEV;2648 2649 return fn + 1;2650}2651 2652static int only_one_child(struct pci_bus *bus)2653{2654 struct pci_dev *bridge = bus->self;2655 2656 /*2657 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so2658 * we scan for all possible devices, not just Device 0.2659 */2660 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))2661 return 0;2662 2663 /*2664 * A PCIe Downstream Port normally leads to a Link with only Device2665 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan2666 * only for Device 0 in that situation.2667 */2668 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge))2669 return 1;2670 2671 return 0;2672}2673 2674/**2675 * pci_scan_slot - Scan a PCI slot on a bus for devices2676 * @bus: PCI bus to scan2677 * @devfn: slot number to scan (must have zero function)2678 *2679 * Scan a PCI slot on the specified PCI bus for devices, adding2680 * discovered devices to the @bus->devices list. New devices2681 * will not have is_added set.2682 *2683 * Returns the number of new devices found.2684 */2685int pci_scan_slot(struct pci_bus *bus, int devfn)2686{2687 struct pci_dev *dev;2688 int fn = 0, nr = 0;2689 2690 if (only_one_child(bus) && (devfn > 0))2691 return 0; /* Already scanned the entire slot */2692 2693 do {2694 dev = pci_scan_single_device(bus, devfn + fn);2695 if (dev) {2696 if (!pci_dev_is_added(dev))2697 nr++;2698 if (fn > 0)2699 dev->multifunction = 1;2700 } else if (fn == 0) {2701 /*2702 * Function 0 is required unless we are running on2703 * a hypervisor that passes through individual PCI2704 * functions.2705 */2706 if (!hypervisor_isolated_pci_functions())2707 break;2708 }2709 fn = next_fn(bus, dev, fn);2710 } while (fn >= 0);2711 2712 /* Only one slot has PCIe device */2713 if (bus->self && nr)2714 pcie_aspm_init_link_state(bus->self);2715 2716 return nr;2717}2718EXPORT_SYMBOL(pci_scan_slot);2719 2720static int pcie_find_smpss(struct pci_dev *dev, void *data)2721{2722 u8 *smpss = data;2723 2724 if (!pci_is_pcie(dev))2725 return 0;2726 2727 /*2728 * We don't have a way to change MPS settings on devices that have2729 * drivers attached. A hot-added device might support only the minimum2730 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge2731 * where devices may be hot-added, we limit the fabric MPS to 128 so2732 * hot-added devices will work correctly.2733 *2734 * However, if we hot-add a device to a slot directly below a Root2735 * Port, it's impossible for there to be other existing devices below2736 * the port. We don't limit the MPS in this case because we can2737 * reconfigure MPS on both the Root Port and the hot-added device,2738 * and there are no other devices involved.2739 *2740 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.2741 */2742 if (dev->is_hotplug_bridge &&2743 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)2744 *smpss = 0;2745 2746 if (*smpss > dev->pcie_mpss)2747 *smpss = dev->pcie_mpss;2748 2749 return 0;2750}2751 2752static void pcie_write_mps(struct pci_dev *dev, int mps)2753{2754 int rc;2755 2756 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {2757 mps = 128 << dev->pcie_mpss;2758 2759 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&2760 dev->bus->self)2761 2762 /*2763 * For "Performance", the assumption is made that2764 * downstream communication will never be larger than2765 * the MRRS. So, the MPS only needs to be configured2766 * for the upstream communication. This being the case,2767 * walk from the top down and set the MPS of the child2768 * to that of the parent bus.2769 *2770 * Configure the device MPS with the smaller of the2771 * device MPSS or the bridge MPS (which is assumed to be2772 * properly configured at this point to the largest2773 * allowable MPS based on its parent bus).2774 */2775 mps = min(mps, pcie_get_mps(dev->bus->self));2776 }2777 2778 rc = pcie_set_mps(dev, mps);2779 if (rc)2780 pci_err(dev, "Failed attempting to set the MPS\n");2781}2782 2783static void pcie_write_mrrs(struct pci_dev *dev)2784{2785 int rc, mrrs;2786 2787 /*2788 * In the "safe" case, do not configure the MRRS. There appear to be2789 * issues with setting MRRS to 0 on a number of devices.2790 */2791 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)2792 return;2793 2794 /*2795 * For max performance, the MRRS must be set to the largest supported2796 * value. However, it cannot be configured larger than the MPS the2797 * device or the bus can support. This should already be properly2798 * configured by a prior call to pcie_write_mps().2799 */2800 mrrs = pcie_get_mps(dev);2801 2802 /*2803 * MRRS is a R/W register. Invalid values can be written, but a2804 * subsequent read will verify if the value is acceptable or not.2805 * If the MRRS value provided is not acceptable (e.g., too large),2806 * shrink the value until it is acceptable to the HW.2807 */2808 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {2809 rc = pcie_set_readrq(dev, mrrs);2810 if (!rc)2811 break;2812 2813 pci_warn(dev, "Failed attempting to set the MRRS\n");2814 mrrs /= 2;2815 }2816 2817 if (mrrs < 128)2818 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");2819}2820 2821static int pcie_bus_configure_set(struct pci_dev *dev, void *data)2822{2823 int mps, orig_mps;2824 2825 if (!pci_is_pcie(dev))2826 return 0;2827 2828 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||2829 pcie_bus_config == PCIE_BUS_DEFAULT)2830 return 0;2831 2832 mps = 128 << *(u8 *)data;2833 orig_mps = pcie_get_mps(dev);2834 2835 pcie_write_mps(dev, mps);2836 pcie_write_mrrs(dev);2837 2838 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",2839 pcie_get_mps(dev), 128 << dev->pcie_mpss,2840 orig_mps, pcie_get_readrq(dev));2841 2842 return 0;2843}2844 2845/*2846 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,2847 * parents then children fashion. If this changes, then this code will not2848 * work as designed.2849 */2850void pcie_bus_configure_settings(struct pci_bus *bus)2851{2852 u8 smpss = 0;2853 2854 if (!bus->self)2855 return;2856 2857 if (!pci_is_pcie(bus->self))2858 return;2859 2860 /*2861 * FIXME - Peer to peer DMA is possible, though the endpoint would need2862 * to be aware of the MPS of the destination. To work around this,2863 * simply force the MPS of the entire system to the smallest possible.2864 */2865 if (pcie_bus_config == PCIE_BUS_PEER2PEER)2866 smpss = 0;2867 2868 if (pcie_bus_config == PCIE_BUS_SAFE) {2869 smpss = bus->self->pcie_mpss;2870 2871 pcie_find_smpss(bus->self, &smpss);2872 pci_walk_bus(bus, pcie_find_smpss, &smpss);2873 }2874 2875 pcie_bus_configure_set(bus->self, &smpss);2876 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);2877}2878EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);2879 2880/*2881 * Called after each bus is probed, but before its children are examined. This2882 * is marked as __weak because multiple architectures define it.2883 */2884void __weak pcibios_fixup_bus(struct pci_bus *bus)2885{2886 /* nothing to do, expected to be removed in the future */2887}2888 2889/**2890 * pci_scan_child_bus_extend() - Scan devices below a bus2891 * @bus: Bus to scan for devices2892 * @available_buses: Total number of buses available (%0 does not try to2893 * extend beyond the minimal)2894 *2895 * Scans devices below @bus including subordinate buses. Returns new2896 * subordinate number including all the found devices. Passing2897 * @available_buses causes the remaining bus space to be distributed2898 * equally between hotplug-capable bridges to allow future extension of the2899 * hierarchy.2900 */2901static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,2902 unsigned int available_buses)2903{2904 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;2905 unsigned int start = bus->busn_res.start;2906 unsigned int devfn, cmax, max = start;2907 struct pci_dev *dev;2908 2909 dev_dbg(&bus->dev, "scanning bus\n");2910 2911 /* Go find them, Rover! */2912 for (devfn = 0; devfn < 256; devfn += 8)2913 pci_scan_slot(bus, devfn);2914 2915 /* Reserve buses for SR-IOV capability */2916 used_buses = pci_iov_bus_range(bus);2917 max += used_buses;2918 2919 /*2920 * After performing arch-dependent fixup of the bus, look behind2921 * all PCI-to-PCI bridges on this bus.2922 */2923 if (!bus->is_added) {2924 dev_dbg(&bus->dev, "fixups for bus\n");2925 pcibios_fixup_bus(bus);2926 bus->is_added = 1;2927 }2928 2929 /*2930 * Calculate how many hotplug bridges and normal bridges there2931 * are on this bus. We will distribute the additional available2932 * buses between hotplug bridges.2933 */2934 for_each_pci_bridge(dev, bus) {2935 if (dev->is_hotplug_bridge)2936 hotplug_bridges++;2937 else2938 normal_bridges++;2939 }2940 2941 /*2942 * Scan bridges that are already configured. We don't touch them2943 * unless they are misconfigured (which will be done in the second2944 * scan below).2945 */2946 for_each_pci_bridge(dev, bus) {2947 cmax = max;2948 max = pci_scan_bridge_extend(bus, dev, max, 0, 0);2949 2950 /*2951 * Reserve one bus for each bridge now to avoid extending2952 * hotplug bridges too much during the second scan below.2953 */2954 used_buses++;2955 if (max - cmax > 1)2956 used_buses += max - cmax - 1;2957 }2958 2959 /* Scan bridges that need to be reconfigured */2960 for_each_pci_bridge(dev, bus) {2961 unsigned int buses = 0;2962 2963 if (!hotplug_bridges && normal_bridges == 1) {2964 /*2965 * There is only one bridge on the bus (upstream2966 * port) so it gets all available buses which it2967 * can then distribute to the possible hotplug2968 * bridges below.2969 */2970 buses = available_buses;2971 } else if (dev->is_hotplug_bridge) {2972 /*2973 * Distribute the extra buses between hotplug2974 * bridges if any.2975 */2976 buses = available_buses / hotplug_bridges;2977 buses = min(buses, available_buses - used_buses + 1);2978 }2979 2980 cmax = max;2981 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1);2982 /* One bus is already accounted so don't add it again */2983 if (max - cmax > 1)2984 used_buses += max - cmax - 1;2985 }2986 2987 /*2988 * Make sure a hotplug bridge has at least the minimum requested2989 * number of buses but allow it to grow up to the maximum available2990 * bus number if there is room.2991 */2992 if (bus->self && bus->self->is_hotplug_bridge) {2993 used_buses = max_t(unsigned int, available_buses,2994 pci_hotplug_bus_size - 1);2995 if (max - start < used_buses) {2996 max = start + used_buses;2997 2998 /* Do not allocate more buses than we have room left */2999 if (max > bus->busn_res.end)3000 max = bus->busn_res.end;3001 3002 dev_dbg(&bus->dev, "%pR extended by %#02x\n",3003 &bus->busn_res, max - start);3004 }3005 }3006 3007 /*3008 * We've scanned the bus and so we know all about what's on3009 * the other side of any bridges that may be on this bus plus3010 * any devices.3011 *3012 * Return how far we've got finding sub-buses.3013 */3014 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);3015 return max;3016}3017 3018/**3019 * pci_scan_child_bus() - Scan devices below a bus3020 * @bus: Bus to scan for devices3021 *3022 * Scans devices below @bus including subordinate buses. Returns new3023 * subordinate number including all the found devices.3024 */3025unsigned int pci_scan_child_bus(struct pci_bus *bus)3026{3027 return pci_scan_child_bus_extend(bus, 0);3028}3029EXPORT_SYMBOL_GPL(pci_scan_child_bus);3030 3031/**3032 * pcibios_root_bridge_prepare - Platform-specific host bridge setup3033 * @bridge: Host bridge to set up3034 *3035 * Default empty implementation. Replace with an architecture-specific setup3036 * routine, if necessary.3037 */3038int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)3039{3040 return 0;3041}3042 3043void __weak pcibios_add_bus(struct pci_bus *bus)3044{3045}3046 3047void __weak pcibios_remove_bus(struct pci_bus *bus)3048{3049}3050 3051struct pci_bus *pci_create_root_bus(struct device *parent, int bus,3052 struct pci_ops *ops, void *sysdata, struct list_head *resources)3053{3054 int error;3055 struct pci_host_bridge *bridge;3056 3057 bridge = pci_alloc_host_bridge(0);3058 if (!bridge)3059 return NULL;3060 3061 bridge->dev.parent = parent;3062 3063 list_splice_init(resources, &bridge->windows);3064 bridge->sysdata = sysdata;3065 bridge->busnr = bus;3066 bridge->ops = ops;3067 3068 error = pci_register_host_bridge(bridge);3069 if (error < 0)3070 goto err_out;3071 3072 return bridge->bus;3073 3074err_out:3075 put_device(&bridge->dev);3076 return NULL;3077}3078EXPORT_SYMBOL_GPL(pci_create_root_bus);3079 3080int pci_host_probe(struct pci_host_bridge *bridge)3081{3082 struct pci_bus *bus, *child;3083 int ret;3084 3085 pci_lock_rescan_remove();3086 ret = pci_scan_root_bus_bridge(bridge);3087 pci_unlock_rescan_remove();3088 if (ret < 0) {3089 dev_err(bridge->dev.parent, "Scanning root bridge failed");3090 return ret;3091 }3092 3093 bus = bridge->bus;3094 3095 /* If we must preserve the resource configuration, claim now */3096 if (bridge->preserve_config)3097 pci_bus_claim_resources(bus);3098 3099 /*3100 * Assign whatever was left unassigned. If we didn't claim above,3101 * this will reassign everything.3102 */3103 pci_assign_unassigned_root_bus_resources(bus);3104 3105 list_for_each_entry(child, &bus->children, node)3106 pcie_bus_configure_settings(child);3107 3108 pci_lock_rescan_remove();3109 pci_bus_add_devices(bus);3110 pci_unlock_rescan_remove();3111 return 0;3112}3113EXPORT_SYMBOL_GPL(pci_host_probe);3114 3115int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)3116{3117 struct resource *res = &b->busn_res;3118 struct resource *parent_res, *conflict;3119 3120 res->start = bus;3121 res->end = bus_max;3122 res->flags = IORESOURCE_BUS;3123 3124 if (!pci_is_root_bus(b))3125 parent_res = &b->parent->busn_res;3126 else {3127 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));3128 res->flags |= IORESOURCE_PCI_FIXED;3129 }3130 3131 conflict = request_resource_conflict(parent_res, res);3132 3133 if (conflict)3134 dev_info(&b->dev,3135 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",3136 res, pci_is_root_bus(b) ? "domain " : "",3137 parent_res, conflict->name, conflict);3138 3139 return conflict == NULL;3140}3141 3142int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)3143{3144 struct resource *res = &b->busn_res;3145 struct resource old_res = *res;3146 resource_size_t size;3147 int ret;3148 3149 if (res->start > bus_max)3150 return -EINVAL;3151 3152 size = bus_max - res->start + 1;3153 ret = adjust_resource(res, res->start, size);3154 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n",3155 &old_res, ret ? "can not be" : "is", bus_max);3156 3157 if (!ret && !res->parent)3158 pci_bus_insert_busn_res(b, res->start, res->end);3159 3160 return ret;3161}3162 3163void pci_bus_release_busn_res(struct pci_bus *b)3164{3165 struct resource *res = &b->busn_res;3166 int ret;3167 3168 if (!res->flags || !res->parent)3169 return;3170 3171 ret = release_resource(res);3172 dev_info(&b->dev, "busn_res: %pR %s released\n",3173 res, ret ? "can not be" : "is");3174}3175 3176int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)3177{3178 struct resource_entry *window;3179 bool found = false;3180 struct pci_bus *b;3181 int max, bus, ret;3182 3183 if (!bridge)3184 return -EINVAL;3185 3186 resource_list_for_each_entry(window, &bridge->windows)3187 if (window->res->flags & IORESOURCE_BUS) {3188 bridge->busnr = window->res->start;3189 found = true;3190 break;3191 }3192 3193 ret = pci_register_host_bridge(bridge);3194 if (ret < 0)3195 return ret;3196 3197 b = bridge->bus;3198 bus = bridge->busnr;3199 3200 if (!found) {3201 dev_info(&b->dev,3202 "No busn resource found for root bus, will use [bus %02x-ff]\n",3203 bus);3204 pci_bus_insert_busn_res(b, bus, 255);3205 }3206 3207 max = pci_scan_child_bus(b);3208 3209 if (!found)3210 pci_bus_update_busn_res_end(b, max);3211 3212 return 0;3213}3214EXPORT_SYMBOL(pci_scan_root_bus_bridge);3215 3216struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,3217 struct pci_ops *ops, void *sysdata, struct list_head *resources)3218{3219 struct resource_entry *window;3220 bool found = false;3221 struct pci_bus *b;3222 int max;3223 3224 resource_list_for_each_entry(window, resources)3225 if (window->res->flags & IORESOURCE_BUS) {3226 found = true;3227 break;3228 }3229 3230 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);3231 if (!b)3232 return NULL;3233 3234 if (!found) {3235 dev_info(&b->dev,3236 "No busn resource found for root bus, will use [bus %02x-ff]\n",3237 bus);3238 pci_bus_insert_busn_res(b, bus, 255);3239 }3240 3241 max = pci_scan_child_bus(b);3242 3243 if (!found)3244 pci_bus_update_busn_res_end(b, max);3245 3246 return b;3247}3248EXPORT_SYMBOL(pci_scan_root_bus);3249 3250struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,3251 void *sysdata)3252{3253 LIST_HEAD(resources);3254 struct pci_bus *b;3255 3256 pci_add_resource(&resources, &ioport_resource);3257 pci_add_resource(&resources, &iomem_resource);3258 pci_add_resource(&resources, &busn_resource);3259 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);3260 if (b) {3261 pci_scan_child_bus(b);3262 } else {3263 pci_free_resource_list(&resources);3264 }3265 return b;3266}3267EXPORT_SYMBOL(pci_scan_bus);3268 3269/**3270 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices3271 * @bridge: PCI bridge for the bus to scan3272 *3273 * Scan a PCI bus and child buses for new devices, add them,3274 * and enable them, resizing bridge mmio/io resource if necessary3275 * and possible. The caller must ensure the child devices are already3276 * removed for resizing to occur.3277 *3278 * Returns the max number of subordinate bus discovered.3279 */3280unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)3281{3282 unsigned int max;3283 struct pci_bus *bus = bridge->subordinate;3284 3285 max = pci_scan_child_bus(bus);3286 3287 pci_assign_unassigned_bridge_resources(bridge);3288 3289 pci_bus_add_devices(bus);3290 3291 return max;3292}3293 3294/**3295 * pci_rescan_bus - Scan a PCI bus for devices3296 * @bus: PCI bus to scan3297 *3298 * Scan a PCI bus and child buses for new devices, add them,3299 * and enable them.3300 *3301 * Returns the max number of subordinate bus discovered.3302 */3303unsigned int pci_rescan_bus(struct pci_bus *bus)3304{3305 unsigned int max;3306 3307 max = pci_scan_child_bus(bus);3308 pci_assign_unassigned_bus_resources(bus);3309 pci_bus_add_devices(bus);3310 3311 return max;3312}3313EXPORT_SYMBOL_GPL(pci_rescan_bus);3314 3315/*3316 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal3317 * routines should always be executed under this mutex.3318 */3319static DEFINE_MUTEX(pci_rescan_remove_lock);3320 3321void pci_lock_rescan_remove(void)3322{3323 mutex_lock(&pci_rescan_remove_lock);3324}3325EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);3326 3327void pci_unlock_rescan_remove(void)3328{3329 mutex_unlock(&pci_rescan_remove_lock);3330}3331EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);3332 3333static int __init pci_sort_bf_cmp(const struct device *d_a,3334 const struct device *d_b)3335{3336 const struct pci_dev *a = to_pci_dev(d_a);3337 const struct pci_dev *b = to_pci_dev(d_b);3338 3339 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;3340 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;3341 3342 if (a->bus->number < b->bus->number) return -1;3343 else if (a->bus->number > b->bus->number) return 1;3344 3345 if (a->devfn < b->devfn) return -1;3346 else if (a->devfn > b->devfn) return 1;3347 3348 return 0;3349}3350 3351void __init pci_sort_breadthfirst(void)3352{3353 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);3354}3355 3356int pci_hp_add_bridge(struct pci_dev *dev)3357{3358 struct pci_bus *parent = dev->bus;3359 int busnr, start = parent->busn_res.start;3360 unsigned int available_buses = 0;3361 int end = parent->busn_res.end;3362 3363 for (busnr = start; busnr <= end; busnr++) {3364 if (!pci_find_bus(pci_domain_nr(parent), busnr))3365 break;3366 }3367 if (busnr-- > end) {3368 pci_err(dev, "No bus number available for hot-added bridge\n");3369 return -1;3370 }3371 3372 /* Scan bridges that are already configured */3373 busnr = pci_scan_bridge(parent, dev, busnr, 0);3374 3375 /*3376 * Distribute the available bus numbers between hotplug-capable3377 * bridges to make extending the chain later possible.3378 */3379 available_buses = end - busnr;3380 3381 /* Scan bridges that need to be reconfigured */3382 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1);3383 3384 if (!dev->subordinate)3385 return -1;3386 3387 return 0;3388}3389EXPORT_SYMBOL_GPL(pci_hp_add_bridge);3390