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1/*2 * cirrus.h 1.4 1999/10/25 20:03:343 *4 * The contents of this file are subject to the Mozilla Public License5 * Version 1.1 (the "License"); you may not use this file except in6 * compliance with the License. You may obtain a copy of the License7 * at http://www.mozilla.org/MPL/8 *9 * Software distributed under the License is distributed on an "AS IS"10 * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See11 * the License for the specific language governing rights and12 * limitations under the License. 13 *14 * The initial developer of the original code is David A. Hinds15 * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds16 * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.17 *18 * Alternatively, the contents of this file may be used under the19 * terms of the GNU General Public License version 2 (the "GPL"), in which20 * case the provisions of the GPL are applicable instead of the21 * above. If you wish to allow the use of your version of this file22 * only under the terms of the GPL and not to allow others to use23 * your version of this file under the MPL, indicate your decision by24 * deleting the provisions above and replace them with the notice and25 * other provisions required by the GPL. If you do not delete the26 * provisions above, a recipient may use your version of this file27 * under either the MPL or the GPL.28 */29 30#ifndef _LINUX_CIRRUS_H31#define _LINUX_CIRRUS_H32 33#define PD67_MISC_CTL_1 0x16 /* Misc control 1 */34#define PD67_FIFO_CTL 0x17 /* FIFO control */35#define PD67_MISC_CTL_2 0x1E /* Misc control 2 */36#define PD67_CHIP_INFO 0x1f /* Chip information */37#define PD67_ATA_CTL 0x026 /* 6730: ATA control */38#define PD67_EXT_INDEX 0x2e /* Extension index */39#define PD67_EXT_DATA 0x2f /* Extension data */40 41/* PD6722 extension registers -- indexed in PD67_EXT_INDEX */42#define PD67_DATA_MASK0 0x01 /* Data mask 0 */43#define PD67_DATA_MASK1 0x02 /* Data mask 1 */44#define PD67_DMA_CTL 0x03 /* DMA control */45 46/* PD6730 extension registers -- indexed in PD67_EXT_INDEX */47#define PD67_EXT_CTL_1 0x03 /* Extension control 1 */48#define PD67_MEM_PAGE(n) ((n)+5) /* PCI window bits 31:24 */49#define PD67_EXTERN_DATA 0x0a50#define PD67_MISC_CTL_3 0x2551#define PD67_SMB_PWR_CTL 0x2652 53/* I/O window address offset */54#define PD67_IO_OFF(w) (0x36+((w)<<1))55 56/* Timing register sets */57#define PD67_TIME_SETUP(n) (0x3a + 3*(n))58#define PD67_TIME_CMD(n) (0x3b + 3*(n))59#define PD67_TIME_RECOV(n) (0x3c + 3*(n))60 61/* Flags for PD67_MISC_CTL_1 */62#define PD67_MC1_5V_DET 0x01 /* 5v detect */63#define PD67_MC1_MEDIA_ENA 0x01 /* 6730: Multimedia enable */64#define PD67_MC1_VCC_3V 0x02 /* 3.3v Vcc */65#define PD67_MC1_PULSE_MGMT 0x0466#define PD67_MC1_PULSE_IRQ 0x0867#define PD67_MC1_SPKR_ENA 0x1068#define PD67_MC1_INPACK_ENA 0x8069 70/* Flags for PD67_FIFO_CTL */71#define PD67_FIFO_EMPTY 0x8072 73/* Flags for PD67_MISC_CTL_2 */74#define PD67_MC2_FREQ_BYPASS 0x0175#define PD67_MC2_DYNAMIC_MODE 0x0276#define PD67_MC2_SUSPEND 0x0477#define PD67_MC2_5V_CORE 0x0878#define PD67_MC2_LED_ENA 0x10 /* IRQ 12 is LED enable */79#define PD67_MC2_FAST_PCI 0x10 /* 6729: PCI bus > 25 MHz */80#define PD67_MC2_3STATE_BIT7 0x20 /* Floppy change bit */81#define PD67_MC2_DMA_MODE 0x4082#define PD67_MC2_IRQ15_RI 0x80 /* IRQ 15 is ring enable */83 84/* Flags for PD67_CHIP_INFO */85#define PD67_INFO_SLOTS 0x20 /* 0 = 1 slot, 1 = 2 slots */86#define PD67_INFO_CHIP_ID 0xc087#define PD67_INFO_REV 0x1c88 89/* Fields in PD67_TIME_* registers */90#define PD67_TIME_SCALE 0xc091#define PD67_TIME_SCALE_1 0x0092#define PD67_TIME_SCALE_16 0x4093#define PD67_TIME_SCALE_256 0x8094#define PD67_TIME_SCALE_4096 0xc095#define PD67_TIME_MULT 0x3f96 97/* Fields in PD67_DMA_CTL */98#define PD67_DMA_MODE 0xc099#define PD67_DMA_OFF 0x00100#define PD67_DMA_DREQ_INPACK 0x40101#define PD67_DMA_DREQ_WP 0x80102#define PD67_DMA_DREQ_BVD2 0xc0103#define PD67_DMA_PULLUP 0x20 /* Disable socket pullups? */104 105/* Fields in PD67_EXT_CTL_1 */106#define PD67_EC1_VCC_PWR_LOCK 0x01107#define PD67_EC1_AUTO_PWR_CLEAR 0x02108#define PD67_EC1_LED_ENA 0x04109#define PD67_EC1_INV_CARD_IRQ 0x08110#define PD67_EC1_INV_MGMT_IRQ 0x10111#define PD67_EC1_PULLUP_CTL 0x20112 113/* Fields in PD67_MISC_CTL_3 */114#define PD67_MC3_IRQ_MASK 0x03115#define PD67_MC3_IRQ_PCPCI 0x00116#define PD67_MC3_IRQ_EXTERN 0x01117#define PD67_MC3_IRQ_PCIWAY 0x02118#define PD67_MC3_IRQ_PCI 0x03119#define PD67_MC3_PWR_MASK 0x0c120#define PD67_MC3_PWR_SERIAL 0x00121#define PD67_MC3_PWR_TI2202 0x08122#define PD67_MC3_PWR_SMB 0x0c123 124/* Register definitions for Cirrus PD6832 PCI-to-CardBus bridge */125 126/* PD6832 extension registers -- indexed in PD67_EXT_INDEX */127#define PD68_EXT_CTL_2 0x0b128#define PD68_PCI_SPACE 0x22129#define PD68_PCCARD_SPACE 0x23130#define PD68_WINDOW_TYPE 0x24131#define PD68_EXT_CSC 0x2e132#define PD68_MISC_CTL_4 0x2f133#define PD68_MISC_CTL_5 0x30134#define PD68_MISC_CTL_6 0x31135 136/* Extra flags in PD67_MISC_CTL_3 */137#define PD68_MC3_HW_SUSP 0x10138#define PD68_MC3_MM_EXPAND 0x40139#define PD68_MC3_MM_ARM 0x80140 141/* Bridge Control Register */142#define PD6832_BCR_MGMT_IRQ_ENA 0x0800143 144/* Socket Number Register */145#define PD6832_SOCKET_NUMBER 0x004c /* 8 bit */146 147#endif /* _LINUX_CIRRUS_H */148