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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * linux/drivers/pcmcia/soc_common.h4 *5 * Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu>6 *7 * This file contains definitions for the PCMCIA support code common to8 * integrated SOCs like the SA-11x0 and PXA2xx microprocessors.9 */10#ifndef _ASM_ARCH_PCMCIA11#define _ASM_ARCH_PCMCIA12 13/* include the world */14#include <linux/clk.h>15#include <linux/cpufreq.h>16#include <pcmcia/cistpl.h>17#include <pcmcia/soc_common.h>18 19struct device;20struct gpio_desc;21struct pcmcia_low_level;22struct regulator;23 24struct skt_dev_info {25 int nskt;26 struct soc_pcmcia_socket skt[];27};28 29struct soc_pcmcia_timing {30 unsigned short io;31 unsigned short mem;32 unsigned short attr;33};34 35extern void soc_common_pcmcia_get_timing(struct soc_pcmcia_socket *, struct soc_pcmcia_timing *);36 37void soc_pcmcia_init_one(struct soc_pcmcia_socket *skt,38 const struct pcmcia_low_level *ops, struct device *dev);39void soc_pcmcia_remove_one(struct soc_pcmcia_socket *skt);40int soc_pcmcia_add_one(struct soc_pcmcia_socket *skt);41int soc_pcmcia_request_gpiods(struct soc_pcmcia_socket *skt);42 43void soc_common_cf_socket_state(struct soc_pcmcia_socket *skt,44 struct pcmcia_state *state);45 46int soc_pcmcia_regulator_set(struct soc_pcmcia_socket *skt,47 struct soc_pcmcia_regulator *r, int v);48 49#ifdef CONFIG_PCMCIA_DEBUG50 51extern void soc_pcmcia_debug(struct soc_pcmcia_socket *skt, const char *func,52 int lvl, const char *fmt, ...);53 54#define debug(skt, lvl, fmt, arg...) \55 soc_pcmcia_debug(skt, __func__, lvl, fmt , ## arg)56 57#else58#define debug(skt, lvl, fmt, arg...) do { } while (0)59#endif60 61 62/*63 * The PC Card Standard, Release 7, section 4.13.4, says that twIORD64 * has a minimum value of 165ns. Section 4.13.5 says that twIOWR has65 * a minimum value of 165ns, as well. Section 4.7.2 (describing66 * common and attribute memory write timing) says that twWE has a67 * minimum value of 150ns for a 250ns cycle time (for 5V operation;68 * see section 4.7.4), or 300ns for a 600ns cycle time (for 3.3V69 * operation, also section 4.7.4). Section 4.7.3 says that taOE70 * has a maximum value of 150ns for a 300ns cycle time (for 5V71 * operation), or 300ns for a 600ns cycle time (for 3.3V operation).72 *73 * When configuring memory maps, Card Services appears to adopt the policy74 * that a memory access time of "0" means "use the default." The default75 * PCMCIA I/O command width time is 165ns. The default PCMCIA 5V attribute76 * and memory command width time is 150ns; the PCMCIA 3.3V attribute and77 * memory command width time is 300ns.78 */79#define SOC_PCMCIA_IO_ACCESS (165)80#define SOC_PCMCIA_5V_MEM_ACCESS (150)81#define SOC_PCMCIA_3V_MEM_ACCESS (300)82#define SOC_PCMCIA_ATTR_MEM_ACCESS (300)83 84/*85 * The socket driver actually works nicely in interrupt-driven form,86 * so the (relatively infrequent) polling is "just to be sure."87 */88#define SOC_PCMCIA_POLL_PERIOD (2*HZ)89 90 91/* I/O pins replacing memory pins92 * (PCMCIA System Architecture, 2nd ed., by Don Anderson, p.75)93 *94 * These signals change meaning when going from memory-only to95 * memory-or-I/O interface:96 */97#define iostschg bvd198#define iospkr bvd299 100#endif101