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1/*2 * tcic.h 1.13 1999/10/25 20:03:343 *4 * The contents of this file are subject to the Mozilla Public License5 * Version 1.1 (the "License"); you may not use this file except in6 * compliance with the License. You may obtain a copy of the License7 * at http://www.mozilla.org/MPL/8 *9 * Software distributed under the License is distributed on an "AS IS"10 * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See11 * the License for the specific language governing rights and12 * limitations under the License. 13 *14 * The initial developer of the original code is David A. Hinds15 * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds16 * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.17 *18 * Alternatively, the contents of this file may be used under the19 * terms of the GNU General Public License version 2 (the "GPL"), in which20 * case the provisions of the GPL are applicable instead of the21 * above. If you wish to allow the use of your version of this file22 * only under the terms of the GPL and not to allow others to use23 * your version of this file under the MPL, indicate your decision by24 * deleting the provisions above and replace them with the notice and25 * other provisions required by the GPL. If you do not delete the26 * provisions above, a recipient may use your version of this file27 * under either the MPL or the GPL.28 */29 30#ifndef _LINUX_TCIC_H31#define _LINUX_TCIC_H32 33#define TCIC_BASE 0x24034 35/* offsets of registers from TCIC_BASE */36#define TCIC_DATA 0x0037#define TCIC_ADDR 0x0238#define TCIC_SCTRL 0x0639#define TCIC_SSTAT 0x0740#define TCIC_MODE 0x0841#define TCIC_PWR 0x0942#define TCIC_EDC 0x0A43#define TCIC_ICSR 0x0C44#define TCIC_IENA 0x0D45#define TCIC_AUX 0x0E46 47#define TCIC_SS_SHFT 1248#define TCIC_SS_MASK 0x700049 50/* Flags for TCIC_ADDR */51#define TCIC_ADR2_REG 0x800052#define TCIC_ADR2_INDREG 0x080053 54#define TCIC_ADDR_REG 0x8000000055#define TCIC_ADDR_SS_SHFT (TCIC_SS_SHFT+16)56#define TCIC_ADDR_SS_MASK (TCIC_SS_MASK<<16)57#define TCIC_ADDR_INDREG 0x0800000058#define TCIC_ADDR_IO 0x0400000059#define TCIC_ADDR_MASK 0x03ffffff60 61/* Flags for TCIC_SCTRL */62#define TCIC_SCTRL_ENA 0x0163#define TCIC_SCTRL_INCMODE 0x1864#define TCIC_SCTRL_INCMODE_HOLD 0x0065#define TCIC_SCTRL_INCMODE_WORD 0x0866#define TCIC_SCTRL_INCMODE_REG 0x1067#define TCIC_SCTRL_INCMODE_AUTO 0x1868#define TCIC_SCTRL_EDCSUM 0x2069#define TCIC_SCTRL_RESET 0x8070 71/* Flags for TCIC_SSTAT */72#define TCIC_SSTAT_6US 0x0173#define TCIC_SSTAT_10US 0x0274#define TCIC_SSTAT_PROGTIME 0x0475#define TCIC_SSTAT_LBAT1 0x0876#define TCIC_SSTAT_LBAT2 0x1077#define TCIC_SSTAT_RDY 0x20 /* Inverted */78#define TCIC_SSTAT_WP 0x4079#define TCIC_SSTAT_CD 0x80 /* Card detect */80 81/* Flags for TCIC_MODE */82#define TCIC_MODE_PGMMASK 0x1f83#define TCIC_MODE_NORMAL 0x0084#define TCIC_MODE_PGMWR 0x0185#define TCIC_MODE_PGMRD 0x0286#define TCIC_MODE_PGMCE 0x0487#define TCIC_MODE_PGMDBW 0x0888#define TCIC_MODE_PGMWORD 0x1089#define TCIC_MODE_AUXSEL_MASK 0xe090 91/* Registers accessed through TCIC_AUX, by setting TCIC_MODE */92#define TCIC_AUX_TCTL (0<<5)93#define TCIC_AUX_PCTL (1<<5)94#define TCIC_AUX_WCTL (2<<5)95#define TCIC_AUX_EXTERN (3<<5)96#define TCIC_AUX_PDATA (4<<5)97#define TCIC_AUX_SYSCFG (5<<5)98#define TCIC_AUX_ILOCK (6<<5)99#define TCIC_AUX_TEST (7<<5)100 101/* Flags for TCIC_PWR */102#define TCIC_PWR_VCC(sock) (0x01<<(sock))103#define TCIC_PWR_VCC_MASK 0x03104#define TCIC_PWR_VPP(sock) (0x08<<(sock))105#define TCIC_PWR_VPP_MASK 0x18106#define TCIC_PWR_CLIMENA 0x40107#define TCIC_PWR_CLIMSTAT 0x80108 109/* Flags for TCIC_ICSR */110#define TCIC_ICSR_CLEAR 0x01111#define TCIC_ICSR_SET 0x02112#define TCIC_ICSR_JAM (TCIC_ICSR_CLEAR|TCIC_ICSR_SET)113#define TCIC_ICSR_STOPCPU 0x04114#define TCIC_ICSR_ILOCK 0x08115#define TCIC_ICSR_PROGTIME 0x10116#define TCIC_ICSR_ERR 0x20117#define TCIC_ICSR_CDCHG 0x40118#define TCIC_ICSR_IOCHK 0x80119 120/* Flags for TCIC_IENA */121#define TCIC_IENA_CFG_MASK 0x03122#define TCIC_IENA_CFG_OFF 0x00 /* disabled */123#define TCIC_IENA_CFG_OD 0x01 /* active low, open drain */124#define TCIC_IENA_CFG_LOW 0x02 /* active low, totem pole */125#define TCIC_IENA_CFG_HIGH 0x03 /* active high, totem pole */126#define TCIC_IENA_ILOCK 0x08127#define TCIC_IENA_PROGTIME 0x10128#define TCIC_IENA_ERR 0x20 /* overcurrent or iochk */129#define TCIC_IENA_CDCHG 0x40130 131/* Flags for TCIC_AUX_WCTL */132#define TCIC_WAIT_COUNT_MASK 0x001f133#define TCIC_WAIT_ASYNC 0x0020134#define TCIC_WAIT_SENSE 0x0040135#define TCIC_WAIT_SRC 0x0080136#define TCIC_WCTL_WR 0x0100137#define TCIC_WCTL_RD 0x0200138#define TCIC_WCTL_CE 0x0400139#define TCIC_WCTL_LLBAT1 0x0800140#define TCIC_WCTL_LLBAT2 0x1000141#define TCIC_WCTL_LRDY 0x2000142#define TCIC_WCTL_LWP 0x4000143#define TCIC_WCTL_LCD 0x8000144 145/* Flags for TCIC_AUX_SYSCFG */146#define TCIC_SYSCFG_IRQ_MASK 0x000f147#define TCIC_SYSCFG_MCSFULL 0x0010148#define TCIC_SYSCFG_IO1723 0x0020149#define TCIC_SYSCFG_MCSXB 0x0040150#define TCIC_SYSCFG_ICSXB 0x0080151#define TCIC_SYSCFG_NOPDN 0x0100152#define TCIC_SYSCFG_MPSEL_SHFT 9153#define TCIC_SYSCFG_MPSEL_MASK 0x0e00154#define TCIC_SYSCFG_MPSENSE 0x2000155#define TCIC_SYSCFG_AUTOBUSY 0x4000156#define TCIC_SYSCFG_ACC 0x8000157 158#define TCIC_ILOCK_OUT 0x01159#define TCIC_ILOCK_SENSE 0x02160#define TCIC_ILOCK_CRESET 0x04161#define TCIC_ILOCK_CRESENA 0x08162#define TCIC_ILOCK_CWAIT 0x10163#define TCIC_ILOCK_CWAITSNS 0x20164#define TCIC_ILOCK_HOLD_MASK 0xc0165#define TCIC_ILOCK_HOLD_CCLK 0xc0166 167#define TCIC_ILOCKTEST_ID_SH 8168#define TCIC_ILOCKTEST_ID_MASK 0x7f00169#define TCIC_ILOCKTEST_MCIC_1 0x8000170 171#define TCIC_ID_DB86082 0x02172#define TCIC_ID_DB86082A 0x03173#define TCIC_ID_DB86084 0x04174#define TCIC_ID_DB86084A 0x08175#define TCIC_ID_DB86072 0x15176#define TCIC_ID_DB86184 0x14177#define TCIC_ID_DB86082B 0x17178 179#define TCIC_TEST_DIAG 0x8000180 181/*182 * Indirectly addressed registers183 */184 185#define TCIC_SCF1(sock) ((sock)<<3)186#define TCIC_SCF2(sock) (((sock)<<3)+2)187 188/* Flags for SCF1 */189#define TCIC_SCF1_IRQ_MASK 0x000f190#define TCIC_SCF1_IRQ_OFF 0x0000191#define TCIC_SCF1_IRQOC 0x0010192#define TCIC_SCF1_PCVT 0x0020193#define TCIC_SCF1_IRDY 0x0040194#define TCIC_SCF1_ATA 0x0080195#define TCIC_SCF1_DMA_SHIFT 8196#define TCIC_SCF1_DMA_MASK 0x0700197#define TCIC_SCF1_DMA_OFF 0198#define TCIC_SCF1_DREQ2 2199#define TCIC_SCF1_IOSTS 0x0800200#define TCIC_SCF1_SPKR 0x1000201#define TCIC_SCF1_FINPACK 0x2000202#define TCIC_SCF1_DELWR 0x4000203#define TCIC_SCF1_HD7IDE 0x8000204 205/* Flags for SCF2 */206#define TCIC_SCF2_RI 0x0001207#define TCIC_SCF2_IDBR 0x0002208#define TCIC_SCF2_MDBR 0x0004209#define TCIC_SCF2_MLBAT1 0x0008210#define TCIC_SCF2_MLBAT2 0x0010211#define TCIC_SCF2_MRDY 0x0020212#define TCIC_SCF2_MWP 0x0040213#define TCIC_SCF2_MCD 0x0080214#define TCIC_SCF2_MALL 0x00f8215 216/* Indirect addresses for memory window registers */217#define TCIC_MWIN(sock,map) (0x100+(((map)+((sock)<<2))<<3))218#define TCIC_MBASE_X 2219#define TCIC_MMAP_X 4220#define TCIC_MCTL_X 6221 222#define TCIC_MBASE_4K_BIT 0x4000223#define TCIC_MBASE_HA_SHFT 12224#define TCIC_MBASE_HA_MASK 0x0fff225 226#define TCIC_MMAP_REG 0x8000227#define TCIC_MMAP_CA_SHFT 12228#define TCIC_MMAP_CA_MASK 0x3fff229 230#define TCIC_MCTL_WSCNT_MASK 0x001f231#define TCIC_MCTL_WCLK 0x0020232#define TCIC_MCTL_WCLK_CCLK 0x0000233#define TCIC_MCTL_WCLK_BCLK 0x0020234#define TCIC_MCTL_QUIET 0x0040235#define TCIC_MCTL_WP 0x0080236#define TCIC_MCTL_ACC 0x0100237#define TCIC_MCTL_KE 0x0200238#define TCIC_MCTL_EDC 0x0400239#define TCIC_MCTL_B8 0x0800240#define TCIC_MCTL_SS_SHFT TCIC_SS_SHFT241#define TCIC_MCTL_SS_MASK TCIC_SS_MASK242#define TCIC_MCTL_ENA 0x8000243 244/* Indirect addresses for I/O window registers */245#define TCIC_IWIN(sock,map) (0x200+(((map)+((sock)<<1))<<2))246#define TCIC_IBASE_X 0247#define TCIC_ICTL_X 2248 249#define TCIC_ICTL_WSCNT_MASK TCIC_MCTL_WSCNT_MASK250#define TCIC_ICTL_QUIET TCIC_MCTL_QUIET251#define TCIC_ICTL_1K 0x0080252#define TCIC_ICTL_PASS16 0x0100253#define TCIC_ICTL_ACC TCIC_MCTL_ACC254#define TCIC_ICTL_TINY 0x0200255#define TCIC_ICTL_B16 0x0400256#define TCIC_ICTL_B8 TCIC_MCTL_B8257#define TCIC_ICTL_BW_MASK (TCIC_ICTL_B16|TCIC_ICTL_B8)258#define TCIC_ICTL_BW_DYN 0259#define TCIC_ICTL_BW_8 TCIC_ICTL_B8260#define TCIC_ICTL_BW_16 TCIC_ICTL_B16261#define TCIC_ICTL_BW_ATA (TCIC_ICTL_B16|TCIC_ICTL_B8)262#define TCIC_ICTL_SS_SHFT TCIC_SS_SHFT263#define TCIC_ICTL_SS_MASK TCIC_SS_MASK264#define TCIC_ICTL_ENA TCIC_MCTL_ENA265 266#endif /* _LINUX_TCIC_H */267