288 lines · plain
1# SPDX-License-Identifier: GPL-2.0-only2#3# Performance Monitor Drivers4#5 6menu "Performance monitor support"7 depends on PERF_EVENTS8 9config ARM_CCI_PMU10 tristate "ARM CCI PMU driver"11 depends on (ARM && CPU_V7) || ARM6412 select ARM_CCI13 help14 Support for PMU events monitoring on the ARM CCI (Cache Coherent15 Interconnect) family of products.16 17 If compiled as a module, it will be called arm-cci.18 19config ARM_CCI400_PMU20 bool "support CCI-400"21 default y22 depends on ARM_CCI_PMU23 select ARM_CCI400_COMMON24 help25 CCI-400 provides 4 independent event counters counting events related26 to the connected slave/master interfaces, plus a cycle counter.27 28config ARM_CCI5xx_PMU29 bool "support CCI-500/CCI-550"30 default y31 depends on ARM_CCI_PMU32 help33 CCI-500/CCI-550 both provide 8 independent event counters, which can34 count events pertaining to the slave/master interfaces as well as the35 internal events to the CCI.36 37config ARM_CCN38 tristate "ARM CCN driver support"39 depends on ARM || ARM64 || COMPILE_TEST40 help41 PMU (perf) driver supporting the ARM CCN (Cache Coherent Network)42 interconnect.43 44config ARM_CMN45 tristate "Arm CMN-600 PMU support"46 depends on ARM64 || COMPILE_TEST47 help48 Support for PMU events monitoring on the Arm CMN-600 Coherent Mesh49 Network interconnect.50 51config ARM_NI52 tristate "Arm NI-700 PMU support"53 depends on ARM64 || COMPILE_TEST54 help55 Support for PMU events monitoring on the Arm NI-700 Network-on-Chip56 interconnect and family.57 58config ARM_PMU59 depends on ARM || ARM6460 bool "ARM PMU framework"61 default y62 help63 Say y if you want to use CPU performance monitors on ARM-based64 systems.65 66config ARM_V6_PMU67 depends on ARM_PMU && (CPU_V6 || CPU_V6K)68 def_bool y69 70config ARM_V7_PMU71 depends on ARM_PMU && CPU_V772 def_bool y73 74config ARM_XSCALE_PMU75 depends on ARM_PMU && CPU_XSCALE76 def_bool y77 78config RISCV_PMU79 depends on RISCV80 bool "RISC-V PMU framework"81 default y82 help83 Say y if you want to use CPU performance monitors on RISCV-based84 systems. This provides the core PMU framework that abstracts common85 PMU functionalities in a core library so that different PMU drivers86 can reuse it.87 88config RISCV_PMU_LEGACY89 depends on RISCV_PMU90 bool "RISC-V legacy PMU implementation"91 default y92 help93 Say y if you want to use the legacy CPU performance monitor94 implementation on RISC-V based systems. This only allows counting95 of cycle/instruction counter and doesn't support counter overflow,96 or programmable counters. It will be removed in future.97 98config RISCV_PMU_SBI99 depends on RISCV_PMU && RISCV_SBI100 bool "RISC-V PMU based on SBI PMU extension"101 default y102 help103 Say y if you want to use the CPU performance monitor104 using SBI PMU extension on RISC-V based systems. This option provides105 full perf feature support i.e. counter overflow, privilege mode106 filtering, counter configuration.107 108config STARFIVE_STARLINK_PMU109 depends on ARCH_STARFIVE || COMPILE_TEST110 depends on 64BIT111 bool "StarFive StarLink PMU"112 help113 Provide support for StarLink Performance Monitor Unit.114 StarLink Performance Monitor Unit integrates one or more cores with115 an L3 memory system. The L3 cache events are added into perf event116 subsystem, allowing monitoring of various L3 cache perf events.117 118config ANDES_CUSTOM_PMU119 bool "Andes custom PMU support"120 depends on ARCH_RENESAS && RISCV_ALTERNATIVE && RISCV_PMU_SBI121 default y122 help123 The Andes cores implement the PMU overflow extension very124 similar to the standard Sscofpmf and Smcntrpmf extension.125 126 This will patch the overflow and pending CSRs and handle the127 non-standard behaviour via the regular SBI PMU driver and128 interface.129 130 If you don't know what to do here, say "Y".131 132config ARM_PMU_ACPI133 depends on ARM_PMU && ACPI134 def_bool y135 136config ARM_SMMU_V3_PMU137 tristate "ARM SMMUv3 Performance Monitors Extension"138 depends on ARM64 || (COMPILE_TEST && 64BIT)139 depends on GENERIC_MSI_IRQ140 help141 Provides support for the ARM SMMUv3 Performance Monitor Counter142 Groups (PMCG), which provide monitoring of transactions passing143 through the SMMU and allow the resulting information to be filtered144 based on the Stream ID of the corresponding master.145 146config ARM_PMUV3147 depends on HW_PERF_EVENTS && ((ARM && CPU_V7) || ARM64)148 bool "ARM PMUv3 support" if !ARM64149 default ARM64150 help151 Say y if you want to use the ARM performance monitor unit (PMU)152 version 3. The PMUv3 is the CPU performance monitors on ARMv8153 (aarch32 and aarch64) systems that implement the PMUv3154 architecture.155 156config ARM_DSU_PMU157 tristate "ARM DynamIQ Shared Unit (DSU) PMU"158 depends on ARM64159 help160 Provides support for performance monitor unit in ARM DynamIQ Shared161 Unit (DSU). The DSU integrates one or more cores with an L3 memory162 system, control logic. The PMU allows counting various events related163 to DSU.164 165config FSL_IMX8_DDR_PMU166 tristate "Freescale i.MX8 DDR perf monitor"167 depends on ARCH_MXC || COMPILE_TEST168 help169 Provides support for the DDR performance monitor in i.MX8, which170 can give information about memory throughput and other related171 events.172 173config FSL_IMX9_DDR_PMU174 tristate "Freescale i.MX9 DDR perf monitor"175 depends on ARCH_MXC176 help177 Provides support for the DDR performance monitor in i.MX9, which178 can give information about memory throughput and other related179 events.180 181config QCOM_L2_PMU182 bool "Qualcomm Technologies L2-cache PMU"183 depends on ARCH_QCOM && ARM64 && ACPI184 select QCOM_KRYO_L2_ACCESSORS185 help186 Provides support for the L2 cache performance monitor unit (PMU)187 in Qualcomm Technologies processors.188 Adds the L2 cache PMU into the perf events subsystem for189 monitoring L2 cache events.190 191config QCOM_L3_PMU192 bool "Qualcomm Technologies L3-cache PMU"193 depends on ARCH_QCOM && ARM64 && ACPI194 select QCOM_IRQ_COMBINER195 help196 Provides support for the L3 cache performance monitor unit (PMU)197 in Qualcomm Technologies processors.198 Adds the L3 cache PMU into the perf events subsystem for199 monitoring L3 cache events.200 201config THUNDERX2_PMU202 tristate "Cavium ThunderX2 SoC PMU UNCORE"203 depends on ARCH_THUNDER2 || COMPILE_TEST204 depends on NUMA && ACPI205 default m206 help207 Provides support for ThunderX2 UNCORE events.208 The SoC has PMU support in its L3 cache controller (L3C) and209 in the DDR4 Memory Controller (DMC).210 211config XGENE_PMU212 depends on ARCH_XGENE || (COMPILE_TEST && 64BIT)213 bool "APM X-Gene SoC PMU"214 default n215 help216 Say y if you want to use APM X-Gene SoC performance monitors.217 218config ARM_SPE_PMU219 tristate "Enable support for the ARMv8.2 Statistical Profiling Extension"220 depends on ARM64221 help222 Enable perf support for the ARMv8.2 Statistical Profiling223 Extension, which provides periodic sampling of operations in224 the CPU pipeline and reports this via the perf AUX interface.225 226config ARM_DMC620_PMU227 tristate "Enable PMU support for the ARM DMC-620 memory controller"228 depends on (ARM64 && ACPI) || COMPILE_TEST229 help230 Support for PMU events monitoring on the ARM DMC-620 memory231 controller.232 233config MARVELL_CN10K_TAD_PMU234 tristate "Marvell CN10K LLC-TAD PMU"235 depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT)236 help237 Provides support for Last-Level cache Tag-and-data Units (LLC-TAD)238 performance monitors on CN10K family silicons.239 240config APPLE_M1_CPU_PMU241 bool "Apple M1 CPU PMU support"242 depends on ARM_PMU && ARCH_APPLE243 help244 Provides support for the non-architectural CPU PMUs present on245 the Apple M1 SoCs and derivatives.246 247config ALIBABA_UNCORE_DRW_PMU248 tristate "Alibaba T-Head Yitian 710 DDR Sub-system Driveway PMU driver"249 depends on (ARM64 && ACPI) || COMPILE_TEST250 help251 Support for Driveway PMU events monitoring on Yitian 710 DDR252 Sub-system.253 254source "drivers/perf/hisilicon/Kconfig"255 256config MARVELL_CN10K_DDR_PMU257 tristate "Enable MARVELL CN10K DRAM Subsystem(DSS) PMU Support"258 depends on ARCH_THUNDER || (COMPILE_TEST && 64BIT)259 help260 Enable perf support for Marvell DDR Performance monitoring261 event on CN10K platform.262 263config DWC_PCIE_PMU264 tristate "Synopsys DesignWare PCIe PMU"265 depends on PCI266 help267 Enable perf support for Synopsys DesignWare PCIe PMU Performance268 monitoring event on platform including the Alibaba Yitian 710.269 270source "drivers/perf/arm_cspmu/Kconfig"271 272source "drivers/perf/amlogic/Kconfig"273 274config CXL_PMU275 tristate "CXL Performance Monitoring Unit"276 depends on CXL_BUS277 help278 Support performance monitoring as defined in CXL rev 3.0279 section 13.2: Performance Monitoring. CXL components may have280 one or more CXL Performance Monitoring Units (CPMUs).281 282 Say 'y/m' to enable a driver that will attach to performance283 monitoring units and provide standard perf based interfaces.284 285 If unsure say 'm'.286 287endmenu288