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1// SPDX-License-Identifier: GPL-2.0-only2// Copyright (C) 2015 Broadcom Corporation3 4#include <linux/delay.h>5#include <linux/io.h>6#include <linux/module.h>7#include <linux/of.h>8#include <linux/phy/phy.h>9#include <linux/platform_device.h>10 11#define PCIE_CFG_OFFSET 0x0012#define PCIE1_PHY_IDDQ_SHIFT 1013#define PCIE0_PHY_IDDQ_SHIFT 214 15enum cygnus_pcie_phy_id {16 CYGNUS_PHY_PCIE0 = 0,17 CYGNUS_PHY_PCIE1,18 MAX_NUM_PHYS,19};20 21struct cygnus_pcie_phy_core;22 23/**24 * struct cygnus_pcie_phy - Cygnus PCIe PHY device25 * @core: pointer to the Cygnus PCIe PHY core control26 * @id: internal ID to identify the Cygnus PCIe PHY27 * @phy: pointer to the kernel PHY device28 */29struct cygnus_pcie_phy {30 struct cygnus_pcie_phy_core *core;31 enum cygnus_pcie_phy_id id;32 struct phy *phy;33};34 35/**36 * struct cygnus_pcie_phy_core - Cygnus PCIe PHY core control37 * @dev: pointer to device38 * @base: base register39 * @lock: mutex to protect access to individual PHYs40 * @phys: pointer to Cygnus PHY device41 */42struct cygnus_pcie_phy_core {43 struct device *dev;44 void __iomem *base;45 struct mutex lock;46 struct cygnus_pcie_phy phys[MAX_NUM_PHYS];47};48 49static int cygnus_pcie_power_config(struct cygnus_pcie_phy *phy, bool enable)50{51 struct cygnus_pcie_phy_core *core = phy->core;52 unsigned shift;53 u32 val;54 55 mutex_lock(&core->lock);56 57 switch (phy->id) {58 case CYGNUS_PHY_PCIE0:59 shift = PCIE0_PHY_IDDQ_SHIFT;60 break;61 62 case CYGNUS_PHY_PCIE1:63 shift = PCIE1_PHY_IDDQ_SHIFT;64 break;65 66 default:67 mutex_unlock(&core->lock);68 dev_err(core->dev, "PCIe PHY %d invalid\n", phy->id);69 return -EINVAL;70 }71 72 if (enable) {73 val = readl(core->base + PCIE_CFG_OFFSET);74 val &= ~BIT(shift);75 writel(val, core->base + PCIE_CFG_OFFSET);76 /*77 * Wait 50 ms for the PCIe Serdes to stabilize after the analog78 * front end is brought up79 */80 msleep(50);81 } else {82 val = readl(core->base + PCIE_CFG_OFFSET);83 val |= BIT(shift);84 writel(val, core->base + PCIE_CFG_OFFSET);85 }86 87 mutex_unlock(&core->lock);88 dev_dbg(core->dev, "PCIe PHY %d %s\n", phy->id,89 enable ? "enabled" : "disabled");90 return 0;91}92 93static int cygnus_pcie_phy_power_on(struct phy *p)94{95 struct cygnus_pcie_phy *phy = phy_get_drvdata(p);96 97 return cygnus_pcie_power_config(phy, true);98}99 100static int cygnus_pcie_phy_power_off(struct phy *p)101{102 struct cygnus_pcie_phy *phy = phy_get_drvdata(p);103 104 return cygnus_pcie_power_config(phy, false);105}106 107static const struct phy_ops cygnus_pcie_phy_ops = {108 .power_on = cygnus_pcie_phy_power_on,109 .power_off = cygnus_pcie_phy_power_off,110 .owner = THIS_MODULE,111};112 113static int cygnus_pcie_phy_probe(struct platform_device *pdev)114{115 struct device *dev = &pdev->dev;116 struct device_node *node = dev->of_node;117 struct cygnus_pcie_phy_core *core;118 struct phy_provider *provider;119 unsigned cnt = 0;120 121 if (of_get_child_count(node) == 0) {122 dev_err(dev, "PHY no child node\n");123 return -ENODEV;124 }125 126 core = devm_kzalloc(dev, sizeof(*core), GFP_KERNEL);127 if (!core)128 return -ENOMEM;129 130 core->dev = dev;131 132 core->base = devm_platform_ioremap_resource(pdev, 0);133 if (IS_ERR(core->base))134 return PTR_ERR(core->base);135 136 mutex_init(&core->lock);137 138 for_each_available_child_of_node_scoped(node, child) {139 unsigned int id;140 struct cygnus_pcie_phy *p;141 142 if (of_property_read_u32(child, "reg", &id)) {143 dev_err(dev, "missing reg property for %pOFn\n",144 child);145 return -EINVAL;146 }147 148 if (id >= MAX_NUM_PHYS) {149 dev_err(dev, "invalid PHY id: %u\n", id);150 return -EINVAL;151 }152 153 if (core->phys[id].phy) {154 dev_err(dev, "duplicated PHY id: %u\n", id);155 return -EINVAL;156 }157 158 p = &core->phys[id];159 p->phy = devm_phy_create(dev, child, &cygnus_pcie_phy_ops);160 if (IS_ERR(p->phy)) {161 dev_err(dev, "failed to create PHY\n");162 return PTR_ERR(p->phy);163 }164 165 p->core = core;166 p->id = id;167 phy_set_drvdata(p->phy, p);168 cnt++;169 }170 171 dev_set_drvdata(dev, core);172 173 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);174 if (IS_ERR(provider)) {175 dev_err(dev, "failed to register PHY provider\n");176 return PTR_ERR(provider);177 }178 179 dev_dbg(dev, "registered %u PCIe PHY(s)\n", cnt);180 181 return 0;182}183 184static const struct of_device_id cygnus_pcie_phy_match_table[] = {185 { .compatible = "brcm,cygnus-pcie-phy" },186 { /* sentinel */ }187};188MODULE_DEVICE_TABLE(of, cygnus_pcie_phy_match_table);189 190static struct platform_driver cygnus_pcie_phy_driver = {191 .driver = {192 .name = "cygnus-pcie-phy",193 .of_match_table = cygnus_pcie_phy_match_table,194 },195 .probe = cygnus_pcie_phy_probe,196};197module_platform_driver(cygnus_pcie_phy_driver);198 199MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");200MODULE_DESCRIPTION("Broadcom Cygnus PCIe PHY driver");201MODULE_LICENSE("GPL v2");202