brintos / linux-shallow public Read only

1// SPDX-License-Identifier: GPL-2.02/*3 * Cadence Sierra PHY Driver4 *5 * Copyright (c) 2018 Cadence Design Systems6 * Author: Alan Douglas <adouglas@cadence.com>7 *8 */9#include <linux/clk.h>10#include <linux/clk-provider.h>11#include <linux/delay.h>12#include <linux/err.h>13#include <linux/io.h>14#include <linux/module.h>15#include <linux/phy/phy.h>16#include <linux/platform_device.h>17#include <linux/pm_runtime.h>18#include <linux/regmap.h>19#include <linux/reset.h>20#include <linux/slab.h>21#include <linux/of.h>22#include <linux/of_platform.h>23#include <dt-bindings/phy/phy.h>24#include <dt-bindings/phy/phy-cadence.h>25 26#define NUM_SSC_MODE		327#define NUM_PHY_TYPE		528 29/* PHY register offsets */30#define SIERRA_COMMON_CDB_OFFSET			0x031#define SIERRA_MACRO_ID_REG				0x032#define SIERRA_CMN_PLLLC_GEN_PREG			0x4233#define SIERRA_CMN_PLLLC_FBDIV_INT_MODE0_PREG		0x4334#define SIERRA_CMN_PLLLC_DCOCAL_CTRL_PREG		0x4535#define SIERRA_CMN_PLLLC_INIT_PREG			0x4636#define SIERRA_CMN_PLLLC_ITERTMR_PREG			0x4737#define SIERRA_CMN_PLLLC_MODE_PREG			0x4838#define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG		0x4939#define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG		0x4A40#define SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG		0x4B41#define SIERRA_CMN_PLLLC_LOCKSEARCH_PREG		0x4C42#define SIERRA_CMN_PLLLC_CLK1_PREG			0x4D43#define SIERRA_CMN_PLLLC_CLK0_PREG			0x4E44#define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG		0x4F45#define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG		0x5046#define SIERRA_CMN_PLLLC_DSMCORR_PREG			0x5147#define SIERRA_CMN_PLLLC_SS_PREG			0x5248#define SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG		0x5349#define SIERRA_CMN_PLLLC_SSTWOPT_PREG			0x5450#define SIERRA_CMN_PLLCSM_PLLEN_TMR_PREG		0x5D51#define SIERRA_CMN_PLLCSM_PLLPRE_TMR_PREG		0x5E52#define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG	0x6253#define SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG		0x6354#define SIERRA_SDOSCCAL_CLK_CNT_PREG			0x6E55#define SIERRA_CMN_REFRCV_PREG				0x9856#define SIERRA_CMN_RESCAL_CTRLA_PREG			0xA057#define SIERRA_CMN_REFRCV1_PREG				0xB858#define SIERRA_CMN_PLLLC1_GEN_PREG			0xC259#define SIERRA_CMN_PLLLC1_FBDIV_INT_PREG		0xC360#define SIERRA_CMN_PLLLC1_DCOCAL_CTRL_PREG		0xC561#define SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG		0xCA62#define SIERRA_CMN_PLLLC1_CLK0_PREG			0xCE63#define SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG		0xD064#define SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG	0xE265 66#define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset)	\67				((0x4000 << (block_offset)) + \68				 (((ln) << 9) << (reg_offset)))69 70#define SIERRA_DET_STANDEC_A_PREG			0x00071#define SIERRA_DET_STANDEC_B_PREG			0x00172#define SIERRA_DET_STANDEC_C_PREG			0x00273#define SIERRA_DET_STANDEC_D_PREG			0x00374#define SIERRA_DET_STANDEC_E_PREG			0x00475#define SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG		0x00876#define SIERRA_PSM_A0IN_TMR_PREG			0x00977#define SIERRA_PSM_A3IN_TMR_PREG			0x00C78#define SIERRA_PSM_DIAG_PREG				0x01579#define SIERRA_PSC_LN_A3_PREG				0x02380#define SIERRA_PSC_LN_A4_PREG				0x02481#define SIERRA_PSC_LN_IDLE_PREG				0x02682#define SIERRA_PSC_TX_A0_PREG				0x02883#define SIERRA_PSC_TX_A1_PREG				0x02984#define SIERRA_PSC_TX_A2_PREG				0x02A85#define SIERRA_PSC_TX_A3_PREG				0x02B86#define SIERRA_PSC_RX_A0_PREG				0x03087#define SIERRA_PSC_RX_A1_PREG				0x03188#define SIERRA_PSC_RX_A2_PREG				0x03289#define SIERRA_PSC_RX_A3_PREG				0x03390#define SIERRA_PLLCTRL_FBDIV_MODE01_PREG		0x03991#define SIERRA_PLLCTRL_SUBRATE_PREG			0x03A92#define SIERRA_PLLCTRL_GEN_A_PREG			0x03B93#define SIERRA_PLLCTRL_GEN_D_PREG			0x03E94#define SIERRA_PLLCTRL_CPGAIN_MODE_PREG			0x03F95#define SIERRA_PLLCTRL_STATUS_PREG			0x04496#define SIERRA_CLKPATH_BIASTRIM_PREG			0x04B97#define SIERRA_DFE_BIASTRIM_PREG			0x04C98#define SIERRA_DRVCTRL_ATTEN_PREG			0x06A99#define SIERRA_DRVCTRL_BOOST_PREG			0x06F100#define SIERRA_LANE_TX_RECEIVER_DETECT_PREG		0x071101#define SIERRA_TX_RCVDET_OVRD_PREG			0x072102#define SIERRA_CLKPATHCTRL_TMR_PREG			0x081103#define SIERRA_RX_CREQ_FLTR_A_MODE3_PREG		0x085104#define SIERRA_RX_CREQ_FLTR_A_MODE2_PREG		0x086105#define SIERRA_RX_CREQ_FLTR_A_MODE1_PREG		0x087106#define SIERRA_RX_CREQ_FLTR_A_MODE0_PREG		0x088107#define SIERRA_CREQ_DCBIASATTEN_OVR_PREG		0x08C108#define SIERRA_CREQ_CCLKDET_MODE01_PREG			0x08E109#define SIERRA_RX_CTLE_CAL_PREG				0x08F110#define SIERRA_RX_CTLE_MAINTENANCE_PREG			0x091111#define SIERRA_CREQ_FSMCLK_SEL_PREG			0x092112#define SIERRA_CREQ_EQ_CTRL_PREG			0x093113#define SIERRA_CREQ_SPARE_PREG				0x096114#define SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG		0x097115#define SIERRA_CTLELUT_CTRL_PREG			0x098116#define SIERRA_DEQ_BLK_TAU_CTRL1_PREG			0x0AC117#define SIERRA_DEQ_BLK_TAU_CTRL4_PREG			0x0AF118#define SIERRA_DFE_ECMP_RATESEL_PREG			0x0C0119#define SIERRA_DFE_SMP_RATESEL_PREG			0x0C1120#define SIERRA_DEQ_PHALIGN_CTRL				0x0C4121#define SIERRA_DEQ_CONCUR_CTRL1_PREG			0x0C8122#define SIERRA_DEQ_CONCUR_CTRL2_PREG			0x0C9123#define SIERRA_DEQ_EPIPWR_CTRL2_PREG			0x0CD124#define SIERRA_DEQ_FAST_MAINT_CYCLES_PREG		0x0CE125#define SIERRA_DEQ_ERRCMP_CTRL_PREG			0x0D0126#define SIERRA_DEQ_OFFSET_CTRL_PREG			0x0D8127#define SIERRA_DEQ_GAIN_CTRL_PREG			0x0E0128#define SIERRA_DEQ_VGATUNE_CTRL_PREG			0x0E1129#define SIERRA_DEQ_GLUT0				0x0E8130#define SIERRA_DEQ_GLUT1				0x0E9131#define SIERRA_DEQ_GLUT2				0x0EA132#define SIERRA_DEQ_GLUT3				0x0EB133#define SIERRA_DEQ_GLUT4				0x0EC134#define SIERRA_DEQ_GLUT5				0x0ED135#define SIERRA_DEQ_GLUT6				0x0EE136#define SIERRA_DEQ_GLUT7				0x0EF137#define SIERRA_DEQ_GLUT8				0x0F0138#define SIERRA_DEQ_GLUT9				0x0F1139#define SIERRA_DEQ_GLUT10				0x0F2140#define SIERRA_DEQ_GLUT11				0x0F3141#define SIERRA_DEQ_GLUT12				0x0F4142#define SIERRA_DEQ_GLUT13				0x0F5143#define SIERRA_DEQ_GLUT14				0x0F6144#define SIERRA_DEQ_GLUT15				0x0F7145#define SIERRA_DEQ_GLUT16				0x0F8146#define SIERRA_POSTPRECUR_EN_CEPH_CTRL_PREG		0x0F9147#define SIERRA_TAU_EN_CEPH2TO0_PREG			0x0FB148#define SIERRA_TAU_EN_CEPH5TO3_PREG			0x0FC149#define SIERRA_DEQ_ALUT0				0x108150#define SIERRA_DEQ_ALUT1				0x109151#define SIERRA_DEQ_ALUT2				0x10A152#define SIERRA_DEQ_ALUT3				0x10B153#define SIERRA_DEQ_ALUT4				0x10C154#define SIERRA_DEQ_ALUT5				0x10D155#define SIERRA_DEQ_ALUT6				0x10E156#define SIERRA_DEQ_ALUT7				0x10F157#define SIERRA_DEQ_ALUT8				0x110158#define SIERRA_DEQ_ALUT9				0x111159#define SIERRA_DEQ_ALUT10				0x112160#define SIERRA_DEQ_ALUT11				0x113161#define SIERRA_DEQ_ALUT12				0x114162#define SIERRA_DEQ_ALUT13				0x115163#define SIERRA_OEPH_EN_CTRL_PREG			0x124164#define SIERRA_DEQ_DFETAP_CTRL_PREG			0x128165#define SIERRA_DEQ_DFETAP0				0x129166#define SIERRA_DEQ_DFETAP1				0x12B167#define SIERRA_DEQ_DFETAP2				0x12D168#define SIERRA_DEQ_DFETAP3				0x12F169#define SIERRA_DEQ_DFETAP4				0x131170#define SIERRA_DFE_EN_1010_IGNORE_PREG			0x134171#define SIERRA_DEQ_PRECUR_PREG				0x138172#define SIERRA_DEQ_POSTCUR_PREG				0x140173#define SIERRA_DEQ_POSTCUR_DECR_PREG			0x142174#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG		0x150175#define SIERRA_DEQ_TAU_CTRL2_PREG			0x151176#define SIERRA_DEQ_TAU_CTRL3_PREG			0x152177#define SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG		0x158178#define SIERRA_DEQ_CONCUR_EPIOFFSET_MODE_PREG		0x159179#define SIERRA_DEQ_OPENEYE_CTRL_PREG			0x15C180#define SIERRA_DEQ_PICTRL_PREG				0x161181#define SIERRA_CPICAL_TMRVAL_MODE1_PREG			0x170182#define SIERRA_CPICAL_TMRVAL_MODE0_PREG			0x171183#define SIERRA_CPICAL_PICNT_MODE1_PREG			0x174184#define SIERRA_CPI_OUTBUF_RATESEL_PREG			0x17C185#define SIERRA_CPI_RESBIAS_BIN_PREG			0x17E186#define SIERRA_CPI_TRIM_PREG				0x17F187#define SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG		0x183188#define SIERRA_CPICAL_RES_STARTCODE_MODE01_PREG		0x184189#define SIERRA_EPI_CTRL_PREG				0x187190#define SIERRA_LFPSDET_SUPPORT_PREG			0x188191#define SIERRA_LFPSFILT_NS_PREG				0x18A192#define SIERRA_LFPSFILT_RD_PREG				0x18B193#define SIERRA_LFPSFILT_MP_PREG				0x18C194#define SIERRA_SIGDET_SUPPORT_PREG			0x190195#define SIERRA_SDFILT_H2L_A_PREG			0x191196#define SIERRA_SDFILT_L2H_PREG				0x193197#define SIERRA_RXBUFFER_CTLECTRL_PREG			0x19E198#define SIERRA_RXBUFFER_RCDFECTRL_PREG			0x19F199#define SIERRA_RXBUFFER_DFECTRL_PREG			0x1A0200#define SIERRA_LN_SPARE_REG_PREG			0x1B0201#define SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG		0x14F202#define SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG		0x150203 204/* PHY PCS common registers */205#define SIERRA_PHY_PCS_COMMON_OFFSET(block_offset)	\206				     (0xc000 << (block_offset))207#define SIERRA_PHY_PIPE_CMN_CTRL1			0x0208#define SIERRA_PHY_PLL_CFG				0xe209 210/* PHY PCS lane registers */211#define SIERRA_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset)	\212				       ((0xD000 << (block_offset)) +	\213				       (((ln) << 8) << (reg_offset)))214 215#define SIERRA_PHY_ISO_LINK_CTRL			0xB216 217/* PHY PMA common registers */218#define SIERRA_PHY_PMA_COMMON_OFFSET(block_offset)	\219				     (0xE000 << (block_offset))220#define SIERRA_PHY_PMA_CMN_CTRL				0x000221 222/* PHY PMA lane registers */223#define SIERRA_PHY_PMA_LANE_CDB_OFFSET(ln, block_offset, reg_offset)	\224				       ((0xF000 << (block_offset)) +	\225				       (((ln) << 8) << (reg_offset)))226 227#define SIERRA_PHY_PMA_XCVR_CTRL			0x000228 229#define SIERRA_MACRO_ID					0x00007364230#define SIERRA_MAX_LANES				16231#define PLL_LOCK_TIME					100000232 233#define CDNS_SIERRA_OUTPUT_CLOCKS			3234#define CDNS_SIERRA_INPUT_CLOCKS			3235enum cdns_sierra_clock_input {236	PHY_CLK,237	CMN_REFCLK_DIG_DIV,238	CMN_REFCLK1_DIG_DIV,239};240 241#define SIERRA_NUM_CMN_PLLC				2242#define SIERRA_NUM_CMN_PLLC_PARENTS			2243 244static const struct reg_field macro_id_type =245				REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15);246static const struct reg_field phy_pll_cfg_1 =247				REG_FIELD(SIERRA_PHY_PLL_CFG, 1, 1);248static const struct reg_field pma_cmn_ready =249				REG_FIELD(SIERRA_PHY_PMA_CMN_CTRL, 0, 0);250static const struct reg_field pllctrl_lock =251				REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, 0);252static const struct reg_field phy_iso_link_ctrl_1 =253				REG_FIELD(SIERRA_PHY_ISO_LINK_CTRL, 1, 1);254static const struct reg_field cmn_plllc_clk1outdiv_preg =255				REG_FIELD(SIERRA_CMN_PLLLC_CLK1_PREG, 0, 6);256static const struct reg_field cmn_plllc_clk1_en_preg =257				REG_FIELD(SIERRA_CMN_PLLLC_CLK1_PREG, 12, 12);258 259static const char * const clk_names[] = {260	[CDNS_SIERRA_PLL_CMNLC] = "pll_cmnlc",261	[CDNS_SIERRA_PLL_CMNLC1] = "pll_cmnlc1",262	[CDNS_SIERRA_DERIVED_REFCLK] = "refclk_der",263};264 265enum cdns_sierra_cmn_plllc {266	CMN_PLLLC,267	CMN_PLLLC1,268};269 270struct cdns_sierra_pll_mux_reg_fields {271	struct reg_field	pfdclk_sel_preg;272	struct reg_field	plllc1en_field;273	struct reg_field	termen_field;274};275 276static const struct cdns_sierra_pll_mux_reg_fields cmn_plllc_pfdclk1_sel_preg[] = {277	[CMN_PLLLC] = {278		.pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC_GEN_PREG, 1, 1),279		.plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 8, 8),280		.termen_field = REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, 0),281	},282	[CMN_PLLLC1] = {283		.pfdclk_sel_preg = REG_FIELD(SIERRA_CMN_PLLLC1_GEN_PREG, 1, 1),284		.plllc1en_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 8, 8),285		.termen_field = REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0),286	},287};288 289struct cdns_sierra_pll_mux {290	struct clk_hw		hw;291	struct regmap_field	*pfdclk_sel_preg;292	struct regmap_field	*plllc1en_field;293	struct regmap_field	*termen_field;294	struct clk_init_data	clk_data;295};296 297#define to_cdns_sierra_pll_mux(_hw)	\298			container_of(_hw, struct cdns_sierra_pll_mux, hw)299 300#define PLL0_REFCLK_NAME "pll0_refclk"301#define PLL1_REFCLK_NAME "pll1_refclk"302 303static const struct clk_parent_data pll_mux_parent_data[][SIERRA_NUM_CMN_PLLC_PARENTS] = {304	[CMN_PLLLC] = {305		{ .fw_name = PLL0_REFCLK_NAME },306		{ .fw_name = PLL1_REFCLK_NAME }307	},308	[CMN_PLLLC1] = {309		{ .fw_name = PLL1_REFCLK_NAME },310		{ .fw_name = PLL0_REFCLK_NAME }311	},312};313 314static const u32 cdns_sierra_pll_mux_table[][SIERRA_NUM_CMN_PLLC_PARENTS] = {315	[CMN_PLLLC] = { 0, 1 },316	[CMN_PLLLC1] = { 1, 0 },317};318 319struct cdns_sierra_derived_refclk {320	struct clk_hw           hw;321	struct regmap_field     *cmn_plllc_clk1outdiv_preg;322	struct regmap_field     *cmn_plllc_clk1_en_preg;323	struct clk_init_data	clk_data;324};325 326#define to_cdns_sierra_derived_refclk(_hw)	\327			container_of(_hw, struct cdns_sierra_derived_refclk, hw)328 329enum cdns_sierra_phy_type {330	TYPE_NONE,331	TYPE_PCIE,332	TYPE_USB,333	TYPE_SGMII,334	TYPE_QSGMII335};336 337enum cdns_sierra_ssc_mode {338	NO_SSC,339	EXTERNAL_SSC,340	INTERNAL_SSC341};342 343struct cdns_sierra_inst {344	struct phy *phy;345	enum cdns_sierra_phy_type phy_type;346	u32 num_lanes;347	u32 mlane;348	struct reset_control *lnk_rst;349	enum cdns_sierra_ssc_mode ssc_mode;350};351 352struct cdns_reg_pairs {353	u16 val;354	u32 off;355};356 357struct cdns_sierra_vals {358	const struct cdns_reg_pairs *reg_pairs;359	u32 num_regs;360};361 362struct cdns_sierra_data {363	u32 id_value;364	u8 block_offset_shift;365	u8 reg_offset_shift;366	const struct cdns_sierra_vals *pcs_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]367						   [NUM_SSC_MODE];368	const struct cdns_sierra_vals *phy_pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]369						      [NUM_SSC_MODE];370	const struct cdns_sierra_vals *pma_cmn_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]371						   [NUM_SSC_MODE];372	const struct cdns_sierra_vals *pma_ln_vals[NUM_PHY_TYPE][NUM_PHY_TYPE]373						  [NUM_SSC_MODE];374};375 376struct cdns_regmap_cdb_context {377	struct device *dev;378	void __iomem *base;379	u8 reg_offset_shift;380};381 382struct cdns_sierra_phy {383	struct device *dev;384	const struct cdns_sierra_data *init_data;385	struct cdns_sierra_inst phys[SIERRA_MAX_LANES];386	struct reset_control *phy_rst;387	struct reset_control *apb_rst;388	struct regmap *regmap_lane_cdb[SIERRA_MAX_LANES];389	struct regmap *regmap_phy_pcs_common_cdb;390	struct regmap *regmap_phy_pcs_lane_cdb[SIERRA_MAX_LANES];391	struct regmap *regmap_phy_pma_common_cdb;392	struct regmap *regmap_phy_pma_lane_cdb[SIERRA_MAX_LANES];393	struct regmap *regmap_common_cdb;394	struct regmap_field *macro_id_type;395	struct regmap_field *phy_pll_cfg_1;396	struct regmap_field *pma_cmn_ready;397	struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES];398	struct regmap_field *phy_iso_link_ctrl_1[SIERRA_MAX_LANES];399	struct regmap_field *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_CMN_PLLC];400	struct regmap_field *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC];401	struct regmap_field *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC];402	struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS];403	int nsubnodes;404	u32 num_lanes;405	bool autoconf;406	int already_configured;407	struct clk *pll_clks[SIERRA_NUM_CMN_PLLC];408	struct clk_hw_onecell_data clk_data;409};410 411static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val)412{413	struct cdns_regmap_cdb_context *ctx = context;414	u32 offset = reg << ctx->reg_offset_shift;415 416	writew(val, ctx->base + offset);417 418	return 0;419}420 421static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val)422{423	struct cdns_regmap_cdb_context *ctx = context;424	u32 offset = reg << ctx->reg_offset_shift;425 426	*val = readw(ctx->base + offset);427	return 0;428}429 430#define SIERRA_LANE_CDB_REGMAP_CONF(n) \431{ \432	.name = "sierra_lane" n "_cdb", \433	.reg_stride = 1, \434	.fast_io = true, \435	.reg_write = cdns_regmap_write, \436	.reg_read = cdns_regmap_read, \437}438 439static const struct regmap_config cdns_sierra_lane_cdb_config[] = {440	SIERRA_LANE_CDB_REGMAP_CONF("0"),441	SIERRA_LANE_CDB_REGMAP_CONF("1"),442	SIERRA_LANE_CDB_REGMAP_CONF("2"),443	SIERRA_LANE_CDB_REGMAP_CONF("3"),444	SIERRA_LANE_CDB_REGMAP_CONF("4"),445	SIERRA_LANE_CDB_REGMAP_CONF("5"),446	SIERRA_LANE_CDB_REGMAP_CONF("6"),447	SIERRA_LANE_CDB_REGMAP_CONF("7"),448	SIERRA_LANE_CDB_REGMAP_CONF("8"),449	SIERRA_LANE_CDB_REGMAP_CONF("9"),450	SIERRA_LANE_CDB_REGMAP_CONF("10"),451	SIERRA_LANE_CDB_REGMAP_CONF("11"),452	SIERRA_LANE_CDB_REGMAP_CONF("12"),453	SIERRA_LANE_CDB_REGMAP_CONF("13"),454	SIERRA_LANE_CDB_REGMAP_CONF("14"),455	SIERRA_LANE_CDB_REGMAP_CONF("15"),456};457 458static const struct regmap_config cdns_sierra_common_cdb_config = {459	.name = "sierra_common_cdb",460	.reg_stride = 1,461	.fast_io = true,462	.reg_write = cdns_regmap_write,463	.reg_read = cdns_regmap_read,464};465 466static const struct regmap_config cdns_sierra_phy_pcs_cmn_cdb_config = {467	.name = "sierra_phy_pcs_cmn_cdb",468	.reg_stride = 1,469	.fast_io = true,470	.reg_write = cdns_regmap_write,471	.reg_read = cdns_regmap_read,472};473 474#define SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF(n) \475{ \476	.name = "sierra_phy_pcs_lane" n "_cdb", \477	.reg_stride = 1, \478	.fast_io = true, \479	.reg_write = cdns_regmap_write, \480	.reg_read = cdns_regmap_read, \481}482 483static const struct regmap_config cdns_sierra_phy_pcs_lane_cdb_config[] = {484	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("0"),485	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("1"),486	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("2"),487	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("3"),488	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("4"),489	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("5"),490	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("6"),491	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("7"),492	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("8"),493	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("9"),494	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("10"),495	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("11"),496	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("12"),497	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("13"),498	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("14"),499	SIERRA_PHY_PCS_LANE_CDB_REGMAP_CONF("15"),500};501 502static const struct regmap_config cdns_sierra_phy_pma_cmn_cdb_config = {503	.name = "sierra_phy_pma_cmn_cdb",504	.reg_stride = 1,505	.fast_io = true,506	.reg_write = cdns_regmap_write,507	.reg_read = cdns_regmap_read,508};509 510#define SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF(n) \511{ \512	.name = "sierra_phy_pma_lane" n "_cdb", \513	.reg_stride = 1, \514	.fast_io = true, \515	.reg_write = cdns_regmap_write, \516	.reg_read = cdns_regmap_read, \517}518 519static const struct regmap_config cdns_sierra_phy_pma_lane_cdb_config[] = {520	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("0"),521	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("1"),522	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("2"),523	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("3"),524	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("4"),525	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("5"),526	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("6"),527	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("7"),528	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("8"),529	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("9"),530	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("10"),531	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("11"),532	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("12"),533	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("13"),534	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("14"),535	SIERRA_PHY_PMA_LANE_CDB_REGMAP_CONF("15"),536};537 538static int cdns_sierra_phy_init(struct phy *gphy)539{540	struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);541	struct cdns_sierra_phy *phy = dev_get_drvdata(gphy->dev.parent);542	const struct cdns_sierra_data *init_data = phy->init_data;543	const struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;544	enum cdns_sierra_phy_type phy_type = ins->phy_type;545	const struct cdns_sierra_vals *phy_pma_ln_vals;546	enum cdns_sierra_ssc_mode ssc = ins->ssc_mode;547	const struct cdns_sierra_vals *pcs_cmn_vals;548	const struct cdns_reg_pairs *reg_pairs;549	struct regmap *regmap;550	u32 num_regs;551	int i, j;552 553	/* Initialise the PHY registers, unless auto configured */554	if (phy->autoconf || phy->already_configured || phy->nsubnodes > 1)555		return 0;556 557	clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000);558	clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);559 560	/* PHY PCS common registers configurations */561	pcs_cmn_vals = init_data->pcs_cmn_vals[phy_type][TYPE_NONE][ssc];562	if (pcs_cmn_vals) {563		reg_pairs = pcs_cmn_vals->reg_pairs;564		num_regs = pcs_cmn_vals->num_regs;565		regmap = phy->regmap_phy_pcs_common_cdb;566		for (i = 0; i < num_regs; i++)567			regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);568	}569 570	/* PHY PMA lane registers configurations */571	phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_type][TYPE_NONE][ssc];572	if (phy_pma_ln_vals) {573		reg_pairs = phy_pma_ln_vals->reg_pairs;574		num_regs = phy_pma_ln_vals->num_regs;575		for (i = 0; i < ins->num_lanes; i++) {576			regmap = phy->regmap_phy_pma_lane_cdb[i + ins->mlane];577			for (j = 0; j < num_regs; j++)578				regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);579		}580	}581 582	/* PMA common registers configurations */583	pma_cmn_vals = init_data->pma_cmn_vals[phy_type][TYPE_NONE][ssc];584	if (pma_cmn_vals) {585		reg_pairs = pma_cmn_vals->reg_pairs;586		num_regs = pma_cmn_vals->num_regs;587		regmap = phy->regmap_common_cdb;588		for (i = 0; i < num_regs; i++)589			regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);590	}591 592	/* PMA lane registers configurations */593	pma_ln_vals = init_data->pma_ln_vals[phy_type][TYPE_NONE][ssc];594	if (pma_ln_vals) {595		reg_pairs = pma_ln_vals->reg_pairs;596		num_regs = pma_ln_vals->num_regs;597		for (i = 0; i < ins->num_lanes; i++) {598			regmap = phy->regmap_lane_cdb[i + ins->mlane];599			for (j = 0; j < num_regs; j++)600				regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);601		}602	}603 604	return 0;605}606 607static int cdns_sierra_phy_on(struct phy *gphy)608{609	struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent);610	struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);611	struct device *dev = sp->dev;612	u32 val;613	int ret;614 615	if (sp->nsubnodes == 1) {616		/* Take the PHY out of reset */617		ret = reset_control_deassert(sp->phy_rst);618		if (ret) {619			dev_err(dev, "Failed to take the PHY out of reset\n");620			return ret;621		}622	}623 624	/* Take the PHY lane group out of reset */625	ret = reset_control_deassert(ins->lnk_rst);626	if (ret) {627		dev_err(dev, "Failed to take the PHY lane out of reset\n");628		return ret;629	}630 631	if (ins->phy_type == TYPE_PCIE || ins->phy_type == TYPE_USB) {632		ret = regmap_field_read_poll_timeout(sp->phy_iso_link_ctrl_1[ins->mlane],633						     val, !val, 1000, PLL_LOCK_TIME);634		if (ret) {635			dev_err(dev, "Timeout waiting for PHY status ready\n");636			return ret;637		}638	}639 640	/*641	 * Wait for cmn_ready assertion642	 * PHY_PMA_CMN_CTRL[0] == 1643	 */644	ret = regmap_field_read_poll_timeout(sp->pma_cmn_ready, val, val,645					     1000, PLL_LOCK_TIME);646	if (ret) {647		dev_err(dev, "Timeout waiting for CMN ready\n");648		return ret;649	}650 651	ret = regmap_field_read_poll_timeout(sp->pllctrl_lock[ins->mlane],652					     val, val, 1000, PLL_LOCK_TIME);653	if (ret < 0)654		dev_err(dev, "PLL lock of lane failed\n");655 656	return ret;657}658 659static int cdns_sierra_phy_off(struct phy *gphy)660{661	struct cdns_sierra_inst *ins = phy_get_drvdata(gphy);662 663	return reset_control_assert(ins->lnk_rst);664}665 666static int cdns_sierra_phy_reset(struct phy *gphy)667{668	struct cdns_sierra_phy *sp = dev_get_drvdata(gphy->dev.parent);669 670	reset_control_assert(sp->phy_rst);671	reset_control_deassert(sp->phy_rst);672	return 0;673};674 675static const struct phy_ops ops = {676	.init		= cdns_sierra_phy_init,677	.power_on	= cdns_sierra_phy_on,678	.power_off	= cdns_sierra_phy_off,679	.reset		= cdns_sierra_phy_reset,680	.owner		= THIS_MODULE,681};682 683static int cdns_sierra_noop_phy_on(struct phy *gphy)684{685	usleep_range(5000, 10000);686 687	return 0;688}689 690static const struct phy_ops noop_ops = {691	.power_on	= cdns_sierra_noop_phy_on,692	.owner		= THIS_MODULE,693};694 695static u8 cdns_sierra_pll_mux_get_parent(struct clk_hw *hw)696{697	struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw);698	struct regmap_field *plllc1en_field = mux->plllc1en_field;699	struct regmap_field *termen_field = mux->termen_field;700	struct regmap_field *field = mux->pfdclk_sel_preg;701	unsigned int val;702	int index;703 704	regmap_field_read(field, &val);705 706	if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1])) {707		index = clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC1], 0, val);708		if (index == 1) {709			regmap_field_write(plllc1en_field, 1);710			regmap_field_write(termen_field, 1);711		}712	} else {713		index = clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table[CMN_PLLLC], 0, val);714	}715 716	return index;717}718 719static int cdns_sierra_pll_mux_set_parent(struct clk_hw *hw, u8 index)720{721	struct cdns_sierra_pll_mux *mux = to_cdns_sierra_pll_mux(hw);722	struct regmap_field *plllc1en_field = mux->plllc1en_field;723	struct regmap_field *termen_field = mux->termen_field;724	struct regmap_field *field = mux->pfdclk_sel_preg;725	int val, ret;726 727	ret = regmap_field_write(plllc1en_field, 0);728	ret |= regmap_field_write(termen_field, 0);729	if (index == 1) {730		ret |= regmap_field_write(plllc1en_field, 1);731		ret |= regmap_field_write(termen_field, 1);732	}733 734	if (strstr(clk_hw_get_name(hw), clk_names[CDNS_SIERRA_PLL_CMNLC1]))735		val = cdns_sierra_pll_mux_table[CMN_PLLLC1][index];736	else737		val = cdns_sierra_pll_mux_table[CMN_PLLLC][index];738 739	ret |= regmap_field_write(field, val);740 741	return ret;742}743 744static const struct clk_ops cdns_sierra_pll_mux_ops = {745	.determine_rate = __clk_mux_determine_rate,746	.set_parent = cdns_sierra_pll_mux_set_parent,747	.get_parent = cdns_sierra_pll_mux_get_parent,748};749 750static int cdns_sierra_pll_mux_register(struct cdns_sierra_phy *sp,751					struct regmap_field *pfdclk1_sel_field,752					struct regmap_field *plllc1en_field,753					struct regmap_field *termen_field,754					int clk_index)755{756	struct cdns_sierra_pll_mux *mux;757	struct device *dev = sp->dev;758	struct clk_init_data *init;759	char clk_name[100];760	int ret;761 762	mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);763	if (!mux)764		return -ENOMEM;765 766	snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), clk_names[clk_index]);767 768	init = &mux->clk_data;769 770	init->ops = &cdns_sierra_pll_mux_ops;771	init->flags = CLK_SET_RATE_NO_REPARENT;772	init->parent_data = pll_mux_parent_data[clk_index];773	init->num_parents = SIERRA_NUM_CMN_PLLC_PARENTS;774	init->name = clk_name;775 776	mux->pfdclk_sel_preg = pfdclk1_sel_field;777	mux->plllc1en_field = plllc1en_field;778	mux->termen_field = termen_field;779	mux->hw.init = init;780 781	ret = devm_clk_hw_register(dev, &mux->hw);782	if (ret)783		return ret;784 785	sp->clk_data.hws[clk_index] = &mux->hw;786 787	sp->pll_clks[clk_index] = devm_clk_hw_get_clk(dev, &mux->hw,788						      clk_names[clk_index]);789 790	return 0;791}792 793static int cdns_sierra_phy_register_pll_mux(struct cdns_sierra_phy *sp)794{795	struct regmap_field *pfdclk1_sel_field;796	struct regmap_field *plllc1en_field;797	struct regmap_field *termen_field;798	struct device *dev = sp->dev;799	int ret = 0, i, clk_index;800 801	clk_index = CDNS_SIERRA_PLL_CMNLC;802	for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++, clk_index++) {803		pfdclk1_sel_field = sp->cmn_plllc_pfdclk1_sel_preg[i];804		plllc1en_field = sp->cmn_refrcv_refclk_plllc1en_preg[i];805		termen_field = sp->cmn_refrcv_refclk_termen_preg[i];806 807		ret = cdns_sierra_pll_mux_register(sp, pfdclk1_sel_field, plllc1en_field,808						   termen_field, clk_index);809		if (ret) {810			dev_err(dev, "Fail to register cmn plllc mux\n");811			return ret;812		}813	}814 815	return 0;816}817 818static int cdns_sierra_derived_refclk_enable(struct clk_hw *hw)819{820	struct cdns_sierra_derived_refclk *derived_refclk = to_cdns_sierra_derived_refclk(hw);821 822	regmap_field_write(derived_refclk->cmn_plllc_clk1_en_preg, 0x1);823 824	/* Programming to get 100Mhz clock output in ref_der_clk_out 5GHz VCO/50 = 100MHz */825	regmap_field_write(derived_refclk->cmn_plllc_clk1outdiv_preg, 0x2E);826 827	return 0;828}829 830static void cdns_sierra_derived_refclk_disable(struct clk_hw *hw)831{832	struct cdns_sierra_derived_refclk *derived_refclk = to_cdns_sierra_derived_refclk(hw);833 834	regmap_field_write(derived_refclk->cmn_plllc_clk1_en_preg, 0);835}836 837static int cdns_sierra_derived_refclk_is_enabled(struct clk_hw *hw)838{839	struct cdns_sierra_derived_refclk *derived_refclk = to_cdns_sierra_derived_refclk(hw);840	int val;841 842	regmap_field_read(derived_refclk->cmn_plllc_clk1_en_preg, &val);843 844	return !!val;845}846 847static const struct clk_ops cdns_sierra_derived_refclk_ops = {848	.enable = cdns_sierra_derived_refclk_enable,849	.disable = cdns_sierra_derived_refclk_disable,850	.is_enabled = cdns_sierra_derived_refclk_is_enabled,851};852 853static int cdns_sierra_derived_refclk_register(struct cdns_sierra_phy *sp)854{855	struct cdns_sierra_derived_refclk *derived_refclk;856	struct device *dev = sp->dev;857	struct regmap_field *field;858	struct clk_init_data *init;859	struct regmap *regmap;860	char clk_name[100];861	int ret;862 863	derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL);864	if (!derived_refclk)865		return -ENOMEM;866 867	snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),868		 clk_names[CDNS_SIERRA_DERIVED_REFCLK]);869 870	init = &derived_refclk->clk_data;871 872	init->ops = &cdns_sierra_derived_refclk_ops;873	init->flags = 0;874	init->name = clk_name;875 876	regmap = sp->regmap_common_cdb;877 878	field = devm_regmap_field_alloc(dev, regmap, cmn_plllc_clk1outdiv_preg);879	if (IS_ERR(field)) {880		dev_err(dev, "cmn_plllc_clk1outdiv_preg reg field init failed\n");881		return PTR_ERR(field);882	}883	derived_refclk->cmn_plllc_clk1outdiv_preg = field;884 885	field = devm_regmap_field_alloc(dev, regmap, cmn_plllc_clk1_en_preg);886	if (IS_ERR(field)) {887		dev_err(dev, "cmn_plllc_clk1_en_preg reg field init failed\n");888		return PTR_ERR(field);889	}890	derived_refclk->cmn_plllc_clk1_en_preg = field;891 892	derived_refclk->hw.init = init;893 894	ret = devm_clk_hw_register(dev, &derived_refclk->hw);895	if (ret)896		return ret;897 898	sp->clk_data.hws[CDNS_SIERRA_DERIVED_REFCLK] = &derived_refclk->hw;899 900	return 0;901}902 903static void cdns_sierra_clk_unregister(struct cdns_sierra_phy *sp)904{905	struct device *dev = sp->dev;906	struct device_node *node = dev->of_node;907 908	of_clk_del_provider(node);909}910 911static int cdns_sierra_clk_register(struct cdns_sierra_phy *sp)912{913	struct device *dev = sp->dev;914	struct device_node *node = dev->of_node;915	int ret;916 917	ret = cdns_sierra_phy_register_pll_mux(sp);918	if (ret) {919		dev_err(dev, "Failed to pll mux clocks\n");920		return ret;921	}922 923	ret = cdns_sierra_derived_refclk_register(sp);924	if (ret) {925		dev_err(dev, "Failed to register derived refclk\n");926		return ret;927	}928 929	sp->clk_data.num = CDNS_SIERRA_OUTPUT_CLOCKS;930	ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,931				     &sp->clk_data);932	if (ret)933		dev_err(dev, "Failed to add clock provider: %s\n", node->name);934 935	return ret;936}937 938static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst,939				    struct device_node *child)940{941	u32 phy_type;942 943	if (of_property_read_u32(child, "reg", &inst->mlane))944		return -EINVAL;945 946	if (of_property_read_u32(child, "cdns,num-lanes", &inst->num_lanes))947		return -EINVAL;948 949	if (of_property_read_u32(child, "cdns,phy-type", &phy_type))950		return -EINVAL;951 952	switch (phy_type) {953	case PHY_TYPE_PCIE:954		inst->phy_type = TYPE_PCIE;955		break;956	case PHY_TYPE_USB3:957		inst->phy_type = TYPE_USB;958		break;959	case PHY_TYPE_SGMII:960		inst->phy_type = TYPE_SGMII;961		break;962	case PHY_TYPE_QSGMII:963		inst->phy_type = TYPE_QSGMII;964		break;965	default:966		return -EINVAL;967	}968 969	inst->ssc_mode = EXTERNAL_SSC;970	of_property_read_u32(child, "cdns,ssc-mode", &inst->ssc_mode);971 972	return 0;973}974 975static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base,976				       u32 block_offset, u8 reg_offset_shift,977				       const struct regmap_config *config)978{979	struct cdns_regmap_cdb_context *ctx;980 981	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);982	if (!ctx)983		return ERR_PTR(-ENOMEM);984 985	ctx->dev = dev;986	ctx->base = base + block_offset;987	ctx->reg_offset_shift = reg_offset_shift;988 989	return devm_regmap_init(dev, NULL, ctx, config);990}991 992static int cdns_regfield_init(struct cdns_sierra_phy *sp)993{994	struct device *dev = sp->dev;995	struct regmap_field *field;996	struct reg_field reg_field;997	struct regmap *regmap;998	int i;999 1000	regmap = sp->regmap_common_cdb;1001	field = devm_regmap_field_alloc(dev, regmap, macro_id_type);1002	if (IS_ERR(field)) {1003		dev_err(dev, "MACRO_ID_TYPE reg field init failed\n");1004		return PTR_ERR(field);1005	}1006	sp->macro_id_type = field;1007 1008	for (i = 0; i < SIERRA_NUM_CMN_PLLC; i++) {1009		reg_field = cmn_plllc_pfdclk1_sel_preg[i].pfdclk_sel_preg;1010		field = devm_regmap_field_alloc(dev, regmap, reg_field);1011		if (IS_ERR(field)) {1012			dev_err(dev, "PLLLC%d_PFDCLK1_SEL failed\n", i);1013			return PTR_ERR(field);1014		}1015		sp->cmn_plllc_pfdclk1_sel_preg[i] = field;1016 1017		reg_field = cmn_plllc_pfdclk1_sel_preg[i].plllc1en_field;1018		field = devm_regmap_field_alloc(dev, regmap, reg_field);1019		if (IS_ERR(field)) {1020			dev_err(dev, "REFRCV%d_REFCLK_PLLLC1EN failed\n", i);1021			return PTR_ERR(field);1022		}1023		sp->cmn_refrcv_refclk_plllc1en_preg[i] = field;1024 1025		reg_field = cmn_plllc_pfdclk1_sel_preg[i].termen_field;1026		field = devm_regmap_field_alloc(dev, regmap, reg_field);1027		if (IS_ERR(field)) {1028			dev_err(dev, "REFRCV%d_REFCLK_TERMEN failed\n", i);1029			return PTR_ERR(field);1030		}1031		sp->cmn_refrcv_refclk_termen_preg[i] = field;1032	}1033 1034	regmap = sp->regmap_phy_pcs_common_cdb;1035	field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1);1036	if (IS_ERR(field)) {1037		dev_err(dev, "PHY_PLL_CFG_1 reg field init failed\n");1038		return PTR_ERR(field);1039	}1040	sp->phy_pll_cfg_1 = field;1041 1042	regmap = sp->regmap_phy_pma_common_cdb;1043	field = devm_regmap_field_alloc(dev, regmap, pma_cmn_ready);1044	if (IS_ERR(field)) {1045		dev_err(dev, "PHY_PMA_CMN_CTRL reg field init failed\n");1046		return PTR_ERR(field);1047	}1048	sp->pma_cmn_ready = field;1049 1050	for (i = 0; i < SIERRA_MAX_LANES; i++) {1051		regmap = sp->regmap_lane_cdb[i];1052		field = devm_regmap_field_alloc(dev, regmap, pllctrl_lock);1053		if (IS_ERR(field)) {1054			dev_err(dev, "P%d_ENABLE reg field init failed\n", i);1055			return PTR_ERR(field);1056		}1057		sp->pllctrl_lock[i] = field;1058	}1059 1060	for (i = 0; i < SIERRA_MAX_LANES; i++) {1061		regmap = sp->regmap_phy_pcs_lane_cdb[i];1062		field = devm_regmap_field_alloc(dev, regmap, phy_iso_link_ctrl_1);1063		if (IS_ERR(field)) {1064			dev_err(dev, "PHY_ISO_LINK_CTRL reg field init for lane %d failed\n", i);1065			return PTR_ERR(field);1066		}1067		sp->phy_iso_link_ctrl_1[i] = field;1068	}1069 1070	return 0;1071}1072 1073static int cdns_regmap_init_blocks(struct cdns_sierra_phy *sp,1074				   void __iomem *base, u8 block_offset_shift,1075				   u8 reg_offset_shift)1076{1077	struct device *dev = sp->dev;1078	struct regmap *regmap;1079	u32 block_offset;1080	int i;1081 1082	for (i = 0; i < SIERRA_MAX_LANES; i++) {1083		block_offset = SIERRA_LANE_CDB_OFFSET(i, block_offset_shift,1084						      reg_offset_shift);1085		regmap = cdns_regmap_init(dev, base, block_offset,1086					  reg_offset_shift,1087					  &cdns_sierra_lane_cdb_config[i]);1088		if (IS_ERR(regmap)) {1089			dev_err(dev, "Failed to init lane CDB regmap\n");1090			return PTR_ERR(regmap);1091		}1092		sp->regmap_lane_cdb[i] = regmap;1093	}1094 1095	regmap = cdns_regmap_init(dev, base, SIERRA_COMMON_CDB_OFFSET,1096				  reg_offset_shift,1097				  &cdns_sierra_common_cdb_config);1098	if (IS_ERR(regmap)) {1099		dev_err(dev, "Failed to init common CDB regmap\n");1100		return PTR_ERR(regmap);1101	}1102	sp->regmap_common_cdb = regmap;1103 1104	block_offset = SIERRA_PHY_PCS_COMMON_OFFSET(block_offset_shift);1105	regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift,1106				  &cdns_sierra_phy_pcs_cmn_cdb_config);1107	if (IS_ERR(regmap)) {1108		dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");1109		return PTR_ERR(regmap);1110	}1111	sp->regmap_phy_pcs_common_cdb = regmap;1112 1113	for (i = 0; i < SIERRA_MAX_LANES; i++) {1114		block_offset = SIERRA_PHY_PCS_LANE_CDB_OFFSET(i, block_offset_shift,1115							      reg_offset_shift);1116		regmap = cdns_regmap_init(dev, base, block_offset,1117					  reg_offset_shift,1118					  &cdns_sierra_phy_pcs_lane_cdb_config[i]);1119		if (IS_ERR(regmap)) {1120			dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n");1121			return PTR_ERR(regmap);1122		}1123		sp->regmap_phy_pcs_lane_cdb[i] = regmap;1124	}1125 1126	block_offset = SIERRA_PHY_PMA_COMMON_OFFSET(block_offset_shift);1127	regmap = cdns_regmap_init(dev, base, block_offset, reg_offset_shift,1128				  &cdns_sierra_phy_pma_cmn_cdb_config);1129	if (IS_ERR(regmap)) {1130		dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");1131		return PTR_ERR(regmap);1132	}1133	sp->regmap_phy_pma_common_cdb = regmap;1134 1135	for (i = 0; i < SIERRA_MAX_LANES; i++) {1136		block_offset = SIERRA_PHY_PMA_LANE_CDB_OFFSET(i, block_offset_shift,1137							      reg_offset_shift);1138		regmap = cdns_regmap_init(dev, base, block_offset,1139					  reg_offset_shift,1140					  &cdns_sierra_phy_pma_lane_cdb_config[i]);1141		if (IS_ERR(regmap)) {1142			dev_err(dev, "Failed to init PHY PMA lane CDB regmap\n");1143			return PTR_ERR(regmap);1144		}1145		sp->regmap_phy_pma_lane_cdb[i] = regmap;1146	}1147 1148	return 0;1149}1150 1151static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,1152				      struct device *dev)1153{1154	struct clk *clk;1155	int ret;1156 1157	clk = devm_clk_get_optional(dev, "cmn_refclk_dig_div");1158	if (IS_ERR(clk)) {1159		dev_err(dev, "cmn_refclk_dig_div clock not found\n");1160		ret = PTR_ERR(clk);1161		return ret;1162	}1163	sp->input_clks[CMN_REFCLK_DIG_DIV] = clk;1164 1165	clk = devm_clk_get_optional(dev, "cmn_refclk1_dig_div");1166	if (IS_ERR(clk)) {1167		dev_err(dev, "cmn_refclk1_dig_div clock not found\n");1168		ret = PTR_ERR(clk);1169		return ret;1170	}1171	sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk;1172 1173	return 0;1174}1175 1176static int cdns_sierra_phy_clk(struct cdns_sierra_phy *sp)1177{1178	struct device *dev = sp->dev;1179	struct clk *clk;1180	int ret;1181 1182	clk = devm_clk_get_optional(dev, "phy_clk");1183	if (IS_ERR(clk)) {1184		dev_err(dev, "failed to get clock phy_clk\n");1185		return PTR_ERR(clk);1186	}1187	sp->input_clks[PHY_CLK] = clk;1188 1189	ret = clk_prepare_enable(sp->input_clks[PHY_CLK]);1190	if (ret)1191		return ret;1192 1193	return 0;1194}1195 1196static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp)1197{1198	int ret;1199 1200	ret = clk_prepare_enable(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC]);1201	if (ret)1202		return ret;1203 1204	ret = clk_prepare_enable(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC1]);1205	if (ret)1206		goto err_pll_cmnlc1;1207 1208	return 0;1209 1210err_pll_cmnlc1:1211	clk_disable_unprepare(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC]);1212 1213	return ret;1214}1215 1216static void cdns_sierra_phy_disable_clocks(struct cdns_sierra_phy *sp)1217{1218	clk_disable_unprepare(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC1]);1219	clk_disable_unprepare(sp->pll_clks[CDNS_SIERRA_PLL_CMNLC]);1220	if (!sp->already_configured)1221		clk_disable_unprepare(sp->input_clks[PHY_CLK]);1222}1223 1224static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp,1225				      struct device *dev)1226{1227	struct reset_control *rst;1228 1229	rst = devm_reset_control_get_exclusive(dev, "sierra_reset");1230	if (IS_ERR(rst)) {1231		dev_err(dev, "failed to get reset\n");1232		return PTR_ERR(rst);1233	}1234	sp->phy_rst = rst;1235 1236	rst = devm_reset_control_get_optional_exclusive(dev, "sierra_apb");1237	if (IS_ERR(rst)) {1238		dev_err(dev, "failed to get apb reset\n");1239		return PTR_ERR(rst);1240	}1241	sp->apb_rst = rst;1242 1243	return 0;1244}1245 1246static int cdns_sierra_phy_configure_multilink(struct cdns_sierra_phy *sp)1247{1248	const struct cdns_sierra_vals *pma_cmn_vals, *pma_ln_vals;1249	const struct cdns_sierra_data *init_data = sp->init_data;1250	const struct cdns_sierra_vals *phy_pma_ln_vals;1251	const struct cdns_sierra_vals *pcs_cmn_vals;1252	enum cdns_sierra_phy_type phy_t1, phy_t2;1253	const struct cdns_reg_pairs *reg_pairs;1254	int i, j, node, mlane, num_lanes, ret;1255	enum cdns_sierra_ssc_mode ssc;1256	struct regmap *regmap;1257	u32 num_regs;1258 1259	/* Maximum 2 links (subnodes) are supported */1260	if (sp->nsubnodes != 2)1261		return -EINVAL;1262 1263	clk_set_rate(sp->input_clks[CMN_REFCLK_DIG_DIV], 25000000);1264	clk_set_rate(sp->input_clks[CMN_REFCLK1_DIG_DIV], 25000000);1265 1266	/* PHY configured to use both PLL LC and LC1 */1267	regmap_field_write(sp->phy_pll_cfg_1, 0x1);1268 1269	phy_t1 = sp->phys[0].phy_type;1270	phy_t2 = sp->phys[1].phy_type;1271 1272	/*1273	 * PHY configuration for multi-link operation is done in two steps.1274	 * e.g. Consider a case for a 4 lane PHY with PCIe using 2 lanes and QSGMII other 2 lanes.1275	 * Sierra PHY has 2 PLLs, viz. PLLLC and PLLLC1. So in this case, PLLLC is used for PCIe1276	 * and PLLLC1 is used for QSGMII. PHY is configured in two steps as described below.1277	 *1278	 * [1] For first step, phy_t1 = TYPE_PCIE and phy_t2 = TYPE_QSGMII1279	 *     So the register values are selected as [TYPE_PCIE][TYPE_QSGMII][ssc].1280	 *     This will configure PHY registers associated for PCIe (i.e. first protocol)1281	 *     involving PLLLC registers and registers for first 2 lanes of PHY.1282	 * [2] In second step, the variables phy_t1 and phy_t2 are swapped. So now,1283	 *     phy_t1 = TYPE_QSGMII and phy_t2 = TYPE_PCIE. And the register values are selected as1284	 *     [TYPE_QSGMII][TYPE_PCIE][ssc].1285	 *     This will configure PHY registers associated for QSGMII (i.e. second protocol)1286	 *     involving PLLLC1 registers and registers for other 2 lanes of PHY.1287	 *1288	 * This completes the PHY configuration for multilink operation. This approach enables1289	 * dividing the large number of PHY register configurations into protocol specific1290	 * smaller groups.1291	 */1292	for (node = 0; node < sp->nsubnodes; node++) {1293		if (node == 1) {1294			/*1295			 * If first link with phy_t1 is configured, then configure the PHY for1296			 * second link with phy_t2. Get the array values as [phy_t2][phy_t1][ssc].1297			 */1298			swap(phy_t1, phy_t2);1299		}1300 1301		mlane = sp->phys[node].mlane;1302		ssc = sp->phys[node].ssc_mode;1303		num_lanes = sp->phys[node].num_lanes;1304 1305		/* PHY PCS common registers configurations */1306		pcs_cmn_vals = init_data->pcs_cmn_vals[phy_t1][phy_t2][ssc];1307		if (pcs_cmn_vals) {1308			reg_pairs = pcs_cmn_vals->reg_pairs;1309			num_regs = pcs_cmn_vals->num_regs;1310			regmap = sp->regmap_phy_pcs_common_cdb;1311			for (i = 0; i < num_regs; i++)1312				regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);1313		}1314 1315		/* PHY PMA lane registers configurations */1316		phy_pma_ln_vals = init_data->phy_pma_ln_vals[phy_t1][phy_t2][ssc];1317		if (phy_pma_ln_vals) {1318			reg_pairs = phy_pma_ln_vals->reg_pairs;1319			num_regs = phy_pma_ln_vals->num_regs;1320			for (i = 0; i < num_lanes; i++) {1321				regmap = sp->regmap_phy_pma_lane_cdb[i + mlane];1322				for (j = 0; j < num_regs; j++)1323					regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);1324			}1325		}1326 1327		/* PMA common registers configurations */1328		pma_cmn_vals = init_data->pma_cmn_vals[phy_t1][phy_t2][ssc];1329		if (pma_cmn_vals) {1330			reg_pairs = pma_cmn_vals->reg_pairs;1331			num_regs = pma_cmn_vals->num_regs;1332			regmap = sp->regmap_common_cdb;1333			for (i = 0; i < num_regs; i++)1334				regmap_write(regmap, reg_pairs[i].off, reg_pairs[i].val);1335		}1336 1337		/* PMA lane registers configurations */1338		pma_ln_vals = init_data->pma_ln_vals[phy_t1][phy_t2][ssc];1339		if (pma_ln_vals) {1340			reg_pairs = pma_ln_vals->reg_pairs;1341			num_regs = pma_ln_vals->num_regs;1342			for (i = 0; i < num_lanes; i++) {1343				regmap = sp->regmap_lane_cdb[i + mlane];1344				for (j = 0; j < num_regs; j++)1345					regmap_write(regmap, reg_pairs[j].off, reg_pairs[j].val);1346			}1347		}1348 1349		if (phy_t1 == TYPE_SGMII || phy_t1 == TYPE_QSGMII)1350			reset_control_deassert(sp->phys[node].lnk_rst);1351	}1352 1353	/* Take the PHY out of reset */1354	ret = reset_control_deassert(sp->phy_rst);1355	if (ret)1356		return ret;1357 1358	return 0;1359}1360 1361static int cdns_sierra_phy_probe(struct platform_device *pdev)1362{1363	struct cdns_sierra_phy *sp;1364	struct phy_provider *phy_provider;1365	struct device *dev = &pdev->dev;1366	const struct cdns_sierra_data *data;1367	unsigned int id_value;1368	int ret, node = 0;1369	void __iomem *base;1370	struct device_node *dn = dev->of_node;1371 1372	if (of_get_child_count(dn) == 0)1373		return -ENODEV;1374 1375	/* Get init data for this PHY */1376	data = of_device_get_match_data(dev);1377	if (!data)1378		return -EINVAL;1379 1380	sp = devm_kzalloc(dev, struct_size(sp, clk_data.hws,1381					   CDNS_SIERRA_OUTPUT_CLOCKS),1382			  GFP_KERNEL);1383	if (!sp)1384		return -ENOMEM;1385	dev_set_drvdata(dev, sp);1386	sp->dev = dev;1387	sp->init_data = data;1388 1389	base = devm_platform_ioremap_resource(pdev, 0);1390	if (IS_ERR(base)) {1391		dev_err(dev, "missing \"reg\"\n");1392		return PTR_ERR(base);1393	}1394 1395	ret = cdns_regmap_init_blocks(sp, base, data->block_offset_shift,1396				      data->reg_offset_shift);1397	if (ret)1398		return ret;1399 1400	ret = cdns_regfield_init(sp);1401	if (ret)1402		return ret;1403 1404	platform_set_drvdata(pdev, sp);1405 1406	ret = cdns_sierra_phy_get_clocks(sp, dev);1407	if (ret)1408		return ret;1409 1410	ret = cdns_sierra_clk_register(sp);1411	if (ret)1412		return ret;1413 1414	ret = cdns_sierra_phy_enable_clocks(sp);1415	if (ret)1416		goto unregister_clk;1417 1418	regmap_field_read(sp->pma_cmn_ready, &sp->already_configured);1419 1420	if (!sp->already_configured) {1421		ret = cdns_sierra_phy_clk(sp);1422		if (ret)1423			goto clk_disable;1424 1425		ret = cdns_sierra_phy_get_resets(sp, dev);1426		if (ret)1427			goto clk_disable;1428 1429		/* Enable APB */1430		reset_control_deassert(sp->apb_rst);1431	}1432 1433	/* Check that PHY is present */1434	regmap_field_read(sp->macro_id_type, &id_value);1435	if  (sp->init_data->id_value != id_value) {1436		ret = -EINVAL;1437		goto ctrl_assert;1438	}1439 1440	sp->autoconf = of_property_read_bool(dn, "cdns,autoconf");1441 1442	for_each_available_child_of_node_scoped(dn, child) {1443		struct phy *gphy;1444 1445		if (!(of_node_name_eq(child, "phy") ||1446		      of_node_name_eq(child, "link")))1447			continue;1448 1449		sp->phys[node].lnk_rst =1450			of_reset_control_array_get_exclusive(child);1451 1452		if (IS_ERR(sp->phys[node].lnk_rst)) {1453			dev_err(dev, "failed to get reset %s\n",1454				child->full_name);1455			ret = PTR_ERR(sp->phys[node].lnk_rst);1456			goto put_control;1457		}1458 1459		if (!sp->autoconf) {1460			ret = cdns_sierra_get_optional(&sp->phys[node], child);1461			if (ret) {1462				dev_err(dev, "missing property in node %s\n",1463					child->name);1464				reset_control_put(sp->phys[node].lnk_rst);1465				goto put_control;1466			}1467		}1468 1469		sp->num_lanes += sp->phys[node].num_lanes;1470 1471		if (!sp->already_configured)1472			gphy = devm_phy_create(dev, child, &ops);1473		else1474			gphy = devm_phy_create(dev, child, &noop_ops);1475		if (IS_ERR(gphy)) {1476			ret = PTR_ERR(gphy);1477			reset_control_put(sp->phys[node].lnk_rst);1478			goto put_control;1479		}1480		sp->phys[node].phy = gphy;1481		phy_set_drvdata(gphy, &sp->phys[node]);1482 1483		node++;1484	}1485	sp->nsubnodes = node;1486 1487	if (sp->num_lanes > SIERRA_MAX_LANES) {1488		ret = -EINVAL;1489		dev_err(dev, "Invalid lane configuration\n");1490		goto put_control;1491	}1492 1493	/* If more than one subnode, configure the PHY as multilink */1494	if (!sp->already_configured && !sp->autoconf && sp->nsubnodes > 1) {1495		ret = cdns_sierra_phy_configure_multilink(sp);1496		if (ret)1497			goto put_control;1498	}1499 1500	pm_runtime_enable(dev);1501	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);1502	if (IS_ERR(phy_provider)) {1503		ret = PTR_ERR(phy_provider);1504		goto put_control;1505	}1506 1507	return 0;1508 1509put_control:1510	while (--node >= 0)1511		reset_control_put(sp->phys[node].lnk_rst);1512ctrl_assert:1513	if (!sp->already_configured)1514		reset_control_assert(sp->apb_rst);1515clk_disable:1516	cdns_sierra_phy_disable_clocks(sp);1517unregister_clk:1518	cdns_sierra_clk_unregister(sp);1519	return ret;1520}1521 1522static void cdns_sierra_phy_remove(struct platform_device *pdev)1523{1524	struct cdns_sierra_phy *phy = platform_get_drvdata(pdev);1525	int i;1526 1527	reset_control_assert(phy->phy_rst);1528	reset_control_assert(phy->apb_rst);1529	pm_runtime_disable(&pdev->dev);1530 1531	cdns_sierra_phy_disable_clocks(phy);1532	/*1533	 * The device level resets will be put automatically.1534	 * Need to put the subnode resets here though.1535	 */1536	for (i = 0; i < phy->nsubnodes; i++) {1537		reset_control_assert(phy->phys[i].lnk_rst);1538		reset_control_put(phy->phys[i].lnk_rst);1539	}1540 1541	cdns_sierra_clk_unregister(phy);1542}1543 1544/* SGMII PHY PMA lane configuration */1545static const struct cdns_reg_pairs sgmii_phy_pma_ln_regs[] = {1546	{0x9010, SIERRA_PHY_PMA_XCVR_CTRL}1547};1548 1549static const struct cdns_sierra_vals sgmii_phy_pma_ln_vals = {1550	.reg_pairs = sgmii_phy_pma_ln_regs,1551	.num_regs = ARRAY_SIZE(sgmii_phy_pma_ln_regs),1552};1553 1554/* SGMII refclk 100MHz, no ssc, opt3 and GE1 links using PLL LC1 */1555static const struct cdns_reg_pairs sgmii_100_no_ssc_plllc1_opt3_cmn_regs[] = {1556	{0x002D, SIERRA_CMN_PLLLC1_FBDIV_INT_PREG},1557	{0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG},1558	{0x1005, SIERRA_CMN_PLLLC1_CLK0_PREG},1559	{0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG},1560	{0x0800, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG}1561};1562 1563static const struct cdns_reg_pairs sgmii_100_no_ssc_plllc1_opt3_ln_regs[] = {1564	{0x688E, SIERRA_DET_STANDEC_D_PREG},1565	{0x0004, SIERRA_PSC_LN_IDLE_PREG},1566	{0x0FFE, SIERRA_PSC_RX_A0_PREG},1567	{0x0106, SIERRA_PLLCTRL_FBDIV_MODE01_PREG},1568	{0x0013, SIERRA_PLLCTRL_SUBRATE_PREG},1569	{0x0003, SIERRA_PLLCTRL_GEN_A_PREG},1570	{0x0106, SIERRA_PLLCTRL_GEN_D_PREG},1571	{0x5231, SIERRA_PLLCTRL_CPGAIN_MODE_PREG },1572	{0x0000, SIERRA_DRVCTRL_ATTEN_PREG},1573	{0x9702, SIERRA_DRVCTRL_BOOST_PREG},1574	{0x0051, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},1575	{0x3C0E, SIERRA_CREQ_CCLKDET_MODE01_PREG},1576	{0x3220, SIERRA_CREQ_FSMCLK_SEL_PREG},1577	{0x0000, SIERRA_CREQ_EQ_CTRL_PREG},1578	{0x0002, SIERRA_DEQ_PHALIGN_CTRL},1579	{0x0186, SIERRA_DEQ_GLUT0},1580	{0x0186, SIERRA_DEQ_GLUT1},1581	{0x0186, SIERRA_DEQ_GLUT2},1582	{0x0186, SIERRA_DEQ_GLUT3},1583	{0x0186, SIERRA_DEQ_GLUT4},1584	{0x0861, SIERRA_DEQ_ALUT0},1585	{0x07E0, SIERRA_DEQ_ALUT1},1586	{0x079E, SIERRA_DEQ_ALUT2},1587	{0x071D, SIERRA_DEQ_ALUT3},1588	{0x03F5, SIERRA_DEQ_DFETAP_CTRL_PREG},1589	{0x0C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},1590	{0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},1591	{0x1C04, SIERRA_DEQ_TAU_CTRL2_PREG},1592	{0x0033, SIERRA_DEQ_PICTRL_PREG},1593	{0x0000, SIERRA_CPI_OUTBUF_RATESEL_PREG},1594	{0x0B6D, SIERRA_CPI_RESBIAS_BIN_PREG},1595	{0x0102, SIERRA_RXBUFFER_CTLECTRL_PREG},1596	{0x0002, SIERRA_RXBUFFER_RCDFECTRL_PREG}1597};1598 1599static const struct cdns_sierra_vals sgmii_100_no_ssc_plllc1_opt3_cmn_vals = {1600	.reg_pairs = sgmii_100_no_ssc_plllc1_opt3_cmn_regs,1601	.num_regs = ARRAY_SIZE(sgmii_100_no_ssc_plllc1_opt3_cmn_regs),1602};1603 1604static const struct cdns_sierra_vals sgmii_100_no_ssc_plllc1_opt3_ln_vals = {1605	.reg_pairs = sgmii_100_no_ssc_plllc1_opt3_ln_regs,1606	.num_regs = ARRAY_SIZE(sgmii_100_no_ssc_plllc1_opt3_ln_regs),1607};1608 1609/* QSGMII PHY PMA lane configuration */1610static const struct cdns_reg_pairs qsgmii_phy_pma_ln_regs[] = {1611	{0x9010, SIERRA_PHY_PMA_XCVR_CTRL}1612};1613 1614static const struct cdns_sierra_vals qsgmii_phy_pma_ln_vals = {1615	.reg_pairs = qsgmii_phy_pma_ln_regs,1616	.num_regs = ARRAY_SIZE(qsgmii_phy_pma_ln_regs),1617};1618 1619/* QSGMII refclk 100MHz, 20b, opt1, No BW cal, no ssc, PLL LC1 */1620static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_cmn_regs[] = {1621	{0x2085, SIERRA_CMN_PLLLC1_LF_COEFF_MODE0_PREG},1622	{0x0000, SIERRA_CMN_PLLLC1_BWCAL_MODE0_PREG},1623	{0x0000, SIERRA_CMN_PLLLC1_SS_TIME_STEPSIZE_MODE_PREG}1624};1625 1626static const struct cdns_reg_pairs qsgmii_100_no_ssc_plllc1_ln_regs[] = {1627	{0xFC08, SIERRA_DET_STANDEC_A_PREG},1628	{0x0252, SIERRA_DET_STANDEC_E_PREG},1629	{0x0004, SIERRA_PSC_LN_IDLE_PREG},1630	{0x0FFE, SIERRA_PSC_RX_A0_PREG},1631	{0x0011, SIERRA_PLLCTRL_SUBRATE_PREG},1632	{0x0001, SIERRA_PLLCTRL_GEN_A_PREG},1633	{0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},1634	{0x0000, SIERRA_DRVCTRL_ATTEN_PREG},1635	{0x0089, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},1636	{0x3C3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},1637	{0x3222, SIERRA_CREQ_FSMCLK_SEL_PREG},1638	{0x0000, SIERRA_CREQ_EQ_CTRL_PREG},1639	{0x8422, SIERRA_CTLELUT_CTRL_PREG},1640	{0x4111, SIERRA_DFE_ECMP_RATESEL_PREG},1641	{0x4111, SIERRA_DFE_SMP_RATESEL_PREG},1642	{0x0002, SIERRA_DEQ_PHALIGN_CTRL},1643	{0x9595, SIERRA_DEQ_VGATUNE_CTRL_PREG},1644	{0x0186, SIERRA_DEQ_GLUT0},1645	{0x0186, SIERRA_DEQ_GLUT1},1646	{0x0186, SIERRA_DEQ_GLUT2},1647	{0x0186, SIERRA_DEQ_GLUT3},1648	{0x0186, SIERRA_DEQ_GLUT4},1649	{0x0861, SIERRA_DEQ_ALUT0},1650	{0x07E0, SIERRA_DEQ_ALUT1},1651	{0x079E, SIERRA_DEQ_ALUT2},1652	{0x071D, SIERRA_DEQ_ALUT3},1653	{0x03F5, SIERRA_DEQ_DFETAP_CTRL_PREG},1654	{0x0C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},1655	{0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},1656	{0x1C04, SIERRA_DEQ_TAU_CTRL2_PREG},1657	{0x0033, SIERRA_DEQ_PICTRL_PREG},1658	{0x0660, SIERRA_CPICAL_TMRVAL_MODE0_PREG},1659	{0x00D5, SIERRA_CPI_OUTBUF_RATESEL_PREG},1660	{0x0B6D, SIERRA_CPI_RESBIAS_BIN_PREG},1661	{0x0102, SIERRA_RXBUFFER_CTLECTRL_PREG},1662	{0x0002, SIERRA_RXBUFFER_RCDFECTRL_PREG}1663};1664 1665static const struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_cmn_vals = {1666	.reg_pairs = qsgmii_100_no_ssc_plllc1_cmn_regs,1667	.num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_plllc1_cmn_regs),1668};1669 1670static const struct cdns_sierra_vals qsgmii_100_no_ssc_plllc1_ln_vals = {1671	.reg_pairs = qsgmii_100_no_ssc_plllc1_ln_regs,1672	.num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_plllc1_ln_regs),1673};1674 1675/* PCIE PHY PCS common configuration */1676static const struct cdns_reg_pairs pcie_phy_pcs_cmn_regs[] = {1677	{0x0430, SIERRA_PHY_PIPE_CMN_CTRL1}1678};1679 1680static const struct cdns_sierra_vals pcie_phy_pcs_cmn_vals = {1681	.reg_pairs = pcie_phy_pcs_cmn_regs,1682	.num_regs = ARRAY_SIZE(pcie_phy_pcs_cmn_regs),1683};1684 1685/* refclk100MHz_32b_PCIe_cmn_pll_no_ssc, pcie_links_using_plllc, pipe_bw_3 */1686static const struct cdns_reg_pairs pcie_100_no_ssc_plllc_cmn_regs[] = {1687	{0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},1688	{0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},1689	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},1690	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}1691};1692 1693/*1694 * refclk100MHz_32b_PCIe_ln_no_ssc, multilink, using_plllc,1695 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz1696 */1697static const struct cdns_reg_pairs ml_pcie_100_no_ssc_ln_regs[] = {1698	{0xFC08, SIERRA_DET_STANDEC_A_PREG},1699	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},1700	{0x0004, SIERRA_PSC_LN_A3_PREG},1701	{0x0004, SIERRA_PSC_LN_A4_PREG},1702	{0x0004, SIERRA_PSC_LN_IDLE_PREG},1703	{0x1555, SIERRA_DFE_BIASTRIM_PREG},1704	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},1705	{0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},1706	{0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},1707	{0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},1708	{0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},1709	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},1710	{0x9800, SIERRA_RX_CTLE_CAL_PREG},1711	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},1712	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},1713	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},1714	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},1715	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},1716	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},1717	{0x0041, SIERRA_DEQ_GLUT0},1718	{0x0082, SIERRA_DEQ_GLUT1},1719	{0x00C3, SIERRA_DEQ_GLUT2},1720	{0x0145, SIERRA_DEQ_GLUT3},1721	{0x0186, SIERRA_DEQ_GLUT4},1722	{0x09E7, SIERRA_DEQ_ALUT0},1723	{0x09A6, SIERRA_DEQ_ALUT1},1724	{0x0965, SIERRA_DEQ_ALUT2},1725	{0x08E3, SIERRA_DEQ_ALUT3},1726	{0x00FA, SIERRA_DEQ_DFETAP0},1727	{0x00FA, SIERRA_DEQ_DFETAP1},1728	{0x00FA, SIERRA_DEQ_DFETAP2},1729	{0x00FA, SIERRA_DEQ_DFETAP3},1730	{0x00FA, SIERRA_DEQ_DFETAP4},1731	{0x000F, SIERRA_DEQ_PRECUR_PREG},1732	{0x0280, SIERRA_DEQ_POSTCUR_PREG},1733	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},1734	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},1735	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},1736	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},1737	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},1738	{0x002B, SIERRA_CPI_TRIM_PREG},1739	{0x0003, SIERRA_EPI_CTRL_PREG},1740	{0x803F, SIERRA_SDFILT_H2L_A_PREG},1741	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},1742	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},1743	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}1744};1745 1746static const struct cdns_sierra_vals pcie_100_no_ssc_plllc_cmn_vals = {1747	.reg_pairs = pcie_100_no_ssc_plllc_cmn_regs,1748	.num_regs = ARRAY_SIZE(pcie_100_no_ssc_plllc_cmn_regs),1749};1750 1751static const struct cdns_sierra_vals ml_pcie_100_no_ssc_ln_vals = {1752	.reg_pairs = ml_pcie_100_no_ssc_ln_regs,1753	.num_regs = ARRAY_SIZE(ml_pcie_100_no_ssc_ln_regs),1754};1755 1756/*1757 * TI J721E:1758 * refclk100MHz_32b_PCIe_ln_no_ssc, multilink, using_plllc,1759 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz1760 */1761static const struct cdns_reg_pairs ti_ml_pcie_100_no_ssc_ln_regs[] = {1762	{0xFC08, SIERRA_DET_STANDEC_A_PREG},1763	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},1764	{0x0004, SIERRA_PSC_LN_A3_PREG},1765	{0x0004, SIERRA_PSC_LN_A4_PREG},1766	{0x0004, SIERRA_PSC_LN_IDLE_PREG},1767	{0x1555, SIERRA_DFE_BIASTRIM_PREG},1768	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},1769	{0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},1770	{0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},1771	{0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},1772	{0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},1773	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},1774	{0x9800, SIERRA_RX_CTLE_CAL_PREG},1775	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},1776	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},1777	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},1778	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},1779	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},1780	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},1781	{0x0041, SIERRA_DEQ_GLUT0},1782	{0x0082, SIERRA_DEQ_GLUT1},1783	{0x00C3, SIERRA_DEQ_GLUT2},1784	{0x0145, SIERRA_DEQ_GLUT3},1785	{0x0186, SIERRA_DEQ_GLUT4},1786	{0x09E7, SIERRA_DEQ_ALUT0},1787	{0x09A6, SIERRA_DEQ_ALUT1},1788	{0x0965, SIERRA_DEQ_ALUT2},1789	{0x08E3, SIERRA_DEQ_ALUT3},1790	{0x00FA, SIERRA_DEQ_DFETAP0},1791	{0x00FA, SIERRA_DEQ_DFETAP1},1792	{0x00FA, SIERRA_DEQ_DFETAP2},1793	{0x00FA, SIERRA_DEQ_DFETAP3},1794	{0x00FA, SIERRA_DEQ_DFETAP4},1795	{0x000F, SIERRA_DEQ_PRECUR_PREG},1796	{0x0280, SIERRA_DEQ_POSTCUR_PREG},1797	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},1798	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},1799	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},1800	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},1801	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},1802	{0x002B, SIERRA_CPI_TRIM_PREG},1803	{0x0003, SIERRA_EPI_CTRL_PREG},1804	{0x803F, SIERRA_SDFILT_H2L_A_PREG},1805	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},1806	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},1807	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG},1808	{0x0002, SIERRA_TX_RCVDET_OVRD_PREG}1809};1810 1811static const struct cdns_sierra_vals ti_ml_pcie_100_no_ssc_ln_vals = {1812	.reg_pairs = ti_ml_pcie_100_no_ssc_ln_regs,1813	.num_regs = ARRAY_SIZE(ti_ml_pcie_100_no_ssc_ln_regs),1814};1815 1816/* refclk100MHz_32b_PCIe_cmn_pll_int_ssc, pcie_links_using_plllc, pipe_bw_3 */1817static const struct cdns_reg_pairs pcie_100_int_ssc_plllc_cmn_regs[] = {1818	{0x000E, SIERRA_CMN_PLLLC_MODE_PREG},1819	{0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},1820	{0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},1821	{0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},1822	{0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},1823	{0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG},1824	{0x7F80, SIERRA_CMN_PLLLC_SS_PREG},1825	{0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG},1826	{0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG},1827	{0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG},1828	{0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG}1829};1830 1831/*1832 * refclk100MHz_32b_PCIe_ln_int_ssc, multilink, using_plllc,1833 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz1834 */1835static const struct cdns_reg_pairs ml_pcie_100_int_ssc_ln_regs[] = {1836	{0xFC08, SIERRA_DET_STANDEC_A_PREG},1837	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},1838	{0x0004, SIERRA_PSC_LN_A3_PREG},1839	{0x0004, SIERRA_PSC_LN_A4_PREG},1840	{0x0004, SIERRA_PSC_LN_IDLE_PREG},1841	{0x1555, SIERRA_DFE_BIASTRIM_PREG},1842	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},1843	{0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},1844	{0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},1845	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},1846	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},1847	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},1848	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},1849	{0x9800, SIERRA_RX_CTLE_CAL_PREG},1850	{0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},1851	{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},1852	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},1853	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},1854	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},1855	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},1856	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},1857	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},1858	{0x0041, SIERRA_DEQ_GLUT0},1859	{0x0082, SIERRA_DEQ_GLUT1},1860	{0x00C3, SIERRA_DEQ_GLUT2},1861	{0x0145, SIERRA_DEQ_GLUT3},1862	{0x0186, SIERRA_DEQ_GLUT4},1863	{0x09E7, SIERRA_DEQ_ALUT0},1864	{0x09A6, SIERRA_DEQ_ALUT1},1865	{0x0965, SIERRA_DEQ_ALUT2},1866	{0x08E3, SIERRA_DEQ_ALUT3},1867	{0x00FA, SIERRA_DEQ_DFETAP0},1868	{0x00FA, SIERRA_DEQ_DFETAP1},1869	{0x00FA, SIERRA_DEQ_DFETAP2},1870	{0x00FA, SIERRA_DEQ_DFETAP3},1871	{0x00FA, SIERRA_DEQ_DFETAP4},1872	{0x000F, SIERRA_DEQ_PRECUR_PREG},1873	{0x0280, SIERRA_DEQ_POSTCUR_PREG},1874	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},1875	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},1876	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},1877	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},1878	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},1879	{0x002B, SIERRA_CPI_TRIM_PREG},1880	{0x0003, SIERRA_EPI_CTRL_PREG},1881	{0x803F, SIERRA_SDFILT_H2L_A_PREG},1882	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},1883	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},1884	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}1885};1886 1887static const struct cdns_sierra_vals pcie_100_int_ssc_plllc_cmn_vals = {1888	.reg_pairs = pcie_100_int_ssc_plllc_cmn_regs,1889	.num_regs = ARRAY_SIZE(pcie_100_int_ssc_plllc_cmn_regs),1890};1891 1892static const struct cdns_sierra_vals ml_pcie_100_int_ssc_ln_vals = {1893	.reg_pairs = ml_pcie_100_int_ssc_ln_regs,1894	.num_regs = ARRAY_SIZE(ml_pcie_100_int_ssc_ln_regs),1895};1896 1897/*1898 * TI J721E:1899 * refclk100MHz_32b_PCIe_ln_int_ssc, multilink, using_plllc,1900 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz1901 */1902static const struct cdns_reg_pairs ti_ml_pcie_100_int_ssc_ln_regs[] = {1903	{0xFC08, SIERRA_DET_STANDEC_A_PREG},1904	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},1905	{0x0004, SIERRA_PSC_LN_A3_PREG},1906	{0x0004, SIERRA_PSC_LN_A4_PREG},1907	{0x0004, SIERRA_PSC_LN_IDLE_PREG},1908	{0x1555, SIERRA_DFE_BIASTRIM_PREG},1909	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},1910	{0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},1911	{0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},1912	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},1913	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},1914	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},1915	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},1916	{0x9800, SIERRA_RX_CTLE_CAL_PREG},1917	{0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},1918	{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},1919	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},1920	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},1921	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},1922	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},1923	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},1924	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},1925	{0x0041, SIERRA_DEQ_GLUT0},1926	{0x0082, SIERRA_DEQ_GLUT1},1927	{0x00C3, SIERRA_DEQ_GLUT2},1928	{0x0145, SIERRA_DEQ_GLUT3},1929	{0x0186, SIERRA_DEQ_GLUT4},1930	{0x09E7, SIERRA_DEQ_ALUT0},1931	{0x09A6, SIERRA_DEQ_ALUT1},1932	{0x0965, SIERRA_DEQ_ALUT2},1933	{0x08E3, SIERRA_DEQ_ALUT3},1934	{0x00FA, SIERRA_DEQ_DFETAP0},1935	{0x00FA, SIERRA_DEQ_DFETAP1},1936	{0x00FA, SIERRA_DEQ_DFETAP2},1937	{0x00FA, SIERRA_DEQ_DFETAP3},1938	{0x00FA, SIERRA_DEQ_DFETAP4},1939	{0x000F, SIERRA_DEQ_PRECUR_PREG},1940	{0x0280, SIERRA_DEQ_POSTCUR_PREG},1941	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},1942	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},1943	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},1944	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},1945	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},1946	{0x002B, SIERRA_CPI_TRIM_PREG},1947	{0x0003, SIERRA_EPI_CTRL_PREG},1948	{0x803F, SIERRA_SDFILT_H2L_A_PREG},1949	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},1950	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},1951	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG},1952	{0x0002, SIERRA_TX_RCVDET_OVRD_PREG}1953};1954 1955static const struct cdns_sierra_vals ti_ml_pcie_100_int_ssc_ln_vals = {1956	.reg_pairs = ti_ml_pcie_100_int_ssc_ln_regs,1957	.num_regs = ARRAY_SIZE(ti_ml_pcie_100_int_ssc_ln_regs),1958};1959 1960/* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc, pcie_links_using_plllc, pipe_bw_3 */1961static const struct cdns_reg_pairs pcie_100_ext_ssc_plllc_cmn_regs[] = {1962	{0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},1963	{0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},1964	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},1965	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},1966	{0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}1967};1968 1969/*1970 * refclk100MHz_32b_PCIe_ln_ext_ssc, multilink, using_plllc,1971 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz1972 */1973static const struct cdns_reg_pairs ml_pcie_100_ext_ssc_ln_regs[] = {1974	{0xFC08, SIERRA_DET_STANDEC_A_PREG},1975	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},1976	{0x0004, SIERRA_PSC_LN_A3_PREG},1977	{0x0004, SIERRA_PSC_LN_A4_PREG},1978	{0x0004, SIERRA_PSC_LN_IDLE_PREG},1979	{0x1555, SIERRA_DFE_BIASTRIM_PREG},1980	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},1981	{0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},1982	{0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},1983	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},1984	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},1985	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},1986	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},1987	{0x9800, SIERRA_RX_CTLE_CAL_PREG},1988	{0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},1989	{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},1990	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},1991	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},1992	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},1993	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},1994	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},1995	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},1996	{0x0041, SIERRA_DEQ_GLUT0},1997	{0x0082, SIERRA_DEQ_GLUT1},1998	{0x00C3, SIERRA_DEQ_GLUT2},1999	{0x0145, SIERRA_DEQ_GLUT3},2000	{0x0186, SIERRA_DEQ_GLUT4},2001	{0x09E7, SIERRA_DEQ_ALUT0},2002	{0x09A6, SIERRA_DEQ_ALUT1},2003	{0x0965, SIERRA_DEQ_ALUT2},2004	{0x08E3, SIERRA_DEQ_ALUT3},2005	{0x00FA, SIERRA_DEQ_DFETAP0},2006	{0x00FA, SIERRA_DEQ_DFETAP1},2007	{0x00FA, SIERRA_DEQ_DFETAP2},2008	{0x00FA, SIERRA_DEQ_DFETAP3},2009	{0x00FA, SIERRA_DEQ_DFETAP4},2010	{0x000F, SIERRA_DEQ_PRECUR_PREG},2011	{0x0280, SIERRA_DEQ_POSTCUR_PREG},2012	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},2013	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},2014	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},2015	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},2016	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},2017	{0x002B, SIERRA_CPI_TRIM_PREG},2018	{0x0003, SIERRA_EPI_CTRL_PREG},2019	{0x803F, SIERRA_SDFILT_H2L_A_PREG},2020	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},2021	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},2022	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}2023};2024 2025static const struct cdns_sierra_vals pcie_100_ext_ssc_plllc_cmn_vals = {2026	.reg_pairs = pcie_100_ext_ssc_plllc_cmn_regs,2027	.num_regs = ARRAY_SIZE(pcie_100_ext_ssc_plllc_cmn_regs),2028};2029 2030static const struct cdns_sierra_vals ml_pcie_100_ext_ssc_ln_vals = {2031	.reg_pairs = ml_pcie_100_ext_ssc_ln_regs,2032	.num_regs = ARRAY_SIZE(ml_pcie_100_ext_ssc_ln_regs),2033};2034 2035/*2036 * TI J721E:2037 * refclk100MHz_32b_PCIe_ln_ext_ssc, multilink, using_plllc,2038 * cmn_pllcy_anaclk0_1Ghz, xcvr_pllclk_fullrt_500mhz2039 */2040static const struct cdns_reg_pairs ti_ml_pcie_100_ext_ssc_ln_regs[] = {2041	{0xFC08, SIERRA_DET_STANDEC_A_PREG},2042	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},2043	{0x0004, SIERRA_PSC_LN_A3_PREG},2044	{0x0004, SIERRA_PSC_LN_A4_PREG},2045	{0x0004, SIERRA_PSC_LN_IDLE_PREG},2046	{0x1555, SIERRA_DFE_BIASTRIM_PREG},2047	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},2048	{0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},2049	{0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},2050	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},2051	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},2052	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},2053	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},2054	{0x9800, SIERRA_RX_CTLE_CAL_PREG},2055	{0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},2056	{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},2057	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},2058	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},2059	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},2060	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},2061	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},2062	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},2063	{0x0041, SIERRA_DEQ_GLUT0},2064	{0x0082, SIERRA_DEQ_GLUT1},2065	{0x00C3, SIERRA_DEQ_GLUT2},2066	{0x0145, SIERRA_DEQ_GLUT3},2067	{0x0186, SIERRA_DEQ_GLUT4},2068	{0x09E7, SIERRA_DEQ_ALUT0},2069	{0x09A6, SIERRA_DEQ_ALUT1},2070	{0x0965, SIERRA_DEQ_ALUT2},2071	{0x08E3, SIERRA_DEQ_ALUT3},2072	{0x00FA, SIERRA_DEQ_DFETAP0},2073	{0x00FA, SIERRA_DEQ_DFETAP1},2074	{0x00FA, SIERRA_DEQ_DFETAP2},2075	{0x00FA, SIERRA_DEQ_DFETAP3},2076	{0x00FA, SIERRA_DEQ_DFETAP4},2077	{0x000F, SIERRA_DEQ_PRECUR_PREG},2078	{0x0280, SIERRA_DEQ_POSTCUR_PREG},2079	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},2080	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},2081	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},2082	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},2083	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},2084	{0x002B, SIERRA_CPI_TRIM_PREG},2085	{0x0003, SIERRA_EPI_CTRL_PREG},2086	{0x803F, SIERRA_SDFILT_H2L_A_PREG},2087	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},2088	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},2089	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG},2090	{0x0002, SIERRA_TX_RCVDET_OVRD_PREG}2091};2092 2093static const struct cdns_sierra_vals ti_ml_pcie_100_ext_ssc_ln_vals = {2094	.reg_pairs = ti_ml_pcie_100_ext_ssc_ln_regs,2095	.num_regs = ARRAY_SIZE(ti_ml_pcie_100_ext_ssc_ln_regs),2096};2097 2098/* refclk100MHz_32b_PCIe_cmn_pll_no_ssc */2099static const struct cdns_reg_pairs cdns_pcie_cmn_regs_no_ssc[] = {2100	{0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},2101	{0x2105, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},2102	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},2103	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG}2104};2105 2106/* refclk100MHz_32b_PCIe_ln_no_ssc */2107static const struct cdns_reg_pairs cdns_pcie_ln_regs_no_ssc[] = {2108	{0xFC08, SIERRA_DET_STANDEC_A_PREG},2109	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},2110	{0x1555, SIERRA_DFE_BIASTRIM_PREG},2111	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},2112	{0x8055, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},2113	{0x80BB, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},2114	{0x8351, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},2115	{0x8349, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},2116	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},2117	{0x9800, SIERRA_RX_CTLE_CAL_PREG},2118	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},2119	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},2120	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},2121	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},2122	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},2123	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},2124	{0x0041, SIERRA_DEQ_GLUT0},2125	{0x0082, SIERRA_DEQ_GLUT1},2126	{0x00C3, SIERRA_DEQ_GLUT2},2127	{0x0145, SIERRA_DEQ_GLUT3},2128	{0x0186, SIERRA_DEQ_GLUT4},2129	{0x09E7, SIERRA_DEQ_ALUT0},2130	{0x09A6, SIERRA_DEQ_ALUT1},2131	{0x0965, SIERRA_DEQ_ALUT2},2132	{0x08E3, SIERRA_DEQ_ALUT3},2133	{0x00FA, SIERRA_DEQ_DFETAP0},2134	{0x00FA, SIERRA_DEQ_DFETAP1},2135	{0x00FA, SIERRA_DEQ_DFETAP2},2136	{0x00FA, SIERRA_DEQ_DFETAP3},2137	{0x00FA, SIERRA_DEQ_DFETAP4},2138	{0x000F, SIERRA_DEQ_PRECUR_PREG},2139	{0x0280, SIERRA_DEQ_POSTCUR_PREG},2140	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},2141	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},2142	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},2143	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},2144	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},2145	{0x002B, SIERRA_CPI_TRIM_PREG},2146	{0x0003, SIERRA_EPI_CTRL_PREG},2147	{0x803F, SIERRA_SDFILT_H2L_A_PREG},2148	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},2149	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},2150	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}2151};2152 2153static const struct cdns_sierra_vals pcie_100_no_ssc_cmn_vals = {2154	.reg_pairs = cdns_pcie_cmn_regs_no_ssc,2155	.num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_no_ssc),2156};2157 2158static const struct cdns_sierra_vals pcie_100_no_ssc_ln_vals = {2159	.reg_pairs = cdns_pcie_ln_regs_no_ssc,2160	.num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_no_ssc),2161};2162 2163/* refclk100MHz_32b_PCIe_cmn_pll_int_ssc */2164static const struct cdns_reg_pairs cdns_pcie_cmn_regs_int_ssc[] = {2165	{0x000E, SIERRA_CMN_PLLLC_MODE_PREG},2166	{0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},2167	{0x4006, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},2168	{0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},2169	{0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},2170	{0x0581, SIERRA_CMN_PLLLC_DSMCORR_PREG},2171	{0x7F80, SIERRA_CMN_PLLLC_SS_PREG},2172	{0x0041, SIERRA_CMN_PLLLC_SS_AMP_STEP_SIZE_PREG},2173	{0x0464, SIERRA_CMN_PLLLC_SSTWOPT_PREG},2174	{0x0D0D, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG},2175	{0x0060, SIERRA_CMN_PLLLC_LOCK_DELAY_CTRL_PREG}2176};2177 2178/* refclk100MHz_32b_PCIe_ln_int_ssc */2179static const struct cdns_reg_pairs cdns_pcie_ln_regs_int_ssc[] = {2180	{0xFC08, SIERRA_DET_STANDEC_A_PREG},2181	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},2182	{0x1555, SIERRA_DFE_BIASTRIM_PREG},2183	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},2184	{0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},2185	{0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},2186	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},2187	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},2188	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},2189	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},2190	{0x9800, SIERRA_RX_CTLE_CAL_PREG},2191	{0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},2192	{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},2193	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},2194	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},2195	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},2196	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},2197	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},2198	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},2199	{0x0041, SIERRA_DEQ_GLUT0},2200	{0x0082, SIERRA_DEQ_GLUT1},2201	{0x00C3, SIERRA_DEQ_GLUT2},2202	{0x0145, SIERRA_DEQ_GLUT3},2203	{0x0186, SIERRA_DEQ_GLUT4},2204	{0x09E7, SIERRA_DEQ_ALUT0},2205	{0x09A6, SIERRA_DEQ_ALUT1},2206	{0x0965, SIERRA_DEQ_ALUT2},2207	{0x08E3, SIERRA_DEQ_ALUT3},2208	{0x00FA, SIERRA_DEQ_DFETAP0},2209	{0x00FA, SIERRA_DEQ_DFETAP1},2210	{0x00FA, SIERRA_DEQ_DFETAP2},2211	{0x00FA, SIERRA_DEQ_DFETAP3},2212	{0x00FA, SIERRA_DEQ_DFETAP4},2213	{0x000F, SIERRA_DEQ_PRECUR_PREG},2214	{0x0280, SIERRA_DEQ_POSTCUR_PREG},2215	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},2216	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},2217	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},2218	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},2219	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},2220	{0x002B, SIERRA_CPI_TRIM_PREG},2221	{0x0003, SIERRA_EPI_CTRL_PREG},2222	{0x803F, SIERRA_SDFILT_H2L_A_PREG},2223	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},2224	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},2225	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}2226};2227 2228static const struct cdns_sierra_vals pcie_100_int_ssc_cmn_vals = {2229	.reg_pairs = cdns_pcie_cmn_regs_int_ssc,2230	.num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_int_ssc),2231};2232 2233static const struct cdns_sierra_vals pcie_100_int_ssc_ln_vals = {2234	.reg_pairs = cdns_pcie_ln_regs_int_ssc,2235	.num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_int_ssc),2236};2237 2238/* refclk100MHz_32b_PCIe_cmn_pll_ext_ssc */2239static const struct cdns_reg_pairs cdns_pcie_cmn_regs_ext_ssc[] = {2240	{0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},2241	{0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},2242	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG},2243	{0x8A06, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},2244	{0x1B1B, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}2245};2246 2247/* refclk100MHz_32b_PCIe_ln_ext_ssc */2248static const struct cdns_reg_pairs cdns_pcie_ln_regs_ext_ssc[] = {2249	{0xFC08, SIERRA_DET_STANDEC_A_PREG},2250	{0x001D, SIERRA_PSM_A3IN_TMR_PREG},2251	{0x1555, SIERRA_DFE_BIASTRIM_PREG},2252	{0x9703, SIERRA_DRVCTRL_BOOST_PREG},2253	{0x813E, SIERRA_CLKPATHCTRL_TMR_PREG},2254	{0x8047, SIERRA_RX_CREQ_FLTR_A_MODE3_PREG},2255	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE2_PREG},2256	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},2257	{0x808F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},2258	{0x0002, SIERRA_CREQ_DCBIASATTEN_OVR_PREG},2259	{0x9800, SIERRA_RX_CTLE_CAL_PREG},2260	{0x033C, SIERRA_RX_CTLE_MAINTENANCE_PREG},2261	{0x44CC, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},2262	{0x5624, SIERRA_DEQ_CONCUR_CTRL2_PREG},2263	{0x000F, SIERRA_DEQ_EPIPWR_CTRL2_PREG},2264	{0x00FF, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},2265	{0x4C4C, SIERRA_DEQ_ERRCMP_CTRL_PREG},2266	{0x02FA, SIERRA_DEQ_OFFSET_CTRL_PREG},2267	{0x02FA, SIERRA_DEQ_GAIN_CTRL_PREG},2268	{0x0041, SIERRA_DEQ_GLUT0},2269	{0x0082, SIERRA_DEQ_GLUT1},2270	{0x00C3, SIERRA_DEQ_GLUT2},2271	{0x0145, SIERRA_DEQ_GLUT3},2272	{0x0186, SIERRA_DEQ_GLUT4},2273	{0x09E7, SIERRA_DEQ_ALUT0},2274	{0x09A6, SIERRA_DEQ_ALUT1},2275	{0x0965, SIERRA_DEQ_ALUT2},2276	{0x08E3, SIERRA_DEQ_ALUT3},2277	{0x00FA, SIERRA_DEQ_DFETAP0},2278	{0x00FA, SIERRA_DEQ_DFETAP1},2279	{0x00FA, SIERRA_DEQ_DFETAP2},2280	{0x00FA, SIERRA_DEQ_DFETAP3},2281	{0x00FA, SIERRA_DEQ_DFETAP4},2282	{0x000F, SIERRA_DEQ_PRECUR_PREG},2283	{0x0280, SIERRA_DEQ_POSTCUR_PREG},2284	{0x8F00, SIERRA_DEQ_POSTCUR_DECR_PREG},2285	{0x3C0F, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},2286	{0x1C0C, SIERRA_DEQ_TAU_CTRL2_PREG},2287	{0x0100, SIERRA_DEQ_TAU_CTRL3_PREG},2288	{0x5E82, SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG},2289	{0x002B, SIERRA_CPI_TRIM_PREG},2290	{0x0003, SIERRA_EPI_CTRL_PREG},2291	{0x803F, SIERRA_SDFILT_H2L_A_PREG},2292	{0x0004, SIERRA_RXBUFFER_CTLECTRL_PREG},2293	{0x2010, SIERRA_RXBUFFER_RCDFECTRL_PREG},2294	{0x4432, SIERRA_RXBUFFER_DFECTRL_PREG}2295};2296 2297static const struct cdns_sierra_vals pcie_100_ext_ssc_cmn_vals = {2298	.reg_pairs = cdns_pcie_cmn_regs_ext_ssc,2299	.num_regs = ARRAY_SIZE(cdns_pcie_cmn_regs_ext_ssc),2300};2301 2302static const struct cdns_sierra_vals pcie_100_ext_ssc_ln_vals = {2303	.reg_pairs = cdns_pcie_ln_regs_ext_ssc,2304	.num_regs = ARRAY_SIZE(cdns_pcie_ln_regs_ext_ssc),2305};2306 2307/* refclk100MHz_20b_USB_cmn_pll_ext_ssc */2308static const struct cdns_reg_pairs cdns_usb_cmn_regs_ext_ssc[] = {2309	{0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG},2310	{0x2085, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},2311	{0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},2312	{0x0000, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG}2313};2314 2315/* refclk100MHz_20b_USB_ln_ext_ssc */2316static const struct cdns_reg_pairs cdns_usb_ln_regs_ext_ssc[] = {2317	{0xFE0A, SIERRA_DET_STANDEC_A_PREG},2318	{0x000F, SIERRA_DET_STANDEC_B_PREG},2319	{0x55A5, SIERRA_DET_STANDEC_C_PREG},2320	{0x69ad, SIERRA_DET_STANDEC_D_PREG},2321	{0x0241, SIERRA_DET_STANDEC_E_PREG},2322	{0x0110, SIERRA_PSM_LANECAL_DLY_A1_RESETS_PREG},2323	{0x0014, SIERRA_PSM_A0IN_TMR_PREG},2324	{0xCF00, SIERRA_PSM_DIAG_PREG},2325	{0x001F, SIERRA_PSC_TX_A0_PREG},2326	{0x0007, SIERRA_PSC_TX_A1_PREG},2327	{0x0003, SIERRA_PSC_TX_A2_PREG},2328	{0x0003, SIERRA_PSC_TX_A3_PREG},2329	{0x0FFF, SIERRA_PSC_RX_A0_PREG},2330	{0x0003, SIERRA_PSC_RX_A1_PREG},2331	{0x0003, SIERRA_PSC_RX_A2_PREG},2332	{0x0001, SIERRA_PSC_RX_A3_PREG},2333	{0x0001, SIERRA_PLLCTRL_SUBRATE_PREG},2334	{0x0406, SIERRA_PLLCTRL_GEN_D_PREG},2335	{0x5233, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},2336	{0x00CA, SIERRA_CLKPATH_BIASTRIM_PREG},2337	{0x2512, SIERRA_DFE_BIASTRIM_PREG},2338	{0x0000, SIERRA_DRVCTRL_ATTEN_PREG},2339	{0x823E, SIERRA_CLKPATHCTRL_TMR_PREG},2340	{0x078F, SIERRA_RX_CREQ_FLTR_A_MODE1_PREG},2341	{0x078F, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},2342	{0x7B3C, SIERRA_CREQ_CCLKDET_MODE01_PREG},2343	{0x023C, SIERRA_RX_CTLE_MAINTENANCE_PREG},2344	{0x3232, SIERRA_CREQ_FSMCLK_SEL_PREG},2345	{0x0000, SIERRA_CREQ_EQ_CTRL_PREG},2346	{0x0000, SIERRA_CREQ_SPARE_PREG},2347	{0xCC44, SIERRA_CREQ_EQ_OPEN_EYE_THRESH_PREG},2348	{0x8452, SIERRA_CTLELUT_CTRL_PREG},2349	{0x4121, SIERRA_DFE_ECMP_RATESEL_PREG},2350	{0x4121, SIERRA_DFE_SMP_RATESEL_PREG},2351	{0x0003, SIERRA_DEQ_PHALIGN_CTRL},2352	{0x3200, SIERRA_DEQ_CONCUR_CTRL1_PREG},2353	{0x5064, SIERRA_DEQ_CONCUR_CTRL2_PREG},2354	{0x0030, SIERRA_DEQ_EPIPWR_CTRL2_PREG},2355	{0x0048, SIERRA_DEQ_FAST_MAINT_CYCLES_PREG},2356	{0x5A5A, SIERRA_DEQ_ERRCMP_CTRL_PREG},2357	{0x02F5, SIERRA_DEQ_OFFSET_CTRL_PREG},2358	{0x02F5, SIERRA_DEQ_GAIN_CTRL_PREG},2359	{0x9999, SIERRA_DEQ_VGATUNE_CTRL_PREG},2360	{0x0014, SIERRA_DEQ_GLUT0},2361	{0x0014, SIERRA_DEQ_GLUT1},2362	{0x0014, SIERRA_DEQ_GLUT2},2363	{0x0014, SIERRA_DEQ_GLUT3},2364	{0x0014, SIERRA_DEQ_GLUT4},2365	{0x0014, SIERRA_DEQ_GLUT5},2366	{0x0014, SIERRA_DEQ_GLUT6},2367	{0x0014, SIERRA_DEQ_GLUT7},2368	{0x0014, SIERRA_DEQ_GLUT8},2369	{0x0014, SIERRA_DEQ_GLUT9},2370	{0x0014, SIERRA_DEQ_GLUT10},2371	{0x0014, SIERRA_DEQ_GLUT11},2372	{0x0014, SIERRA_DEQ_GLUT12},2373	{0x0014, SIERRA_DEQ_GLUT13},2374	{0x0014, SIERRA_DEQ_GLUT14},2375	{0x0014, SIERRA_DEQ_GLUT15},2376	{0x0014, SIERRA_DEQ_GLUT16},2377	{0x0BAE, SIERRA_DEQ_ALUT0},2378	{0x0AEB, SIERRA_DEQ_ALUT1},2379	{0x0A28, SIERRA_DEQ_ALUT2},2380	{0x0965, SIERRA_DEQ_ALUT3},2381	{0x08A2, SIERRA_DEQ_ALUT4},2382	{0x07DF, SIERRA_DEQ_ALUT5},2383	{0x071C, SIERRA_DEQ_ALUT6},2384	{0x0659, SIERRA_DEQ_ALUT7},2385	{0x0596, SIERRA_DEQ_ALUT8},2386	{0x0514, SIERRA_DEQ_ALUT9},2387	{0x0492, SIERRA_DEQ_ALUT10},2388	{0x0410, SIERRA_DEQ_ALUT11},2389	{0x038E, SIERRA_DEQ_ALUT12},2390	{0x030C, SIERRA_DEQ_ALUT13},2391	{0x03F4, SIERRA_DEQ_DFETAP_CTRL_PREG},2392	{0x0001, SIERRA_DFE_EN_1010_IGNORE_PREG},2393	{0x3C01, SIERRA_DEQ_TAU_CTRL1_FAST_MAINT_PREG},2394	{0x3C40, SIERRA_DEQ_TAU_CTRL1_SLOW_MAINT_PREG},2395	{0x1C08, SIERRA_DEQ_TAU_CTRL2_PREG},2396	{0x0033, SIERRA_DEQ_PICTRL_PREG},2397	{0x0400, SIERRA_CPICAL_TMRVAL_MODE1_PREG},2398	{0x0330, SIERRA_CPICAL_TMRVAL_MODE0_PREG},2399	{0x01FF, SIERRA_CPICAL_PICNT_MODE1_PREG},2400	{0x0009, SIERRA_CPI_OUTBUF_RATESEL_PREG},2401	{0x3232, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG},2402	{0x0005, SIERRA_LFPSDET_SUPPORT_PREG},2403	{0x000F, SIERRA_LFPSFILT_NS_PREG},2404	{0x0009, SIERRA_LFPSFILT_RD_PREG},2405	{0x0001, SIERRA_LFPSFILT_MP_PREG},2406	{0x6013, SIERRA_SIGDET_SUPPORT_PREG},2407	{0x8013, SIERRA_SDFILT_H2L_A_PREG},2408	{0x8009, SIERRA_SDFILT_L2H_PREG},2409	{0x0024, SIERRA_RXBUFFER_CTLECTRL_PREG},2410	{0x0020, SIERRA_RXBUFFER_RCDFECTRL_PREG},2411	{0x4243, SIERRA_RXBUFFER_DFECTRL_PREG}2412};2413 2414static const struct cdns_sierra_vals usb_100_ext_ssc_cmn_vals = {2415	.reg_pairs = cdns_usb_cmn_regs_ext_ssc,2416	.num_regs = ARRAY_SIZE(cdns_usb_cmn_regs_ext_ssc),2417};2418 2419static const struct cdns_sierra_vals usb_100_ext_ssc_ln_vals = {2420	.reg_pairs = cdns_usb_ln_regs_ext_ssc,2421	.num_regs = ARRAY_SIZE(cdns_usb_ln_regs_ext_ssc),2422};2423 2424/* SGMII PHY common configuration */2425static const struct cdns_reg_pairs sgmii_pma_cmn_vals[] = {2426	{0x0180, SIERRA_SDOSCCAL_CLK_CNT_PREG},2427	{0x6000, SIERRA_CMN_REFRCV_PREG},2428	{0x0031, SIERRA_CMN_RESCAL_CTRLA_PREG},2429	{0x001C, SIERRA_CMN_PLLLC_FBDIV_INT_MODE0_PREG},2430	{0x2106, SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG},2431	{0x0000, SIERRA_CMN_PLLLC_LOCKSEARCH_PREG},2432	{0x8103, SIERRA_CMN_PLLLC_CLK0_PREG},2433	{0x0000, SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG},2434	{0x0027, SIERRA_CMN_PLLCSM_PLLEN_TMR_PREG},2435	{0x0062, SIERRA_CMN_PLLCSM_PLLPRE_TMR_PREG},2436	{0x0800, SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG},2437	{0x0000, SIERRA_CMN_PLLLC_INIT_PREG},2438	{0x0000, SIERRA_CMN_PLLLC_ITERTMR_PREG},2439	{0x0020, SIERRA_CMN_PLLLC_LOCK_CNTSTART_PREG},2440	{0x0013, SIERRA_CMN_PLLLC_DCOCAL_CTRL_PREG},2441	{0x0013, SIERRA_CMN_PLLLC1_DCOCAL_CTRL_PREG},2442};2443 2444static const struct cdns_sierra_vals sgmii_cmn_vals = {2445	.reg_pairs = sgmii_pma_cmn_vals,2446	.num_regs = ARRAY_SIZE(sgmii_pma_cmn_vals),2447};2448 2449/* SGMII PHY lane configuration */2450static const struct cdns_reg_pairs sgmii_ln_regs[] = {2451	{0x691E, SIERRA_DET_STANDEC_D_PREG},2452	{0x0FFE, SIERRA_PSC_RX_A0_PREG},2453	{0x0104, SIERRA_PLLCTRL_FBDIV_MODE01_PREG},2454	{0x0013, SIERRA_PLLCTRL_SUBRATE_PREG},2455	{0x0106, SIERRA_PLLCTRL_GEN_D_PREG},2456	{0x5234, SIERRA_PLLCTRL_CPGAIN_MODE_PREG},2457	{0x0000, SIERRA_DRVCTRL_ATTEN_PREG},2458	{0x00AB, SIERRA_RX_CREQ_FLTR_A_MODE0_PREG},2459	{0x3C0E, SIERRA_CREQ_CCLKDET_MODE01_PREG},2460	{0x3220, SIERRA_CREQ_FSMCLK_SEL_PREG},2461	{0x0000, SIERRA_CREQ_EQ_CTRL_PREG},2462	{0x6320, SIERRA_DEQ_CONCUR_EPIOFFSET_MODE_PREG},2463	{0x0000, SIERRA_CPI_OUTBUF_RATESEL_PREG},2464	{0x15A2, SIERRA_LN_SPARE_REG_PREG},2465	{0x7900, SIERRA_DEQ_BLK_TAU_CTRL1_PREG},2466	{0x2202, SIERRA_DEQ_BLK_TAU_CTRL4_PREG},2467	{0x2206, SIERRA_DEQ_TAU_CTRL2_PREG},2468	{0x0005, SIERRA_LANE_TX_RECEIVER_DETECT_PREG},2469	{0x8001, SIERRA_CREQ_SPARE_PREG},2470	{0x0000, SIERRA_DEQ_CONCUR_CTRL1_PREG},2471	{0xD004, SIERRA_DEQ_CONCUR_CTRL2_PREG},2472	{0x0101, SIERRA_DEQ_GLUT9},2473	{0x0101, SIERRA_DEQ_GLUT10},2474	{0x0101, SIERRA_DEQ_GLUT11},2475	{0x0101, SIERRA_DEQ_GLUT12},2476	{0x0000, SIERRA_DEQ_GLUT13},2477	{0x0000, SIERRA_DEQ_GLUT16},2478	{0x0000, SIERRA_POSTPRECUR_EN_CEPH_CTRL_PREG},2479	{0x0000, SIERRA_TAU_EN_CEPH2TO0_PREG},2480	{0x0003, SIERRA_TAU_EN_CEPH5TO3_PREG},2481	{0x0101, SIERRA_DEQ_ALUT8},2482	{0x0101, SIERRA_DEQ_ALUT9},2483	{0x0100, SIERRA_DEQ_ALUT10},2484	{0x0000, SIERRA_OEPH_EN_CTRL_PREG},2485	{0x5425, SIERRA_DEQ_OPENEYE_CTRL_PREG},2486	{0x7458, SIERRA_CPICAL_RES_STARTCODE_MODE23_PREG},2487	{0x321F, SIERRA_CPICAL_RES_STARTCODE_MODE01_PREG},2488};2489 2490static const struct cdns_sierra_vals sgmii_pma_ln_vals = {2491	.reg_pairs = sgmii_ln_regs,2492	.num_regs = ARRAY_SIZE(sgmii_ln_regs),2493};2494 2495static const struct cdns_sierra_data cdns_map_sierra = {2496	.id_value = SIERRA_MACRO_ID,2497	.block_offset_shift = 0x2,2498	.reg_offset_shift = 0x2,2499	.pcs_cmn_vals = {2500		[TYPE_PCIE] = {2501			[TYPE_NONE] = {2502				[NO_SSC] = &pcie_phy_pcs_cmn_vals,2503				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,2504				[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,2505			},2506			[TYPE_SGMII] = {2507				[NO_SSC] = &pcie_phy_pcs_cmn_vals,2508				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,2509				[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,2510			},2511			[TYPE_QSGMII] = {2512				[NO_SSC] = &pcie_phy_pcs_cmn_vals,2513				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,2514				[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,2515			},2516		},2517	},2518	.pma_cmn_vals = {2519		[TYPE_PCIE] = {2520			[TYPE_NONE] = {2521				[NO_SSC] = &pcie_100_no_ssc_cmn_vals,2522				[EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,2523				[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,2524			},2525			[TYPE_SGMII] = {2526				[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,2527				[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,2528				[INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,2529			},2530			[TYPE_QSGMII] = {2531				[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,2532				[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,2533				[INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,2534			},2535		},2536		[TYPE_USB] = {2537			[TYPE_NONE] = {2538				[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,2539			},2540		},2541		[TYPE_SGMII] = {2542			[TYPE_NONE] = {2543				[NO_SSC] = &sgmii_cmn_vals,2544			},2545			[TYPE_PCIE] = {2546				[NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,2547				[EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,2548				[INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,2549			},2550		},2551		[TYPE_QSGMII] = {2552			[TYPE_PCIE] = {2553				[NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,2554				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,2555				[INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,2556			},2557		},2558	},2559	.pma_ln_vals = {2560		[TYPE_PCIE] = {2561			[TYPE_NONE] = {2562				[NO_SSC] = &pcie_100_no_ssc_ln_vals,2563				[EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,2564				[INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals,2565			},2566			[TYPE_SGMII] = {2567				[NO_SSC] = &ml_pcie_100_no_ssc_ln_vals,2568				[EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals,2569				[INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals,2570			},2571			[TYPE_QSGMII] = {2572				[NO_SSC] = &ml_pcie_100_no_ssc_ln_vals,2573				[EXTERNAL_SSC] = &ml_pcie_100_ext_ssc_ln_vals,2574				[INTERNAL_SSC] = &ml_pcie_100_int_ssc_ln_vals,2575			},2576		},2577		[TYPE_USB] = {2578			[TYPE_NONE] = {2579				[EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,2580			},2581		},2582		[TYPE_SGMII] = {2583			[TYPE_NONE] = {2584				[NO_SSC] = &sgmii_pma_ln_vals,2585			},2586			[TYPE_PCIE] = {2587				[NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,2588				[EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,2589				[INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,2590			},2591		},2592		[TYPE_QSGMII] = {2593			[TYPE_PCIE] = {2594				[NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,2595				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,2596				[INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,2597			},2598		},2599	},2600};2601 2602static const struct cdns_sierra_data cdns_ti_map_sierra = {2603	.id_value = SIERRA_MACRO_ID,2604	.block_offset_shift = 0x0,2605	.reg_offset_shift = 0x1,2606	.pcs_cmn_vals = {2607		[TYPE_PCIE] = {2608			[TYPE_NONE] = {2609				[NO_SSC] = &pcie_phy_pcs_cmn_vals,2610				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,2611				[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,2612			},2613			[TYPE_SGMII] = {2614				[NO_SSC] = &pcie_phy_pcs_cmn_vals,2615				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,2616				[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,2617			},2618			[TYPE_QSGMII] = {2619				[NO_SSC] = &pcie_phy_pcs_cmn_vals,2620				[EXTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,2621				[INTERNAL_SSC] = &pcie_phy_pcs_cmn_vals,2622			},2623		},2624	},2625	.phy_pma_ln_vals = {2626		[TYPE_SGMII] = {2627			[TYPE_PCIE] = {2628				[NO_SSC] = &sgmii_phy_pma_ln_vals,2629				[EXTERNAL_SSC] = &sgmii_phy_pma_ln_vals,2630				[INTERNAL_SSC] = &sgmii_phy_pma_ln_vals,2631			},2632		},2633		[TYPE_QSGMII] = {2634			[TYPE_PCIE] = {2635				[NO_SSC] = &qsgmii_phy_pma_ln_vals,2636				[EXTERNAL_SSC] = &qsgmii_phy_pma_ln_vals,2637				[INTERNAL_SSC] = &qsgmii_phy_pma_ln_vals,2638			},2639		},2640	},2641	.pma_cmn_vals = {2642		[TYPE_PCIE] = {2643			[TYPE_NONE] = {2644				[NO_SSC] = &pcie_100_no_ssc_cmn_vals,2645				[EXTERNAL_SSC] = &pcie_100_ext_ssc_cmn_vals,2646				[INTERNAL_SSC] = &pcie_100_int_ssc_cmn_vals,2647			},2648			[TYPE_SGMII] = {2649				[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,2650				[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,2651				[INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,2652			},2653			[TYPE_QSGMII] = {2654				[NO_SSC] = &pcie_100_no_ssc_plllc_cmn_vals,2655				[EXTERNAL_SSC] = &pcie_100_ext_ssc_plllc_cmn_vals,2656				[INTERNAL_SSC] = &pcie_100_int_ssc_plllc_cmn_vals,2657			},2658		},2659		[TYPE_USB] = {2660			[TYPE_NONE] = {2661				[EXTERNAL_SSC] = &usb_100_ext_ssc_cmn_vals,2662			},2663		},2664		[TYPE_SGMII] = {2665			[TYPE_PCIE] = {2666				[NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,2667				[EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,2668				[INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_cmn_vals,2669			},2670		},2671		[TYPE_QSGMII] = {2672			[TYPE_PCIE] = {2673				[NO_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,2674				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,2675				[INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_cmn_vals,2676			},2677		},2678	},2679	.pma_ln_vals = {2680		[TYPE_PCIE] = {2681			[TYPE_NONE] = {2682				[NO_SSC] = &pcie_100_no_ssc_ln_vals,2683				[EXTERNAL_SSC] = &pcie_100_ext_ssc_ln_vals,2684				[INTERNAL_SSC] = &pcie_100_int_ssc_ln_vals,2685			},2686			[TYPE_SGMII] = {2687				[NO_SSC] = &ti_ml_pcie_100_no_ssc_ln_vals,2688				[EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals,2689				[INTERNAL_SSC] = &ti_ml_pcie_100_int_ssc_ln_vals,2690			},2691			[TYPE_QSGMII] = {2692				[NO_SSC] = &ti_ml_pcie_100_no_ssc_ln_vals,2693				[EXTERNAL_SSC] = &ti_ml_pcie_100_ext_ssc_ln_vals,2694				[INTERNAL_SSC] = &ti_ml_pcie_100_int_ssc_ln_vals,2695			},2696		},2697		[TYPE_USB] = {2698			[TYPE_NONE] = {2699				[EXTERNAL_SSC] = &usb_100_ext_ssc_ln_vals,2700			},2701		},2702		[TYPE_SGMII] = {2703			[TYPE_PCIE] = {2704				[NO_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,2705				[EXTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,2706				[INTERNAL_SSC] = &sgmii_100_no_ssc_plllc1_opt3_ln_vals,2707			},2708		},2709		[TYPE_QSGMII] = {2710			[TYPE_PCIE] = {2711				[NO_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,2712				[EXTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,2713				[INTERNAL_SSC] = &qsgmii_100_no_ssc_plllc1_ln_vals,2714			},2715		},2716	},2717};2718 2719static const struct of_device_id cdns_sierra_id_table[] = {2720	{2721		.compatible = "cdns,sierra-phy-t0",2722		.data = &cdns_map_sierra,2723	},2724	{2725		.compatible = "ti,sierra-phy-t0",2726		.data = &cdns_ti_map_sierra,2727	},2728	{}2729};2730MODULE_DEVICE_TABLE(of, cdns_sierra_id_table);2731 2732static struct platform_driver cdns_sierra_driver = {2733	.probe		= cdns_sierra_phy_probe,2734	.remove_new	= cdns_sierra_phy_remove,2735	.driver		= {2736		.name	= "cdns-sierra-phy",2737		.of_match_table = cdns_sierra_id_table,2738	},2739};2740module_platform_driver(cdns_sierra_driver);2741 2742MODULE_ALIAS("platform:cdns_sierra");2743MODULE_AUTHOR("Cadence Design Systems");2744MODULE_DESCRIPTION("CDNS sierra phy driver");2745MODULE_LICENSE("GPL v2");2746