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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Cadence Torrent SD0801 PHY driver.4 *5 * Copyright 2018 Cadence Design Systems, Inc.6 *7 */8 9#include <dt-bindings/phy/phy.h>10#include <dt-bindings/phy/phy-cadence.h>11#include <linux/clk.h>12#include <linux/clk-provider.h>13#include <linux/delay.h>14#include <linux/err.h>15#include <linux/io.h>16#include <linux/iopoll.h>17#include <linux/kernel.h>18#include <linux/module.h>19#include <linux/of.h>20#include <linux/phy/phy.h>21#include <linux/platform_device.h>22#include <linux/reset.h>23#include <linux/regmap.h>24 25#define REF_CLK_19_2MHZ		1920000026#define REF_CLK_25MHZ		2500000027#define REF_CLK_100MHZ		10000000028#define REF_CLK_156_25MHZ	15625000029 30#define MAX_NUM_LANES		431#define DEFAULT_MAX_BIT_RATE	8100 /* in Mbps */32 33#define POLL_TIMEOUT_US		500034#define PLL_LOCK_TIMEOUT	10000035 36#define DP_PLL0			BIT(0)37#define DP_PLL1			BIT(1)38 39#define TORRENT_COMMON_CDB_OFFSET	0x040 41#define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset)	\42				((0x4000 << (block_offset)) +		\43				(((ln) << 9) << (reg_offset)))44 45#define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset)	\46				((0x8000 << (block_offset)) +		\47				(((ln) << 9) << (reg_offset)))48 49#define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset)	\50				(0xC000 << (block_offset))51 52#define TORRENT_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset)	\53				((0xD000 << (block_offset)) +		\54				(((ln) << 8) << (reg_offset)))55 56#define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset)	\57				(0xE000 << (block_offset))58 59#define TORRENT_DPTX_PHY_OFFSET		0x060 61/*62 * register offsets from DPTX PHY register block base (i.e MHDP63 * register base + 0x30a00)64 */65#define PHY_AUX_CTRL			0x0466#define PHY_RESET			0x2067#define PMA_TX_ELEC_IDLE_SHIFT		468#define PHY_PMA_XCVR_PLLCLK_EN		0x2469#define PHY_PMA_XCVR_PLLCLK_EN_ACK	0x2870#define PHY_PMA_XCVR_POWER_STATE_REQ	0x2c71#define PHY_POWER_STATE_LN(ln)		((ln) * 8)72#define PMA_XCVR_POWER_STATE_REQ_LN_MASK	0x3FU73#define PHY_PMA_XCVR_POWER_STATE_ACK	0x3074#define PHY_PMA_CMN_READY		0x3475 76/*77 * register offsets from SD0801 PHY register block base (i.e MHDP78 * register base + 0x500000)79 */80#define CMN_SSM_BANDGAP_TMR		0x0021U81#define CMN_SSM_BIAS_TMR		0x0022U82#define CMN_PLLSM0_PLLPRE_TMR		0x002AU83#define CMN_PLLSM0_PLLLOCK_TMR		0x002CU84#define CMN_PLLSM1_PLLPRE_TMR		0x0032U85#define CMN_PLLSM1_PLLLOCK_TMR		0x0034U86#define CMN_CDIAG_CDB_PWRI_OVRD		0x0041U87#define CMN_CDIAG_XCVRC_PWRI_OVRD	0x0047U88#define CMN_CDIAG_REFCLK_OVRD		0x004CU89#define CMN_CDIAG_REFCLK_DRV0_CTRL	0x0050U90#define CMN_BGCAL_INIT_TMR		0x0064U91#define CMN_BGCAL_ITER_TMR		0x0065U92#define CMN_IBCAL_INIT_TMR		0x0074U93#define CMN_PLL0_VCOCAL_TCTRL		0x0082U94#define CMN_PLL0_VCOCAL_INIT_TMR	0x0084U95#define CMN_PLL0_VCOCAL_ITER_TMR	0x0085U96#define CMN_PLL0_VCOCAL_REFTIM_START	0x0086U97#define CMN_PLL0_VCOCAL_PLLCNT_START	0x0088U98#define CMN_PLL0_INTDIV_M0		0x0090U99#define CMN_PLL0_FRACDIVL_M0		0x0091U100#define CMN_PLL0_FRACDIVH_M0		0x0092U101#define CMN_PLL0_HIGH_THR_M0		0x0093U102#define CMN_PLL0_DSM_DIAG_M0		0x0094U103#define CMN_PLL0_DSM_FBH_OVRD_M0	0x0095U104#define CMN_PLL0_DSM_FBL_OVRD_M0	0x0096U105#define CMN_PLL0_SS_CTRL1_M0		0x0098U106#define CMN_PLL0_SS_CTRL2_M0            0x0099U107#define CMN_PLL0_SS_CTRL3_M0            0x009AU108#define CMN_PLL0_SS_CTRL4_M0            0x009BU109#define CMN_PLL0_LOCK_REFCNT_START      0x009CU110#define CMN_PLL0_LOCK_PLLCNT_START	0x009EU111#define CMN_PLL0_LOCK_PLLCNT_THR        0x009FU112#define CMN_PLL0_INTDIV_M1		0x00A0U113#define CMN_PLL0_FRACDIVH_M1		0x00A2U114#define CMN_PLL0_HIGH_THR_M1		0x00A3U115#define CMN_PLL0_DSM_DIAG_M1		0x00A4U116#define CMN_PLL0_SS_CTRL1_M1		0x00A8U117#define CMN_PLL0_SS_CTRL2_M1		0x00A9U118#define CMN_PLL0_SS_CTRL3_M1		0x00AAU119#define CMN_PLL0_SS_CTRL4_M1		0x00ABU120#define CMN_PLL1_VCOCAL_TCTRL		0x00C2U121#define CMN_PLL1_VCOCAL_INIT_TMR	0x00C4U122#define CMN_PLL1_VCOCAL_ITER_TMR	0x00C5U123#define CMN_PLL1_VCOCAL_REFTIM_START	0x00C6U124#define CMN_PLL1_VCOCAL_PLLCNT_START	0x00C8U125#define CMN_PLL1_INTDIV_M0		0x00D0U126#define CMN_PLL1_FRACDIVL_M0		0x00D1U127#define CMN_PLL1_FRACDIVH_M0		0x00D2U128#define CMN_PLL1_HIGH_THR_M0		0x00D3U129#define CMN_PLL1_DSM_DIAG_M0		0x00D4U130#define CMN_PLL1_DSM_FBH_OVRD_M0	0x00D5U131#define CMN_PLL1_DSM_FBL_OVRD_M0	0x00D6U132#define CMN_PLL1_SS_CTRL1_M0		0x00D8U133#define CMN_PLL1_SS_CTRL2_M0            0x00D9U134#define CMN_PLL1_SS_CTRL3_M0            0x00DAU135#define CMN_PLL1_SS_CTRL4_M0            0x00DBU136#define CMN_PLL1_LOCK_REFCNT_START      0x00DCU137#define CMN_PLL1_LOCK_PLLCNT_START	0x00DEU138#define CMN_PLL1_LOCK_PLLCNT_THR        0x00DFU139#define CMN_TXPUCAL_TUNE		0x0103U140#define CMN_TXPUCAL_INIT_TMR		0x0104U141#define CMN_TXPUCAL_ITER_TMR		0x0105U142#define CMN_TXPDCAL_TUNE		0x010BU143#define CMN_TXPDCAL_INIT_TMR		0x010CU144#define CMN_TXPDCAL_ITER_TMR		0x010DU145#define CMN_RXCAL_INIT_TMR		0x0114U146#define CMN_RXCAL_ITER_TMR		0x0115U147#define CMN_SD_CAL_INIT_TMR		0x0124U148#define CMN_SD_CAL_ITER_TMR		0x0125U149#define CMN_SD_CAL_REFTIM_START		0x0126U150#define CMN_SD_CAL_PLLCNT_START		0x0128U151#define CMN_PDIAG_PLL0_CTRL_M0		0x01A0U152#define CMN_PDIAG_PLL0_CLK_SEL_M0	0x01A1U153#define CMN_PDIAG_PLL0_CP_PADJ_M0	0x01A4U154#define CMN_PDIAG_PLL0_CP_IADJ_M0	0x01A5U155#define CMN_PDIAG_PLL0_FILT_PADJ_M0	0x01A6U156#define CMN_PDIAG_PLL0_CTRL_M1		0x01B0U157#define CMN_PDIAG_PLL0_CLK_SEL_M1	0x01B1U158#define CMN_PDIAG_PLL0_CP_PADJ_M1	0x01B4U159#define CMN_PDIAG_PLL0_CP_IADJ_M1	0x01B5U160#define CMN_PDIAG_PLL0_FILT_PADJ_M1	0x01B6U161#define CMN_PDIAG_PLL1_CTRL_M0		0x01C0U162#define CMN_PDIAG_PLL1_CLK_SEL_M0	0x01C1U163#define CMN_PDIAG_PLL1_CP_PADJ_M0	0x01C4U164#define CMN_PDIAG_PLL1_CP_IADJ_M0	0x01C5U165#define CMN_PDIAG_PLL1_FILT_PADJ_M0	0x01C6U166#define CMN_DIAG_BIAS_OVRD1		0x01E1U167 168/* PMA TX Lane registers */169#define TX_TXCC_CTRL			0x0040U170#define TX_TXCC_CPOST_MULT_00		0x004CU171#define TX_TXCC_CPOST_MULT_01		0x004DU172#define TX_TXCC_MGNFS_MULT_000		0x0050U173#define TX_TXCC_MGNFS_MULT_100		0x0054U174#define DRV_DIAG_TX_DRV			0x00C6U175#define XCVR_DIAG_PLLDRC_CTRL		0x00E5U176#define XCVR_DIAG_HSCLK_SEL		0x00E6U177#define XCVR_DIAG_HSCLK_DIV		0x00E7U178#define XCVR_DIAG_RXCLK_CTRL		0x00E9U179#define XCVR_DIAG_BIDI_CTRL		0x00EAU180#define XCVR_DIAG_PSC_OVRD		0x00EBU181#define TX_PSC_A0			0x0100U182#define TX_PSC_A1			0x0101U183#define TX_PSC_A2			0x0102U184#define TX_PSC_A3			0x0103U185#define TX_RCVDET_ST_TMR		0x0123U186#define TX_DIAG_ACYA			0x01E7U187#define TX_DIAG_ACYA_HBDC_MASK		0x0001U188 189/* PMA RX Lane registers */190#define RX_PSC_A0			0x0000U191#define RX_PSC_A1			0x0001U192#define RX_PSC_A2			0x0002U193#define RX_PSC_A3			0x0003U194#define RX_PSC_CAL			0x0006U195#define RX_SDCAL0_INIT_TMR		0x0044U196#define RX_SDCAL0_ITER_TMR		0x0045U197#define RX_SDCAL1_INIT_TMR		0x004CU198#define RX_SDCAL1_ITER_TMR		0x004DU199#define RX_CDRLF_CNFG			0x0080U200#define RX_CDRLF_CNFG3			0x0082U201#define RX_SIGDET_HL_FILT_TMR		0x0090U202#define RX_REE_GCSM1_CTRL		0x0108U203#define RX_REE_GCSM1_EQENM_PH1		0x0109U204#define RX_REE_GCSM1_EQENM_PH2		0x010AU205#define RX_REE_GCSM2_CTRL		0x0110U206#define RX_REE_PERGCSM_CTRL		0x0118U207#define RX_REE_ATTEN_THR		0x0149U208#define RX_REE_TAP1_CLIP		0x0171U209#define RX_REE_TAP2TON_CLIP		0x0172U210#define RX_REE_SMGM_CTRL1		0x0177U211#define RX_REE_SMGM_CTRL2		0x0178U212#define RX_DIAG_DFE_CTRL		0x01E0U213#define RX_DIAG_DFE_AMP_TUNE_2		0x01E2U214#define RX_DIAG_DFE_AMP_TUNE_3		0x01E3U215#define RX_DIAG_NQST_CTRL		0x01E5U216#define RX_DIAG_SIGDET_TUNE		0x01E8U217#define RX_DIAG_PI_RATE			0x01F4U218#define RX_DIAG_PI_CAP			0x01F5U219#define RX_DIAG_ACYA			0x01FFU220 221/* PHY PCS common registers */222#define PHY_PIPE_CMN_CTRL1		0x0000U223#define PHY_PLL_CFG			0x000EU224#define PHY_PIPE_USB3_GEN2_PRE_CFG0	0x0020U225#define PHY_PIPE_USB3_GEN2_POST_CFG0	0x0022U226#define PHY_PIPE_USB3_GEN2_POST_CFG1	0x0023U227 228/* PHY PCS lane registers */229#define PHY_PCS_ISO_LINK_CTRL		0x000BU230 231/* PHY PMA common registers */232#define PHY_PMA_CMN_CTRL1		0x0000U233#define PHY_PMA_CMN_CTRL2		0x0001U234#define PHY_PMA_PLL_RAW_CTRL		0x0003U235 236#define CDNS_TORRENT_OUTPUT_CLOCKS	3237 238static const char * const clk_names[] = {239	[CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",240	[CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der",241	[CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec",242};243 244static const struct reg_field phy_pll_cfg =245				REG_FIELD(PHY_PLL_CFG, 0, 1);246 247static const struct reg_field phy_pma_cmn_ctrl_1 =248				REG_FIELD(PHY_PMA_CMN_CTRL1, 0, 0);249 250static const struct reg_field phy_pma_cmn_ctrl_2 =251				REG_FIELD(PHY_PMA_CMN_CTRL2, 0, 7);252 253static const struct reg_field phy_pma_pll_raw_ctrl =254				REG_FIELD(PHY_PMA_PLL_RAW_CTRL, 0, 1);255 256static const struct reg_field phy_reset_ctrl =257				REG_FIELD(PHY_RESET, 8, 8);258 259static const struct reg_field phy_pcs_iso_link_ctrl_1 =260				REG_FIELD(PHY_PCS_ISO_LINK_CTRL, 1, 1);261 262static const struct reg_field phy_pipe_cmn_ctrl1_0 = REG_FIELD(PHY_PIPE_CMN_CTRL1, 0, 0);263 264static const struct reg_field cmn_cdiag_refclk_ovrd_4 =265				REG_FIELD(CMN_CDIAG_REFCLK_OVRD, 4, 4);266 267#define REFCLK_OUT_NUM_CMN_CONFIG	4268 269enum cdns_torrent_refclk_out_cmn {270	CMN_CDIAG_REFCLK_DRV0_CTRL_1,271	CMN_CDIAG_REFCLK_DRV0_CTRL_4,272	CMN_CDIAG_REFCLK_DRV0_CTRL_5,273	CMN_CDIAG_REFCLK_DRV0_CTRL_6,274};275 276static const struct reg_field refclk_out_cmn_cfg[] = {277	[CMN_CDIAG_REFCLK_DRV0_CTRL_1]	= REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 1, 1),278	[CMN_CDIAG_REFCLK_DRV0_CTRL_4]	= REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 4, 4),279	[CMN_CDIAG_REFCLK_DRV0_CTRL_5]  = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 5, 5),280	[CMN_CDIAG_REFCLK_DRV0_CTRL_6]	= REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 6, 6),281};282 283static const int refclk_driver_parent_index[] = {284	CDNS_TORRENT_DERIVED_REFCLK,285	CDNS_TORRENT_RECEIVED_REFCLK286};287 288static const u32 cdns_torrent_refclk_driver_mux_table[] = { 1, 0 };289 290enum cdns_torrent_phy_type {291	TYPE_NONE,292	TYPE_DP,293	TYPE_PCIE,294	TYPE_SGMII,295	TYPE_QSGMII,296	TYPE_USB,297	TYPE_USXGMII,298};299 300enum cdns_torrent_ref_clk {301	CLK_19_2_MHZ,302	CLK_25_MHZ,303	CLK_100_MHZ,304	CLK_156_25_MHZ,305	CLK_ANY,306};307 308enum cdns_torrent_ssc_mode {309	NO_SSC,310	EXTERNAL_SSC,311	INTERNAL_SSC,312	ANY_SSC,313};314 315/* Unique key id for vals table entry316 * REFCLK0_RATE | REFCLK1_RATE | LINK0_TYPE | LINK1_TYPE | SSC_TYPE317 */318#define REFCLK0_SHIFT	12319#define REFCLK0_MASK	GENMASK(14, 12)320#define REFCLK1_SHIFT	9321#define REFCLK1_MASK	GENMASK(11, 9)322#define LINK0_SHIFT	6323#define LINK0_MASK	GENMASK(8, 6)324#define LINK1_SHIFT	3325#define LINK1_MASK	GENMASK(5, 3)326#define SSC_SHIFT	0327#define SSC_MASK	GENMASK(2, 0)328 329#define CDNS_TORRENT_KEY(refclk0, refclk1, link0, link1, ssc) \330			((((refclk0) << REFCLK0_SHIFT) & REFCLK0_MASK) | \331			(((refclk1) << REFCLK1_SHIFT) & REFCLK1_MASK) | \332			(((link0) << LINK0_SHIFT) & LINK0_MASK) | \333			(((link1) << LINK1_SHIFT) & LINK1_MASK) | \334			(((ssc) << SSC_SHIFT) & SSC_MASK))335 336#define CDNS_TORRENT_KEY_ANYCLK(link0, link1) \337			CDNS_TORRENT_KEY(CLK_ANY, CLK_ANY, \338					 (link0), (link1), ANY_SSC)339 340struct cdns_torrent_inst {341	struct phy *phy;342	u32 mlane;343	enum cdns_torrent_phy_type phy_type;344	u32 num_lanes;345	struct reset_control *lnk_rst;346	enum cdns_torrent_ssc_mode ssc_mode;347};348 349struct cdns_torrent_phy {350	void __iomem *base;	/* DPTX registers base */351	void __iomem *sd_base; /* SD0801 registers base */352	u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */353	u32 dp_pll;354	u32 protocol_bitmask;355	struct reset_control *phy_rst;356	struct reset_control *apb_rst;357	struct device *dev;358	struct clk *clk;359	struct clk *clk1;360	enum cdns_torrent_ref_clk ref_clk_rate;361	enum cdns_torrent_ref_clk ref_clk1_rate;362	struct cdns_torrent_inst phys[MAX_NUM_LANES];363	int nsubnodes;364	int already_configured;365	const struct cdns_torrent_data *init_data;366	struct regmap *regmap_common_cdb;367	struct regmap *regmap_phy_pcs_common_cdb;368	struct regmap *regmap_phy_pma_common_cdb;369	struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES];370	struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES];371	struct regmap *regmap_phy_pcs_lane_cdb[MAX_NUM_LANES];372	struct regmap *regmap_dptx_phy_reg;373	struct regmap_field *phy_pll_cfg;374	struct regmap_field *phy_pipe_cmn_ctrl1_0;375	struct regmap_field *cmn_cdiag_refclk_ovrd_4;376	struct regmap_field *phy_pma_cmn_ctrl_1;377	struct regmap_field *phy_pma_cmn_ctrl_2;378	struct regmap_field *phy_pma_pll_raw_ctrl;379	struct regmap_field *phy_reset_ctrl;380	struct regmap_field *phy_pcs_iso_link_ctrl_1[MAX_NUM_LANES];381	struct clk_hw_onecell_data *clk_hw_data;382};383 384enum phy_powerstate {385	POWERSTATE_A0 = 0,386	/* Powerstate A1 is unused */387	POWERSTATE_A2 = 2,388	POWERSTATE_A3 = 3,389};390 391struct cdns_torrent_refclk_driver {392	struct clk_hw		hw;393	struct regmap_field	*cmn_fields[REFCLK_OUT_NUM_CMN_CONFIG];394	struct clk_init_data	clk_data;395};396 397#define to_cdns_torrent_refclk_driver(_hw)	\398			container_of(_hw, struct cdns_torrent_refclk_driver, hw)399 400struct cdns_torrent_derived_refclk {401	struct clk_hw		hw;402	struct regmap_field	*phy_pipe_cmn_ctrl1_0;403	struct regmap_field	*cmn_cdiag_refclk_ovrd_4;404	struct clk_init_data	clk_data;405};406 407#define to_cdns_torrent_derived_refclk(_hw)	\408			container_of(_hw, struct cdns_torrent_derived_refclk, hw)409 410struct cdns_torrent_received_refclk {411	struct clk_hw		hw;412	struct regmap_field	*phy_pipe_cmn_ctrl1_0;413	struct regmap_field	*cmn_cdiag_refclk_ovrd_4;414	struct clk_init_data	clk_data;415};416 417#define to_cdns_torrent_received_refclk(_hw)	\418			container_of(_hw, struct cdns_torrent_received_refclk, hw)419 420struct cdns_reg_pairs {421	u32 val;422	u32 off;423};424 425struct cdns_torrent_vals {426	const struct cdns_reg_pairs *reg_pairs;427	u32 num_regs;428};429 430struct cdns_torrent_vals_entry {431	u32 key;432	const struct cdns_torrent_vals *vals;433};434 435struct cdns_torrent_vals_table {436	const struct cdns_torrent_vals_entry *entries;437	u32 num_entries;438};439 440struct cdns_torrent_data {441	u8 block_offset_shift;442	u8 reg_offset_shift;443	struct cdns_torrent_vals_table link_cmn_vals_tbl;444	struct cdns_torrent_vals_table xcvr_diag_vals_tbl;445	struct cdns_torrent_vals_table pcs_cmn_vals_tbl;446	struct cdns_torrent_vals_table phy_pma_cmn_vals_tbl;447	struct cdns_torrent_vals_table cmn_vals_tbl;448	struct cdns_torrent_vals_table tx_ln_vals_tbl;449	struct cdns_torrent_vals_table rx_ln_vals_tbl;450};451 452struct cdns_regmap_cdb_context {453	struct device *dev;454	void __iomem *base;455	u8 reg_offset_shift;456};457 458static const struct cdns_torrent_vals *cdns_torrent_get_tbl_vals(const struct cdns_torrent_vals_table *tbl,459								 enum cdns_torrent_ref_clk refclk0,460								 enum cdns_torrent_ref_clk refclk1,461								 enum cdns_torrent_phy_type link0,462								 enum cdns_torrent_phy_type link1,463								 enum cdns_torrent_ssc_mode ssc)464{465	int i;466	u32 key = CDNS_TORRENT_KEY(refclk0, refclk1, link0, link1, ssc);467 468	for (i = 0; i < tbl->num_entries; i++) {469		if (tbl->entries[i].key == key)470			return tbl->entries[i].vals;471	}472 473	return NULL;474}475 476static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val)477{478	struct cdns_regmap_cdb_context *ctx = context;479	u32 offset = reg << ctx->reg_offset_shift;480 481	writew(val, ctx->base + offset);482 483	return 0;484}485 486static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val)487{488	struct cdns_regmap_cdb_context *ctx = context;489	u32 offset = reg << ctx->reg_offset_shift;490 491	*val = readw(ctx->base + offset);492	return 0;493}494 495static int cdns_regmap_dptx_write(void *context, unsigned int reg,496				  unsigned int val)497{498	struct cdns_regmap_cdb_context *ctx = context;499	u32 offset = reg;500 501	writel(val, ctx->base + offset);502 503	return 0;504}505 506static int cdns_regmap_dptx_read(void *context, unsigned int reg,507				 unsigned int *val)508{509	struct cdns_regmap_cdb_context *ctx = context;510	u32 offset = reg;511 512	*val = readl(ctx->base + offset);513	return 0;514}515 516#define TORRENT_TX_LANE_CDB_REGMAP_CONF(n) \517{ \518	.name = "torrent_tx_lane" n "_cdb", \519	.reg_stride = 1, \520	.fast_io = true, \521	.reg_write = cdns_regmap_write, \522	.reg_read = cdns_regmap_read, \523}524 525#define TORRENT_RX_LANE_CDB_REGMAP_CONF(n) \526{ \527	.name = "torrent_rx_lane" n "_cdb", \528	.reg_stride = 1, \529	.fast_io = true, \530	.reg_write = cdns_regmap_write, \531	.reg_read = cdns_regmap_read, \532}533 534static const struct regmap_config cdns_torrent_tx_lane_cdb_config[] = {535	TORRENT_TX_LANE_CDB_REGMAP_CONF("0"),536	TORRENT_TX_LANE_CDB_REGMAP_CONF("1"),537	TORRENT_TX_LANE_CDB_REGMAP_CONF("2"),538	TORRENT_TX_LANE_CDB_REGMAP_CONF("3"),539};540 541static const struct regmap_config cdns_torrent_rx_lane_cdb_config[] = {542	TORRENT_RX_LANE_CDB_REGMAP_CONF("0"),543	TORRENT_RX_LANE_CDB_REGMAP_CONF("1"),544	TORRENT_RX_LANE_CDB_REGMAP_CONF("2"),545	TORRENT_RX_LANE_CDB_REGMAP_CONF("3"),546};547 548static const struct regmap_config cdns_torrent_common_cdb_config = {549	.name = "torrent_common_cdb",550	.reg_stride = 1,551	.fast_io = true,552	.reg_write = cdns_regmap_write,553	.reg_read = cdns_regmap_read,554};555 556#define TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF(n) \557{ \558	.name = "torrent_phy_pcs_lane" n "_cdb", \559	.reg_stride = 1, \560	.fast_io = true, \561	.reg_write = cdns_regmap_write, \562	.reg_read = cdns_regmap_read, \563}564 565static const struct regmap_config cdns_torrent_phy_pcs_lane_cdb_config[] = {566	TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("0"),567	TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("1"),568	TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("2"),569	TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("3"),570};571 572static const struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = {573	.name = "torrent_phy_pcs_cmn_cdb",574	.reg_stride = 1,575	.fast_io = true,576	.reg_write = cdns_regmap_write,577	.reg_read = cdns_regmap_read,578};579 580static const struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = {581	.name = "torrent_phy_pma_cmn_cdb",582	.reg_stride = 1,583	.fast_io = true,584	.reg_write = cdns_regmap_write,585	.reg_read = cdns_regmap_read,586};587 588static const struct regmap_config cdns_torrent_dptx_phy_config = {589	.name = "torrent_dptx_phy",590	.reg_stride = 1,591	.fast_io = true,592	.reg_write = cdns_regmap_dptx_write,593	.reg_read = cdns_regmap_dptx_read,594};595 596/* PHY mmr access functions */597 598static void cdns_torrent_phy_write(struct regmap *regmap, u32 offset, u32 val)599{600	regmap_write(regmap, offset, val);601}602 603static u32 cdns_torrent_phy_read(struct regmap *regmap, u32 offset)604{605	unsigned int val;606 607	regmap_read(regmap, offset, &val);608	return val;609}610 611/* DPTX mmr access functions */612 613static void cdns_torrent_dp_write(struct regmap *regmap, u32 offset, u32 val)614{615	regmap_write(regmap, offset, val);616}617 618static u32 cdns_torrent_dp_read(struct regmap *regmap, u32 offset)619{620	u32 val;621 622	regmap_read(regmap, offset, &val);623	return val;624}625 626/*627 * Structure used to store values of PHY registers for voltage-related628 * coefficients, for particular voltage swing and pre-emphasis level. Values629 * are shared across all physical lanes.630 */631struct coefficients {632	/* Value of DRV_DIAG_TX_DRV register to use */633	u16 diag_tx_drv;634	/* Value of TX_TXCC_MGNFS_MULT_000 register to use */635	u16 mgnfs_mult;636	/* Value of TX_TXCC_CPOST_MULT_00 register to use */637	u16 cpost_mult;638};639 640/*641 * Array consists of values of voltage-related registers for sd0801 PHY. A value642 * of 0xFFFF is a placeholder for invalid combination, and will never be used.643 */644static const struct coefficients vltg_coeff[4][4] = {645	/* voltage swing 0, pre-emphasis 0->3 */646	{	{.diag_tx_drv = 0x0003, .mgnfs_mult = 0x002A,647		 .cpost_mult = 0x0000},648		{.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,649		 .cpost_mult = 0x0014},650		{.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0012,651		 .cpost_mult = 0x0020},652		{.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,653		 .cpost_mult = 0x002A}654	},655 656	/* voltage swing 1, pre-emphasis 0->3 */657	{	{.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F,658		 .cpost_mult = 0x0000},659		{.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,660		 .cpost_mult = 0x0012},661		{.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,662		 .cpost_mult = 0x001F},663		{.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,664		 .cpost_mult = 0xFFFF}665	},666 667	/* voltage swing 2, pre-emphasis 0->3 */668	{	{.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013,669		 .cpost_mult = 0x0000},670		{.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,671		 .cpost_mult = 0x0013},672		{.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,673		 .cpost_mult = 0xFFFF},674		{.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,675		 .cpost_mult = 0xFFFF}676	},677 678	/* voltage swing 3, pre-emphasis 0->3 */679	{	{.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000,680		 .cpost_mult = 0x0000},681		{.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,682		 .cpost_mult = 0xFFFF},683		{.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,684		 .cpost_mult = 0xFFFF},685		{.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF,686		 .cpost_mult = 0xFFFF}687	}688};689 690static const char *cdns_torrent_get_phy_type(enum cdns_torrent_phy_type phy_type)691{692	switch (phy_type) {693	case TYPE_DP:694		return "DisplayPort";695	case TYPE_PCIE:696		return "PCIe";697	case TYPE_SGMII:698		return "SGMII";699	case TYPE_QSGMII:700		return "QSGMII";701	case TYPE_USB:702		return "USB";703	case TYPE_USXGMII:704		return "USXGMII";705	default:706		return "None";707	}708}709 710/*711 * Set registers responsible for enabling and configuring SSC, with second and712 * third register values provided by parameters.713 */714static715void cdns_torrent_dp_enable_ssc_19_2mhz(struct cdns_torrent_phy *cdns_phy,716					u32 ctrl2_val, u32 ctrl3_val)717{718	struct regmap *regmap = cdns_phy->regmap_common_cdb;719 720	cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);721	cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);722	cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl3_val);723	cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);724	cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);725	cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);726	cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl3_val);727	cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);728}729 730static731void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy,732					     u32 rate, bool ssc)733{734	struct regmap *regmap = cdns_phy->regmap_common_cdb;735 736	/* Assumes 19.2 MHz refclock */737	switch (rate) {738	/* Setting VCO for 10.8GHz */739	case 2700:740	case 5400:741		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0119);742		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000);743		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);744		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00BC);745		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0012);746		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0119);747		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000);748		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);749		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00BC);750		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0012);751		if (ssc)752			cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A, 0x006A);753		break;754	/* Setting VCO for 9.72GHz */755	case 1620:756	case 2430:757	case 3240:758		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01FA);759		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000);760		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);761		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0152);762		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);763		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01FA);764		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000);765		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);766		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0152);767		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);768		if (ssc)769			cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD, 0x0069);770		break;771	/* Setting VCO for 8.64GHz */772	case 2160:773	case 4320:774		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01C2);775		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);776		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);777		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x012C);778		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);779		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01C2);780		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);781		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);782		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x012C);783		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);784		if (ssc)785			cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536, 0x0069);786		break;787	/* Setting VCO for 8.1GHz */788	case 8100:789		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01A5);790		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xE000);791		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);792		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x011A);793		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);794		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01A5);795		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xE000);796		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);797		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x011A);798		cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);799		if (ssc)800			cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7, 0x006A);801		break;802	}803 804	if (ssc) {805		cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E);806		cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);807		cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E);808		cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);809	} else {810		cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260);811		cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260);812		/* Set reset register values to disable SSC */813		cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002);814		cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000);815		cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000);816		cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000);817		cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);818		cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002);819		cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000);820		cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000);821		cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000);822		cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);823	}824 825	cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x0099);826	cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x0099);827	cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x0099);828	cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099);829}830 831/*832 * Set registers responsible for enabling and configuring SSC, with second833 * register value provided by a parameter.834 */835static void cdns_torrent_dp_enable_ssc_25mhz(struct cdns_torrent_phy *cdns_phy,836					     u32 ctrl2_val)837{838	struct regmap *regmap = cdns_phy->regmap_common_cdb;839 840	cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001);841	cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val);842	cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x007F);843	cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003);844	cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001);845	cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val);846	cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x007F);847	cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003);848}849 850static851void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy,852					   u32 rate, bool ssc)853{854	struct regmap *regmap = cdns_phy->regmap_common_cdb;855 856	/* Assumes 25 MHz refclock */857	switch (rate) {858	/* Setting VCO for 10.8GHz */859	case 2700:860	case 5400:861		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01B0);862		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);863		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);864		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0120);865		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01B0);866		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);867		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);868		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0120);869		if (ssc)870			cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x0423);871		break;872	/* Setting VCO for 9.72GHz */873	case 1620:874	case 2430:875	case 3240:876		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0184);877		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xCCCD);878		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);879		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0104);880		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0184);881		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xCCCD);882		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);883		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0104);884		if (ssc)885			cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x03B9);886		break;887	/* Setting VCO for 8.64GHz */888	case 2160:889	case 4320:890		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0159);891		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x999A);892		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);893		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00E7);894		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0159);895		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x999A);896		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);897		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00E7);898		if (ssc)899			cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x034F);900		break;901	/* Setting VCO for 8.1GHz */902	case 8100:903		cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0144);904		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000);905		cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);906		cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00D8);907		cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0144);908		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000);909		cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);910		cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00D8);911		if (ssc)912			cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x031A);913		break;914	}915 916	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);917	cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);918 919	if (ssc) {920		cdns_torrent_phy_write(regmap,921				       CMN_PLL0_VCOCAL_PLLCNT_START, 0x0315);922		cdns_torrent_phy_write(regmap,923				       CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);924		cdns_torrent_phy_write(regmap,925				       CMN_PLL1_VCOCAL_PLLCNT_START, 0x0315);926		cdns_torrent_phy_write(regmap,927				       CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);928	} else {929		cdns_torrent_phy_write(regmap,930				       CMN_PLL0_VCOCAL_PLLCNT_START, 0x0317);931		cdns_torrent_phy_write(regmap,932				       CMN_PLL1_VCOCAL_PLLCNT_START, 0x0317);933		/* Set reset register values to disable SSC */934		cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002);935		cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000);936		cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000);937		cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000);938		cdns_torrent_phy_write(regmap,939				       CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);940		cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002);941		cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000);942		cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000);943		cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000);944		cdns_torrent_phy_write(regmap,945				       CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);946	}947 948	cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x00C7);949	cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7);950	cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x00C7);951	cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7);952}953 954static955void cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(struct cdns_torrent_phy *cdns_phy,956					    u32 rate, bool ssc)957{958	struct regmap *regmap = cdns_phy->regmap_common_cdb;959 960	/* Assumes 100 MHz refclock */961	switch (rate) {962	/* Setting VCO for 10.8GHz */963	case 2700:964	case 5400:965		if (cdns_phy->dp_pll & DP_PLL0)966			cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_FBH_OVRD_M0, 0x0022);967 968		if (cdns_phy->dp_pll & DP_PLL1) {969			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0028);970			cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBH_OVRD_M0, 0x0022);971			cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBL_OVRD_M0, 0x000C);972		}973		break;974	/* Setting VCO for 9.72GHz */975	case 1620:976	case 2430:977	case 3240:978		if (cdns_phy->dp_pll & DP_PLL0) {979			cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);980			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);981			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);982			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);983			cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0061);984			cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x3333);985			cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);986			cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0042);987			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);988		}989		if (cdns_phy->dp_pll & DP_PLL1) {990			cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);991			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);992			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);993			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);994			cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0061);995			cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x3333);996			cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);997			cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0042);998			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);999		}1000		break;1001	/* Setting VCO for 8.64GHz */1002	case 2160:1003	case 4320:1004		if (cdns_phy->dp_pll & DP_PLL0) {1005			cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);1006			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);1007			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);1008			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);1009			cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0056);1010			cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x6666);1011			cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);1012			cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x003A);1013			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);1014		}1015		if (cdns_phy->dp_pll & DP_PLL1) {1016			cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);1017			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);1018			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);1019			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);1020			cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0056);1021			cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x6666);1022			cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);1023			cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x003A);1024			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);1025		}1026		break;1027	/* Setting VCO for 8.1GHz */1028	case 8100:1029		if (cdns_phy->dp_pll & DP_PLL0) {1030			cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004);1031			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509);1032			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00);1033			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08);1034			cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0051);1035			cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002);1036			cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0036);1037			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);1038		}1039		if (cdns_phy->dp_pll & DP_PLL1) {1040			cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004);1041			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509);1042			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00);1043			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08);1044			cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0051);1045			cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002);1046			cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0036);1047			cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);1048		}1049		break;1050	}1051}1052 1053/* Set PLL used for DP configuration */1054static int cdns_torrent_dp_get_pll(struct cdns_torrent_phy *cdns_phy,1055				   enum cdns_torrent_phy_type phy_t2)1056{1057	switch (phy_t2) {1058	case TYPE_PCIE:1059	case TYPE_USB:1060		cdns_phy->dp_pll = DP_PLL1;1061		break;1062	case TYPE_SGMII:1063	case TYPE_QSGMII:1064		cdns_phy->dp_pll = DP_PLL0;1065		break;1066	case TYPE_NONE:1067		cdns_phy->dp_pll = DP_PLL0 | DP_PLL1;1068		break;1069	default:1070		dev_err(cdns_phy->dev, "Unsupported PHY configuration\n");1071		return -EINVAL;1072	}1073 1074	return 0;1075}1076 1077/*1078 * Enable or disable PLL for selected lanes.1079 */1080static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy,1081				      struct cdns_torrent_inst *inst,1082				      struct phy_configure_opts_dp *dp,1083				      bool enable)1084{1085	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;1086	u32 rd_val, pll_ack_val;1087	int ret;1088 1089	/*1090	 * Used to determine, which bits to check for or enable in1091	 * PHY_PMA_XCVR_PLLCLK_EN register.1092	 */1093	u32 pll_bits;1094	/* Used to enable or disable lanes. */1095	u32 pll_val;1096 1097	/* Select values of registers and mask, depending on enabled lane count. */1098	pll_val = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_PLLCLK_EN);1099 1100	if (enable) {1101		pll_bits = ((1 << dp->lanes) - 1);1102		pll_val |= pll_bits;1103		pll_ack_val = pll_bits;1104	} else {1105		pll_bits = ((1 << inst->num_lanes) - 1);1106		pll_val &= (~pll_bits);1107		pll_ack_val = 0;1108	}1109 1110	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_val);1111 1112	/* Wait for acknowledgment from PHY. */1113	ret = regmap_read_poll_timeout(regmap,1114				       PHY_PMA_XCVR_PLLCLK_EN_ACK,1115				       rd_val,1116				       (rd_val & pll_bits) == pll_ack_val,1117				       0, POLL_TIMEOUT_US);1118	ndelay(100);1119	return ret;1120}1121 1122static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy,1123					   struct cdns_torrent_inst *inst,1124					   u32 num_lanes,1125					   enum phy_powerstate powerstate)1126{1127	/* Register value for power state for a single byte. */1128	u32 value_part, i;1129	u32 value = 0;1130	u32 mask = 0;1131	u32 read_val;1132	int ret;1133	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;1134 1135	switch (powerstate) {1136	case (POWERSTATE_A0):1137		value_part = 0x01U;1138		break;1139	case (POWERSTATE_A2):1140		value_part = 0x04U;1141		break;1142	default:1143		/* Powerstate A3 */1144		value_part = 0x08U;1145		break;1146	}1147 1148	/* Select values of registers and mask, depending on enabled lane count. */1149 1150	for (i = 0; i < num_lanes; i++) {1151		value |= (value_part << PHY_POWER_STATE_LN(i));1152		mask |= (PMA_XCVR_POWER_STATE_REQ_LN_MASK << PHY_POWER_STATE_LN(i));1153	}1154 1155	/* Set power state A<n>. */1156	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, value);1157	/* Wait, until PHY acknowledges power state completion. */1158	ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_POWER_STATE_ACK,1159				       read_val, (read_val & mask) == value, 0,1160				       POLL_TIMEOUT_US);1161	if (ret)1162		return ret;1163 1164	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000);1165	ndelay(100);1166 1167	return ret;1168}1169 1170static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy,1171			       struct cdns_torrent_inst *inst, u32 num_lanes)1172{1173	unsigned int read_val;1174	int ret;1175	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;1176 1177	/*1178	 * waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the1179	 * master lane1180	 */1181	ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK,1182				       read_val, read_val & 1,1183				       0, POLL_TIMEOUT_US);1184	if (ret == -ETIMEDOUT) {1185		dev_err(cdns_phy->dev,1186			"timeout waiting for link PLL clock enable ack\n");1187		return ret;1188	}1189 1190	ndelay(100);1191 1192	ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, num_lanes,1193					      POWERSTATE_A2);1194	if (ret)1195		return ret;1196 1197	ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, num_lanes,1198					      POWERSTATE_A0);1199 1200	return ret;1201}1202 1203static int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy)1204{1205	unsigned int reg;1206	int ret;1207	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;1208 1209	ret = regmap_read_poll_timeout(regmap, PHY_PMA_CMN_READY, reg,1210				       reg & 1, 0, POLL_TIMEOUT_US);1211	if (ret == -ETIMEDOUT) {1212		dev_err(cdns_phy->dev,1213			"timeout waiting for PMA common ready\n");1214		return -ETIMEDOUT;1215	}1216 1217	return 0;1218}1219 1220static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy,1221					 struct cdns_torrent_inst *inst,1222					 u32 rate, u32 num_lanes)1223{1224	unsigned int clk_sel_val = 0;1225	unsigned int hsclk_div_val = 0;1226	unsigned int i;1227 1228	switch (rate) {1229	case 1620:1230		clk_sel_val = 0x0f01;1231		hsclk_div_val = 2;1232		break;1233	case 2160:1234	case 2430:1235	case 2700:1236		clk_sel_val = 0x0701;1237		hsclk_div_val = 1;1238		break;1239	case 3240:1240		clk_sel_val = 0x0b00;1241		hsclk_div_val = 2;1242		break;1243	case 4320:1244	case 5400:1245		clk_sel_val = 0x0301;1246		hsclk_div_val = 0;1247		break;1248	case 8100:1249		clk_sel_val = 0x0200;1250		hsclk_div_val = 0;1251		break;1252	}1253 1254	if (cdns_phy->dp_pll & DP_PLL0)1255		cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,1256				       CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val);1257 1258	if (cdns_phy->dp_pll & DP_PLL1)1259		cdns_torrent_phy_write(cdns_phy->regmap_common_cdb,1260				       CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val);1261 1262	/* PMA lane configuration to deal with multi-link operation */1263	for (i = 0; i < num_lanes; i++)1264		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + i],1265				       XCVR_DIAG_HSCLK_DIV, hsclk_div_val);1266}1267 1268/*1269 * Perform register operations related to setting link rate, once powerstate is1270 * set and PLL disable request was processed.1271 */1272static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy,1273					  struct cdns_torrent_inst *inst,1274					  struct phy_configure_opts_dp *dp)1275{1276	u32 read_val, field_val;1277	int ret;1278 1279	/*1280	 * Disable the associated PLL (cmn_pll0_en or cmn_pll1_en) before1281	 * re-programming the new data rate.1282	 */1283	ret = regmap_field_read(cdns_phy->phy_pma_pll_raw_ctrl, &field_val);1284	if (ret)1285		return ret;1286	field_val &= ~(cdns_phy->dp_pll);1287	regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, field_val);1288 1289	/*1290	 * Wait for PLL ready de-assertion.1291	 * For PLL0 - PHY_PMA_CMN_CTRL2[2] == 11292	 * For PLL1 - PHY_PMA_CMN_CTRL2[3] == 11293	 */1294	if (cdns_phy->dp_pll & DP_PLL0) {1295		ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,1296						     read_val,1297						     ((read_val >> 2) & 0x01) != 0,1298						     0, POLL_TIMEOUT_US);1299		if (ret)1300			return ret;1301	}1302 1303	if ((cdns_phy->dp_pll & DP_PLL1) && cdns_phy->nsubnodes != 1) {1304		ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,1305						     read_val,1306						     ((read_val >> 3) & 0x01) != 0,1307						     0, POLL_TIMEOUT_US);1308		if (ret)1309			return ret;1310	}1311	ndelay(200);1312 1313	/* DP Rate Change - VCO Output settings. */1314	if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)1315		/* PMA common configuration 19.2MHz */1316		cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate, dp->ssc);1317	else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)1318		/* PMA common configuration 25MHz */1319		cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate, dp->ssc);1320	else if (cdns_phy->ref_clk_rate == CLK_100_MHZ)1321		/* PMA common configuration 100MHz */1322		cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy, dp->link_rate, dp->ssc);1323 1324	cdns_torrent_dp_pma_cmn_rate(cdns_phy, inst, dp->link_rate, dp->lanes);1325 1326	/* Enable the associated PLL (cmn_pll0_en or cmn_pll1_en) */1327	ret = regmap_field_read(cdns_phy->phy_pma_pll_raw_ctrl, &field_val);1328	if (ret)1329		return ret;1330	field_val |= cdns_phy->dp_pll;1331	regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, field_val);1332 1333	/*1334	 * Wait for PLL ready assertion.1335	 * For PLL0 - PHY_PMA_CMN_CTRL2[0] == 11336	 * For PLL1 - PHY_PMA_CMN_CTRL2[1] == 11337	 */1338	if (cdns_phy->dp_pll & DP_PLL0) {1339		ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,1340						     read_val,1341						     (read_val & 0x01) != 0,1342						     0, POLL_TIMEOUT_US);1343		if (ret)1344			return ret;1345	}1346 1347	if ((cdns_phy->dp_pll & DP_PLL1) && cdns_phy->nsubnodes != 1)1348		ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2,1349						     read_val,1350						     ((read_val >> 1) & 0x01) != 0,1351						     0, POLL_TIMEOUT_US);1352 1353	return ret;1354}1355 1356/*1357 * Verify, that parameters to configure PHY with are correct.1358 */1359static int cdns_torrent_dp_verify_config(struct cdns_torrent_inst *inst,1360					 struct phy_configure_opts_dp *dp)1361{1362	u8 i;1363 1364	/* If changing link rate was required, verify it's supported. */1365	if (dp->set_rate) {1366		switch (dp->link_rate) {1367		case 1620:1368		case 2160:1369		case 2430:1370		case 2700:1371		case 3240:1372		case 4320:1373		case 5400:1374		case 8100:1375			/* valid bit rate */1376			break;1377		default:1378			return -EINVAL;1379		}1380	}1381 1382	/* Verify lane count. */1383	switch (dp->lanes) {1384	case 1:1385	case 2:1386	case 4:1387		/* valid lane count. */1388		break;1389	default:1390		return -EINVAL;1391	}1392 1393	/* Check against actual number of PHY's lanes. */1394	if (dp->lanes > inst->num_lanes)1395		return -EINVAL;1396 1397	/*1398	 * If changing voltages is required, check swing and pre-emphasis1399	 * levels, per-lane.1400	 */1401	if (dp->set_voltages) {1402		/* Lane count verified previously. */1403		for (i = 0; i < dp->lanes; i++) {1404			if (dp->voltage[i] > 3 || dp->pre[i] > 3)1405				return -EINVAL;1406 1407			/* Sum of voltage swing and pre-emphasis levels cannot1408			 * exceed 3.1409			 */1410			if (dp->voltage[i] + dp->pre[i] > 3)1411				return -EINVAL;1412		}1413	}1414 1415	return 0;1416}1417 1418/* Set power state A0 and PLL clock enable to 0 on enabled lanes. */1419static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy,1420				       struct cdns_torrent_inst *inst,1421				       u32 num_lanes)1422{1423	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;1424	u32 pwr_state = cdns_torrent_dp_read(regmap,1425					     PHY_PMA_XCVR_POWER_STATE_REQ);1426	u32 pll_clk_en = cdns_torrent_dp_read(regmap,1427					      PHY_PMA_XCVR_PLLCLK_EN);1428	u32 i;1429 1430	for (i = 0; i < num_lanes; i++) {1431		pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK1432			     << PHY_POWER_STATE_LN(inst->mlane + i));1433 1434		pll_clk_en &= ~(0x01U << (inst->mlane + i));1435	}1436 1437	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state);1438	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en);1439}1440 1441/* Configure lane count as required. */1442static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy,1443				     struct cdns_torrent_inst *inst,1444				     struct phy_configure_opts_dp *dp)1445{1446	u32 value, i;1447	int ret;1448	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;1449	u8 lane_mask = (1 << dp->lanes) - 1;1450	u8 pma_tx_elec_idle_mask = 0;1451	u32 clane = inst->mlane;1452 1453	lane_mask <<= clane;1454 1455	value = cdns_torrent_dp_read(regmap, PHY_RESET);1456	/* clear pma_tx_elec_idle_ln_* bits. */1457	pma_tx_elec_idle_mask = ((1 << inst->num_lanes) - 1) << clane;1458 1459	pma_tx_elec_idle_mask <<= PMA_TX_ELEC_IDLE_SHIFT;1460 1461	value &= ~pma_tx_elec_idle_mask;1462 1463	/* Assert pma_tx_elec_idle_ln_* for disabled lanes. */1464	value |= ((~lane_mask) << PMA_TX_ELEC_IDLE_SHIFT) &1465		 pma_tx_elec_idle_mask;1466 1467	cdns_torrent_dp_write(regmap, PHY_RESET, value);1468 1469	/* reset the link by asserting master lane phy_l0*_reset_n low */1470	cdns_torrent_dp_write(regmap, PHY_RESET,1471			      value & (~(1 << clane)));1472 1473	/*1474	 * Assert lane reset on unused lanes and master lane so they remain in reset1475	 * and powered down when re-enabling the link1476	 */1477	for (i = 0; i < inst->num_lanes; i++)1478		value &= (~(1 << (clane + i)));1479 1480	for (i = 1; i < inst->num_lanes; i++)1481		value |= ((1 << (clane + i)) & lane_mask);1482 1483	cdns_torrent_dp_write(regmap, PHY_RESET, value);1484 1485	cdns_torrent_dp_set_a0_pll(cdns_phy, inst, dp->lanes);1486 1487	/* release phy_l0*_reset_n based on used laneCount */1488	for (i = 0; i < inst->num_lanes; i++)1489		value &= (~(1 << (clane + i)));1490 1491	for (i = 0; i < inst->num_lanes; i++)1492		value |= ((1 << (clane + i)) & lane_mask);1493 1494	cdns_torrent_dp_write(regmap, PHY_RESET, value);1495 1496	/* Wait, until PHY gets ready after releasing PHY reset signal. */1497	ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);1498	if (ret)1499		return ret;1500 1501	ndelay(100);1502 1503	/* release pma_xcvr_pllclk_en_ln_*, only for the master lane */1504	value = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_PLLCLK_EN);1505	value |= (1 << clane);1506	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, value);1507 1508	ret = cdns_torrent_dp_run(cdns_phy, inst, dp->lanes);1509 1510	return ret;1511}1512 1513/* Configure link rate as required. */1514static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy,1515				    struct cdns_torrent_inst *inst,1516				    struct phy_configure_opts_dp *dp)1517{1518	int ret;1519 1520	ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes,1521					      POWERSTATE_A3);1522	if (ret)1523		return ret;1524	ret = cdns_torrent_dp_set_pll_en(cdns_phy, inst, dp, false);1525	if (ret)1526		return ret;1527	ndelay(200);1528 1529	ret = cdns_torrent_dp_configure_rate(cdns_phy, inst, dp);1530	if (ret)1531		return ret;1532	ndelay(200);1533 1534	ret = cdns_torrent_dp_set_pll_en(cdns_phy, inst, dp, true);1535	if (ret)1536		return ret;1537	ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes,1538					      POWERSTATE_A2);1539	if (ret)1540		return ret;1541	ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes,1542					      POWERSTATE_A0);1543	if (ret)1544		return ret;1545	ndelay(900);1546 1547	return ret;1548}1549 1550/* Configure voltage swing and pre-emphasis for all enabled lanes. */1551static void cdns_torrent_dp_set_voltages(struct cdns_torrent_phy *cdns_phy,1552					 struct cdns_torrent_inst *inst,1553					 struct phy_configure_opts_dp *dp)1554{1555	u8 lane;1556	u16 val;1557 1558	for (lane = 0; lane < dp->lanes; lane++) {1559		val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],1560					    TX_DIAG_ACYA);1561		/*1562		 * Write 1 to register bit TX_DIAG_ACYA[0] to freeze the1563		 * current state of the analog TX driver.1564		 */1565		val |= TX_DIAG_ACYA_HBDC_MASK;1566		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],1567				       TX_DIAG_ACYA, val);1568 1569		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],1570				       TX_TXCC_CTRL, 0x08A4);1571		val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].diag_tx_drv;1572		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],1573				       DRV_DIAG_TX_DRV, val);1574		val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].mgnfs_mult;1575		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],1576				       TX_TXCC_MGNFS_MULT_000,1577				       val);1578		val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].cpost_mult;1579		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],1580				       TX_TXCC_CPOST_MULT_00,1581				       val);1582 1583		val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],1584					    TX_DIAG_ACYA);1585		/*1586		 * Write 0 to register bit TX_DIAG_ACYA[0] to allow the state of1587		 * analog TX driver to reflect the new programmed one.1588		 */1589		val &= ~TX_DIAG_ACYA_HBDC_MASK;1590		cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane],1591				       TX_DIAG_ACYA, val);1592	}1593};1594 1595static int cdns_torrent_dp_configure(struct phy *phy,1596				     union phy_configure_opts *opts)1597{1598	struct cdns_torrent_inst *inst = phy_get_drvdata(phy);1599	struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);1600	int ret;1601 1602	if (cdns_phy->already_configured)1603		return 0;1604 1605	ret = cdns_torrent_dp_verify_config(inst, &opts->dp);1606	if (ret) {1607		dev_err(&phy->dev, "invalid params for phy configure\n");1608		return ret;1609	}1610 1611	if (opts->dp.set_lanes) {1612		ret = cdns_torrent_dp_set_lanes(cdns_phy, inst, &opts->dp);1613		if (ret) {1614			dev_err(&phy->dev, "cdns_torrent_dp_set_lanes failed\n");1615			return ret;1616		}1617	}1618 1619	if (opts->dp.set_rate) {1620		ret = cdns_torrent_dp_set_rate(cdns_phy, inst, &opts->dp);1621		if (ret) {1622			dev_err(&phy->dev, "cdns_torrent_dp_set_rate failed\n");1623			return ret;1624		}1625	}1626 1627	if (opts->dp.set_voltages)1628		cdns_torrent_dp_set_voltages(cdns_phy, inst, &opts->dp);1629 1630	return ret;1631}1632 1633static int cdns_torrent_phy_on(struct phy *phy)1634{1635	struct cdns_torrent_inst *inst = phy_get_drvdata(phy);1636	struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);1637	u32 read_val;1638	int ret;1639 1640	if (cdns_phy->already_configured) {1641		/* Give 5ms to 10ms delay for the PIPE clock to be stable */1642		usleep_range(5000, 10000);1643		return 0;1644	}1645 1646	if (cdns_phy->nsubnodes == 1) {1647		/* Take the PHY lane group out of reset */1648		reset_control_deassert(inst->lnk_rst);1649 1650		/* Take the PHY out of reset */1651		ret = reset_control_deassert(cdns_phy->phy_rst);1652		if (ret)1653			return ret;1654	}1655 1656	/*1657	 * Wait for cmn_ready assertion1658	 * PHY_PMA_CMN_CTRL1[0] == 11659	 */1660	ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1,1661					     read_val, read_val, 1000,1662					     PLL_LOCK_TIMEOUT);1663	if (ret) {1664		dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n");1665		return ret;1666	}1667 1668	if (inst->phy_type == TYPE_PCIE || inst->phy_type == TYPE_USB) {1669		ret = regmap_field_read_poll_timeout(cdns_phy->phy_pcs_iso_link_ctrl_1[inst->mlane],1670						     read_val, !read_val, 1000,1671						     PLL_LOCK_TIMEOUT);1672		if (ret == -ETIMEDOUT) {1673			dev_err(cdns_phy->dev, "Timeout waiting for PHY status ready\n");1674			return ret;1675		}1676	}1677 1678	return 0;1679}1680 1681static int cdns_torrent_phy_off(struct phy *phy)1682{1683	struct cdns_torrent_inst *inst = phy_get_drvdata(phy);1684	struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);1685	int ret;1686 1687	if (cdns_phy->nsubnodes != 1)1688		return 0;1689 1690	ret = reset_control_assert(cdns_phy->phy_rst);1691	if (ret)1692		return ret;1693 1694	return reset_control_assert(inst->lnk_rst);1695}1696 1697static void cdns_torrent_dp_common_init(struct cdns_torrent_phy *cdns_phy,1698					struct cdns_torrent_inst *inst)1699{1700	struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg;1701	unsigned char lane_bits;1702	u32 val;1703 1704	cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */1705 1706	/*1707	 * Set lines power state to A01708	 * Set lines pll clk enable to 01709	 */1710	cdns_torrent_dp_set_a0_pll(cdns_phy, inst, inst->num_lanes);1711 1712	/*1713	 * release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on1714	 * used lanes1715	 */1716	lane_bits = (1 << inst->num_lanes) - 1;1717 1718	val = cdns_torrent_dp_read(regmap, PHY_RESET);1719	val |= (0xF & lane_bits);1720	val &= ~(lane_bits << 4);1721	cdns_torrent_dp_write(regmap, PHY_RESET, val);1722 1723	/* release pma_xcvr_pllclk_en_ln_*, only for the master lane */1724	val = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_PLLCLK_EN);1725	val |= 1;1726	cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, val);1727 1728	/*1729	 * PHY PMA registers configuration functions1730	 * Initialize PHY with max supported link rate, without SSC.1731	 */1732	if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ)1733		cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy,1734							cdns_phy->max_bit_rate,1735							false);1736	else if (cdns_phy->ref_clk_rate == CLK_25_MHZ)1737		cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy,1738						      cdns_phy->max_bit_rate,1739						      false);1740	else if (cdns_phy->ref_clk_rate == CLK_100_MHZ)1741		cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy,1742						       cdns_phy->max_bit_rate,1743						       false);1744 1745	cdns_torrent_dp_pma_cmn_rate(cdns_phy, inst, cdns_phy->max_bit_rate,1746				     inst->num_lanes);1747 1748	/* take out of reset */1749	regmap_field_write(cdns_phy->phy_reset_ctrl, 0x1);1750}1751 1752static int cdns_torrent_dp_start(struct cdns_torrent_phy *cdns_phy,1753				 struct cdns_torrent_inst *inst,1754				 struct phy *phy)1755{1756	int ret;1757 1758	ret = cdns_torrent_phy_on(phy);1759	if (ret)1760		return ret;1761 1762	ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy);1763	if (ret)1764		return ret;1765 1766	ret = cdns_torrent_dp_run(cdns_phy, inst, inst->num_lanes);1767 1768	return ret;1769}1770 1771static int cdns_torrent_dp_init(struct phy *phy)1772{1773	struct cdns_torrent_inst *inst = phy_get_drvdata(phy);1774	struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);1775	int ret;1776 1777	switch (cdns_phy->ref_clk_rate) {1778	case CLK_19_2_MHZ:1779	case CLK_25_MHZ:1780	case CLK_100_MHZ:1781		/* Valid Ref Clock Rate */1782		break;1783	default:1784		dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n");1785		return -EINVAL;1786	}1787 1788	ret = cdns_torrent_dp_get_pll(cdns_phy, TYPE_NONE);1789	if (ret)1790		return ret;1791 1792	cdns_torrent_dp_common_init(cdns_phy, inst);1793 1794	return cdns_torrent_dp_start(cdns_phy, inst, phy);1795}1796 1797static int cdns_torrent_dp_multilink_init(struct cdns_torrent_phy *cdns_phy,1798					  struct cdns_torrent_inst *inst,1799					  struct phy *phy)1800{1801	if (cdns_phy->ref_clk_rate != CLK_100_MHZ) {1802		dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n");1803		return -EINVAL;1804	}1805 1806	cdns_torrent_dp_common_init(cdns_phy, inst);1807 1808	return cdns_torrent_dp_start(cdns_phy, inst, phy);1809}1810 1811static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw)1812{1813	struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);1814 1815	regmap_field_write(derived_refclk->cmn_cdiag_refclk_ovrd_4, 1);1816	regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 1);1817 1818	return 0;1819}1820 1821static void cdns_torrent_derived_refclk_disable(struct clk_hw *hw)1822{1823	struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);1824 1825	regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 0);1826	regmap_field_write(derived_refclk->cmn_cdiag_refclk_ovrd_4, 0);1827}1828 1829static int cdns_torrent_derived_refclk_is_enabled(struct clk_hw *hw)1830{1831	struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw);1832	int val;1833 1834	regmap_field_read(derived_refclk->cmn_cdiag_refclk_ovrd_4, &val);1835 1836	return !!val;1837}1838 1839static const struct clk_ops cdns_torrent_derived_refclk_ops = {1840	.enable = cdns_torrent_derived_refclk_enable,1841	.disable = cdns_torrent_derived_refclk_disable,1842	.is_enabled = cdns_torrent_derived_refclk_is_enabled,1843};1844 1845static int cdns_torrent_derived_refclk_register(struct cdns_torrent_phy *cdns_phy)1846{1847	struct cdns_torrent_derived_refclk *derived_refclk;1848	struct device *dev = cdns_phy->dev;1849	struct clk_init_data *init;1850	const char *parent_name;1851	char clk_name[100];1852	struct clk_hw *hw;1853	struct clk *clk;1854	int ret;1855 1856	derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL);1857	if (!derived_refclk)1858		return -ENOMEM;1859 1860	snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),1861		 clk_names[CDNS_TORRENT_DERIVED_REFCLK]);1862 1863	clk = devm_clk_get_optional(dev, "phy_en_refclk");1864	if (IS_ERR(clk)) {1865		dev_err(dev, "No parent clock for derived_refclk\n");1866		return PTR_ERR(clk);1867	}1868 1869	init = &derived_refclk->clk_data;1870 1871	if (clk) {1872		parent_name = __clk_get_name(clk);1873		init->parent_names = &parent_name;1874		init->num_parents = 1;1875	}1876	init->ops = &cdns_torrent_derived_refclk_ops;1877	init->flags = 0;1878	init->name = clk_name;1879 1880	derived_refclk->phy_pipe_cmn_ctrl1_0 = cdns_phy->phy_pipe_cmn_ctrl1_0;1881	derived_refclk->cmn_cdiag_refclk_ovrd_4 = cdns_phy->cmn_cdiag_refclk_ovrd_4;1882 1883	derived_refclk->hw.init = init;1884 1885	hw = &derived_refclk->hw;1886	ret = devm_clk_hw_register(dev, hw);1887	if (ret)1888		return ret;1889 1890	cdns_phy->clk_hw_data->hws[CDNS_TORRENT_DERIVED_REFCLK] = hw;1891 1892	return 0;1893}1894 1895static int cdns_torrent_received_refclk_enable(struct clk_hw *hw)1896{1897	struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw);1898 1899	regmap_field_write(received_refclk->phy_pipe_cmn_ctrl1_0, 1);1900 1901	return 0;1902}1903 1904static void cdns_torrent_received_refclk_disable(struct clk_hw *hw)1905{1906	struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw);1907 1908	regmap_field_write(received_refclk->phy_pipe_cmn_ctrl1_0, 0);1909}1910 1911static int cdns_torrent_received_refclk_is_enabled(struct clk_hw *hw)1912{1913	struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw);1914	int val, cmn_val;1915 1916	regmap_field_read(received_refclk->phy_pipe_cmn_ctrl1_0, &val);1917	regmap_field_read(received_refclk->cmn_cdiag_refclk_ovrd_4, &cmn_val);1918 1919	return val && !cmn_val;1920}1921 1922static const struct clk_ops cdns_torrent_received_refclk_ops = {1923	.enable = cdns_torrent_received_refclk_enable,1924	.disable = cdns_torrent_received_refclk_disable,1925	.is_enabled = cdns_torrent_received_refclk_is_enabled,1926};1927 1928static int cdns_torrent_received_refclk_register(struct cdns_torrent_phy *cdns_phy)1929{1930	struct cdns_torrent_received_refclk *received_refclk;1931	struct device *dev = cdns_phy->dev;1932	struct clk_init_data *init;1933	const char *parent_name;1934	char clk_name[100];1935	struct clk_hw *hw;1936	struct clk *clk;1937	int ret;1938 1939	received_refclk = devm_kzalloc(dev, sizeof(*received_refclk), GFP_KERNEL);1940	if (!received_refclk)1941		return -ENOMEM;1942 1943	snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),1944		 clk_names[CDNS_TORRENT_RECEIVED_REFCLK]);1945 1946	clk = devm_clk_get_optional(dev, "phy_en_refclk");1947	if (IS_ERR(clk)) {1948		dev_err(dev, "No parent clock for received_refclk\n");1949		return PTR_ERR(clk);1950	}1951 1952	init = &received_refclk->clk_data;1953 1954	if (clk) {1955		parent_name = __clk_get_name(clk);1956		init->parent_names = &parent_name;1957		init->num_parents = 1;1958	}1959	init->ops = &cdns_torrent_received_refclk_ops;1960	init->flags = 0;1961	init->name = clk_name;1962 1963	received_refclk->phy_pipe_cmn_ctrl1_0 = cdns_phy->phy_pipe_cmn_ctrl1_0;1964	received_refclk->cmn_cdiag_refclk_ovrd_4 = cdns_phy->cmn_cdiag_refclk_ovrd_4;1965 1966	received_refclk->hw.init = init;1967 1968	hw = &received_refclk->hw;1969	ret = devm_clk_hw_register(dev, hw);1970	if (ret)1971		return ret;1972 1973	cdns_phy->clk_hw_data->hws[CDNS_TORRENT_RECEIVED_REFCLK] = hw;1974 1975	return 0;1976}1977 1978static int cdns_torrent_refclk_driver_enable(struct clk_hw *hw)1979{1980	struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);1981 1982	regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_6], 0);1983	regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_5], 1);1984	regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 0);1985 1986	return 0;1987}1988 1989static void cdns_torrent_refclk_driver_disable(struct clk_hw *hw)1990{1991	struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);1992 1993	regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 1);1994}1995 1996static int cdns_torrent_refclk_driver_is_enabled(struct clk_hw *hw)1997{1998	struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);1999	int val;2000 2001	regmap_field_read(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], &val);2002 2003	return !val;2004}2005 2006static u8 cdns_torrent_refclk_driver_get_parent(struct clk_hw *hw)2007{2008	struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);2009	unsigned int val;2010 2011	regmap_field_read(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], &val);2012	return clk_mux_val_to_index(hw, cdns_torrent_refclk_driver_mux_table, 0, val);2013}2014 2015static int cdns_torrent_refclk_driver_set_parent(struct clk_hw *hw, u8 index)2016{2017	struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw);2018	unsigned int val;2019 2020	val = cdns_torrent_refclk_driver_mux_table[index];2021	return regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], val);2022}2023 2024static const struct clk_ops cdns_torrent_refclk_driver_ops = {2025	.enable = cdns_torrent_refclk_driver_enable,2026	.disable = cdns_torrent_refclk_driver_disable,2027	.is_enabled = cdns_torrent_refclk_driver_is_enabled,2028	.determine_rate = __clk_mux_determine_rate,2029	.set_parent = cdns_torrent_refclk_driver_set_parent,2030	.get_parent = cdns_torrent_refclk_driver_get_parent,2031};2032 2033static int cdns_torrent_refclk_driver_register(struct cdns_torrent_phy *cdns_phy)2034{2035	struct cdns_torrent_refclk_driver *refclk_driver;2036	struct device *dev = cdns_phy->dev;2037	struct regmap_field *field;2038	struct clk_init_data *init;2039	const char **parent_names;2040	unsigned int num_parents;2041	struct regmap *regmap;2042	char clk_name[100];2043	struct clk_hw *hw;2044	int i, ret;2045 2046	refclk_driver = devm_kzalloc(dev, sizeof(*refclk_driver), GFP_KERNEL);2047	if (!refclk_driver)2048		return -ENOMEM;2049 2050	num_parents = ARRAY_SIZE(refclk_driver_parent_index);2051	parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), GFP_KERNEL);2052	if (!parent_names)2053		return -ENOMEM;2054 2055	for (i = 0; i < num_parents; i++) {2056		hw = cdns_phy->clk_hw_data->hws[refclk_driver_parent_index[i]];2057		if (IS_ERR_OR_NULL(hw)) {2058			dev_err(dev, "No parent clock for refclk driver clock\n");2059			return IS_ERR(hw) ? PTR_ERR(hw) : -ENOENT;2060		}2061		parent_names[i] = clk_hw_get_name(hw);2062	}2063 2064	snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),2065		 clk_names[CDNS_TORRENT_REFCLK_DRIVER]);2066 2067	init = &refclk_driver->clk_data;2068 2069	init->ops = &cdns_torrent_refclk_driver_ops;2070	init->flags = CLK_SET_RATE_NO_REPARENT;2071	init->parent_names = parent_names;2072	init->num_parents = num_parents;2073	init->name = clk_name;2074 2075	regmap = cdns_phy->regmap_common_cdb;2076 2077	for (i = 0; i < REFCLK_OUT_NUM_CMN_CONFIG; i++) {2078		field = devm_regmap_field_alloc(dev, regmap, refclk_out_cmn_cfg[i]);2079		if (IS_ERR(field)) {2080			dev_err(dev, "Refclk driver CMN reg field init failed\n");2081			return PTR_ERR(field);2082		}2083		refclk_driver->cmn_fields[i] = field;2084	}2085 2086	/* Enable Derived reference clock as default */2087	regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], 1);2088 2089	refclk_driver->hw.init = init;2090 2091	hw = &refclk_driver->hw;2092	ret = devm_clk_hw_register(dev, hw);2093	if (ret)2094		return ret;2095 2096	cdns_phy->clk_hw_data->hws[CDNS_TORRENT_REFCLK_DRIVER] = hw;2097 2098	return 0;2099}2100 2101static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base,2102				       u32 block_offset,2103				       u8 reg_offset_shift,2104				       const struct regmap_config *config)2105{2106	struct cdns_regmap_cdb_context *ctx;2107 2108	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);2109	if (!ctx)2110		return ERR_PTR(-ENOMEM);2111 2112	ctx->dev = dev;2113	ctx->base = base + block_offset;2114	ctx->reg_offset_shift = reg_offset_shift;2115 2116	return devm_regmap_init(dev, NULL, ctx, config);2117}2118 2119static int cdns_torrent_dp_regfield_init(struct cdns_torrent_phy *cdns_phy)2120{2121	struct device *dev = cdns_phy->dev;2122	struct regmap_field *field;2123	struct regmap *regmap;2124 2125	regmap = cdns_phy->regmap_dptx_phy_reg;2126	field = devm_regmap_field_alloc(dev, regmap, phy_reset_ctrl);2127	if (IS_ERR(field)) {2128		dev_err(dev, "PHY_RESET reg field init failed\n");2129		return PTR_ERR(field);2130	}2131	cdns_phy->phy_reset_ctrl = field;2132 2133	return 0;2134}2135 2136static int cdns_torrent_regfield_init(struct cdns_torrent_phy *cdns_phy)2137{2138	struct device *dev = cdns_phy->dev;2139	struct regmap_field *field;2140	struct regmap *regmap;2141	int i;2142 2143	regmap = cdns_phy->regmap_phy_pcs_common_cdb;2144	field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg);2145	if (IS_ERR(field)) {2146		dev_err(dev, "PHY_PLL_CFG reg field init failed\n");2147		return PTR_ERR(field);2148	}2149	cdns_phy->phy_pll_cfg = field;2150 2151	regmap = cdns_phy->regmap_phy_pcs_common_cdb;2152	field = devm_regmap_field_alloc(dev, regmap, phy_pipe_cmn_ctrl1_0);2153	if (IS_ERR(field)) {2154		dev_err(dev, "phy_pipe_cmn_ctrl1_0 reg field init failed\n");2155		return PTR_ERR(field);2156	}2157	cdns_phy->phy_pipe_cmn_ctrl1_0 = field;2158 2159	regmap = cdns_phy->regmap_common_cdb;2160	field = devm_regmap_field_alloc(dev, regmap, cmn_cdiag_refclk_ovrd_4);2161	if (IS_ERR(field)) {2162		dev_err(dev, "cmn_cdiag_refclk_ovrd_4 reg field init failed\n");2163		return PTR_ERR(field);2164	}2165	cdns_phy->cmn_cdiag_refclk_ovrd_4 = field;2166 2167	regmap = cdns_phy->regmap_phy_pma_common_cdb;2168	field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_1);2169	if (IS_ERR(field)) {2170		dev_err(dev, "PHY_PMA_CMN_CTRL1 reg field init failed\n");2171		return PTR_ERR(field);2172	}2173	cdns_phy->phy_pma_cmn_ctrl_1 = field;2174 2175	regmap = cdns_phy->regmap_phy_pma_common_cdb;2176	field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_2);2177	if (IS_ERR(field)) {2178		dev_err(dev, "PHY_PMA_CMN_CTRL2 reg field init failed\n");2179		return PTR_ERR(field);2180	}2181	cdns_phy->phy_pma_cmn_ctrl_2 = field;2182 2183	regmap = cdns_phy->regmap_phy_pma_common_cdb;2184	field = devm_regmap_field_alloc(dev, regmap, phy_pma_pll_raw_ctrl);2185	if (IS_ERR(field)) {2186		dev_err(dev, "PHY_PMA_PLL_RAW_CTRL reg field init failed\n");2187		return PTR_ERR(field);2188	}2189	cdns_phy->phy_pma_pll_raw_ctrl = field;2190 2191	for (i = 0; i < MAX_NUM_LANES; i++) {2192		regmap = cdns_phy->regmap_phy_pcs_lane_cdb[i];2193		field = devm_regmap_field_alloc(dev, regmap, phy_pcs_iso_link_ctrl_1);2194		if (IS_ERR(field)) {2195			dev_err(dev, "PHY_PCS_ISO_LINK_CTRL reg field init for ln %d failed\n", i);2196			return PTR_ERR(field);2197		}2198		cdns_phy->phy_pcs_iso_link_ctrl_1[i] = field;2199	}2200 2201	return 0;2202}2203 2204static int cdns_torrent_dp_regmap_init(struct cdns_torrent_phy *cdns_phy)2205{2206	void __iomem *base = cdns_phy->base;2207	struct device *dev = cdns_phy->dev;2208	struct regmap *regmap;2209	u8 reg_offset_shift;2210	u32 block_offset;2211 2212	reg_offset_shift = cdns_phy->init_data->reg_offset_shift;2213 2214	block_offset = TORRENT_DPTX_PHY_OFFSET;2215	regmap = cdns_regmap_init(dev, base, block_offset,2216				  reg_offset_shift,2217				  &cdns_torrent_dptx_phy_config);2218	if (IS_ERR(regmap)) {2219		dev_err(dev, "Failed to init DPTX PHY regmap\n");2220		return PTR_ERR(regmap);2221	}2222	cdns_phy->regmap_dptx_phy_reg = regmap;2223 2224	return 0;2225}2226 2227static int cdns_torrent_regmap_init(struct cdns_torrent_phy *cdns_phy)2228{2229	void __iomem *sd_base = cdns_phy->sd_base;2230	u8 block_offset_shift, reg_offset_shift;2231	struct device *dev = cdns_phy->dev;2232	struct regmap *regmap;2233	u32 block_offset;2234	int i;2235 2236	block_offset_shift = cdns_phy->init_data->block_offset_shift;2237	reg_offset_shift = cdns_phy->init_data->reg_offset_shift;2238 2239	for (i = 0; i < MAX_NUM_LANES; i++) {2240		block_offset = TORRENT_TX_LANE_CDB_OFFSET(i, block_offset_shift,2241							  reg_offset_shift);2242		regmap = cdns_regmap_init(dev, sd_base, block_offset,2243					  reg_offset_shift,2244					  &cdns_torrent_tx_lane_cdb_config[i]);2245		if (IS_ERR(regmap)) {2246			dev_err(dev, "Failed to init tx lane CDB regmap\n");2247			return PTR_ERR(regmap);2248		}2249		cdns_phy->regmap_tx_lane_cdb[i] = regmap;2250 2251		block_offset = TORRENT_RX_LANE_CDB_OFFSET(i, block_offset_shift,2252							  reg_offset_shift);2253		regmap = cdns_regmap_init(dev, sd_base, block_offset,2254					  reg_offset_shift,2255					  &cdns_torrent_rx_lane_cdb_config[i]);2256		if (IS_ERR(regmap)) {2257			dev_err(dev, "Failed to init rx lane CDB regmap\n");2258			return PTR_ERR(regmap);2259		}2260		cdns_phy->regmap_rx_lane_cdb[i] = regmap;2261 2262		block_offset = TORRENT_PHY_PCS_LANE_CDB_OFFSET(i, block_offset_shift,2263							       reg_offset_shift);2264		regmap = cdns_regmap_init(dev, sd_base, block_offset,2265					  reg_offset_shift,2266					  &cdns_torrent_phy_pcs_lane_cdb_config[i]);2267		if (IS_ERR(regmap)) {2268			dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n");2269			return PTR_ERR(regmap);2270		}2271		cdns_phy->regmap_phy_pcs_lane_cdb[i] = regmap;2272	}2273 2274	block_offset = TORRENT_COMMON_CDB_OFFSET;2275	regmap = cdns_regmap_init(dev, sd_base, block_offset,2276				  reg_offset_shift,2277				  &cdns_torrent_common_cdb_config);2278	if (IS_ERR(regmap)) {2279		dev_err(dev, "Failed to init common CDB regmap\n");2280		return PTR_ERR(regmap);2281	}2282	cdns_phy->regmap_common_cdb = regmap;2283 2284	block_offset = TORRENT_PHY_PCS_COMMON_OFFSET(block_offset_shift);2285	regmap = cdns_regmap_init(dev, sd_base, block_offset,2286				  reg_offset_shift,2287				  &cdns_torrent_phy_pcs_cmn_cdb_config);2288	if (IS_ERR(regmap)) {2289		dev_err(dev, "Failed to init PHY PCS common CDB regmap\n");2290		return PTR_ERR(regmap);2291	}2292	cdns_phy->regmap_phy_pcs_common_cdb = regmap;2293 2294	block_offset = TORRENT_PHY_PMA_COMMON_OFFSET(block_offset_shift);2295	regmap = cdns_regmap_init(dev, sd_base, block_offset,2296				  reg_offset_shift,2297				  &cdns_torrent_phy_pma_cmn_cdb_config);2298	if (IS_ERR(regmap)) {2299		dev_err(dev, "Failed to init PHY PMA common CDB regmap\n");2300		return PTR_ERR(regmap);2301	}2302	cdns_phy->regmap_phy_pma_common_cdb = regmap;2303 2304	return 0;2305}2306 2307static int cdns_torrent_phy_init(struct phy *phy)2308{2309	struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent);2310	const struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;2311	const struct cdns_torrent_data *init_data = cdns_phy->init_data;2312	const struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;2313	enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate;2314	struct cdns_torrent_inst *inst = phy_get_drvdata(phy);2315	enum cdns_torrent_phy_type phy_type = inst->phy_type;2316	const struct cdns_torrent_vals *phy_pma_cmn_vals;2317	enum cdns_torrent_ssc_mode ssc = inst->ssc_mode;2318	const struct cdns_torrent_vals *pcs_cmn_vals;2319	const struct cdns_reg_pairs *reg_pairs;2320	struct regmap *regmap;2321	u32 num_regs;2322	int i, j;2323 2324	if (cdns_phy->already_configured)2325		return 0;2326 2327	if (cdns_phy->nsubnodes > 1) {2328		if (phy_type == TYPE_DP)2329			return cdns_torrent_dp_multilink_init(cdns_phy, inst, phy);2330		return 0;2331	}2332 2333	/**2334	 * Spread spectrum generation is not required or supported2335	 * for SGMII/QSGMII/USXGMII2336	 */2337	if (phy_type == TYPE_SGMII || phy_type == TYPE_QSGMII || phy_type == TYPE_USXGMII)2338		ssc = NO_SSC;2339 2340	/* PHY configuration specific registers for single link */2341	link_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->link_cmn_vals_tbl,2342						  CLK_ANY, CLK_ANY,2343						  phy_type, TYPE_NONE,2344						  ANY_SSC);2345	if (link_cmn_vals) {2346		reg_pairs = link_cmn_vals->reg_pairs;2347		num_regs = link_cmn_vals->num_regs;2348		regmap = cdns_phy->regmap_common_cdb;2349 2350		/**2351		 * First array value in link_cmn_vals must be of2352		 * PHY_PLL_CFG register2353		 */2354		regmap_field_write(cdns_phy->phy_pll_cfg, reg_pairs[0].val);2355 2356		for (i = 1; i < num_regs; i++)2357			regmap_write(regmap, reg_pairs[i].off,2358				     reg_pairs[i].val);2359	}2360 2361	xcvr_diag_vals = cdns_torrent_get_tbl_vals(&init_data->xcvr_diag_vals_tbl,2362						   CLK_ANY, CLK_ANY,2363						   phy_type, TYPE_NONE,2364						   ANY_SSC);2365	if (xcvr_diag_vals) {2366		reg_pairs = xcvr_diag_vals->reg_pairs;2367		num_regs = xcvr_diag_vals->num_regs;2368		for (i = 0; i < inst->num_lanes; i++) {2369			regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];2370			for (j = 0; j < num_regs; j++)2371				regmap_write(regmap, reg_pairs[j].off,2372					     reg_pairs[j].val);2373		}2374	}2375 2376	/* PHY PCS common registers configurations */2377	pcs_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->pcs_cmn_vals_tbl,2378						 CLK_ANY, CLK_ANY,2379						 phy_type, TYPE_NONE,2380						 ANY_SSC);2381	if (pcs_cmn_vals) {2382		reg_pairs = pcs_cmn_vals->reg_pairs;2383		num_regs = pcs_cmn_vals->num_regs;2384		regmap = cdns_phy->regmap_phy_pcs_common_cdb;2385		for (i = 0; i < num_regs; i++)2386			regmap_write(regmap, reg_pairs[i].off,2387				     reg_pairs[i].val);2388	}2389 2390	/* PHY PMA common registers configurations */2391	phy_pma_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->phy_pma_cmn_vals_tbl,2392						     CLK_ANY, CLK_ANY,2393						     phy_type, TYPE_NONE,2394						     ANY_SSC);2395	if (phy_pma_cmn_vals) {2396		reg_pairs = phy_pma_cmn_vals->reg_pairs;2397		num_regs = phy_pma_cmn_vals->num_regs;2398		regmap = cdns_phy->regmap_phy_pma_common_cdb;2399		for (i = 0; i < num_regs; i++)2400			regmap_write(regmap, reg_pairs[i].off,2401				     reg_pairs[i].val);2402	}2403 2404	/* PMA common registers configurations */2405	cmn_vals = cdns_torrent_get_tbl_vals(&init_data->cmn_vals_tbl,2406					     ref_clk, ref_clk,2407					     phy_type, TYPE_NONE,2408					     ssc);2409	if (cmn_vals) {2410		reg_pairs = cmn_vals->reg_pairs;2411		num_regs = cmn_vals->num_regs;2412		regmap = cdns_phy->regmap_common_cdb;2413		for (i = 0; i < num_regs; i++)2414			regmap_write(regmap, reg_pairs[i].off,2415				     reg_pairs[i].val);2416	}2417 2418	/* PMA TX lane registers configurations */2419	tx_ln_vals = cdns_torrent_get_tbl_vals(&init_data->tx_ln_vals_tbl,2420					       ref_clk, ref_clk,2421					       phy_type, TYPE_NONE,2422					       ssc);2423	if (tx_ln_vals) {2424		reg_pairs = tx_ln_vals->reg_pairs;2425		num_regs = tx_ln_vals->num_regs;2426		for (i = 0; i < inst->num_lanes; i++) {2427			regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane];2428			for (j = 0; j < num_regs; j++)2429				regmap_write(regmap, reg_pairs[j].off,2430					     reg_pairs[j].val);2431		}2432	}2433 2434	/* PMA RX lane registers configurations */2435	rx_ln_vals = cdns_torrent_get_tbl_vals(&init_data->rx_ln_vals_tbl,2436					       ref_clk, ref_clk,2437					       phy_type, TYPE_NONE,2438					       ssc);2439	if (rx_ln_vals) {2440		reg_pairs = rx_ln_vals->reg_pairs;2441		num_regs = rx_ln_vals->num_regs;2442		for (i = 0; i < inst->num_lanes; i++) {2443			regmap = cdns_phy->regmap_rx_lane_cdb[i + inst->mlane];2444			for (j = 0; j < num_regs; j++)2445				regmap_write(regmap, reg_pairs[j].off,2446					     reg_pairs[j].val);2447		}2448	}2449 2450	if (phy_type == TYPE_DP)2451		return cdns_torrent_dp_init(phy);2452 2453	return 0;2454}2455 2456static const struct phy_ops cdns_torrent_phy_ops = {2457	.init		= cdns_torrent_phy_init,2458	.configure	= cdns_torrent_dp_configure,2459	.power_on	= cdns_torrent_phy_on,2460	.power_off	= cdns_torrent_phy_off,2461	.owner		= THIS_MODULE,2462};2463 2464static2465int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy)2466{2467	const struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals;2468	const struct cdns_torrent_data *init_data = cdns_phy->init_data;2469	const struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals;2470	enum cdns_torrent_ref_clk ref_clk1 = cdns_phy->ref_clk1_rate;2471	enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate;2472	const struct cdns_torrent_vals *phy_pma_cmn_vals;2473	const struct cdns_torrent_vals *pcs_cmn_vals;2474	enum cdns_torrent_phy_type phy_t1, phy_t2;2475	const struct cdns_reg_pairs *reg_pairs;2476	int i, j, node, mlane, num_lanes, ret;2477	struct device *dev = cdns_phy->dev;2478	enum cdns_torrent_ssc_mode ssc;2479	struct regmap *regmap;2480	u32 num_regs, num_protocols, protocol;2481 2482	num_protocols = hweight32(cdns_phy->protocol_bitmask);2483	/* Maximum 2 protocols are supported */2484	if (num_protocols > 2) {2485		dev_err(dev, "at most 2 protocols are supported\n");2486		return -EINVAL;2487	}2488 2489 2490	/**2491	 * Get PHY types directly from subnodes if only 2 subnodes exist.2492	 * It is possible for phy_t1 to be the same as phy_t2 for special2493	 * configurations such as PCIe Multilink.2494	 */2495	if (cdns_phy->nsubnodes == 2) {2496		phy_t1 = cdns_phy->phys[0].phy_type;2497		phy_t2 = cdns_phy->phys[1].phy_type;2498	} else {2499		/**2500		 * Both PHY types / protocols should be unique.2501		 * If they are the same, it should be expressed with either2502		 * a) Single-Link (1 Sub-node) - handled via PHY APIs2503		 * OR2504		 * b) Double-Link (2 Sub-nodes) - handled above2505		 */2506		if (num_protocols != 2) {2507			dev_err(dev, "incorrect representation of link\n");2508			return -EINVAL;2509		}2510 2511		phy_t1 = fns(cdns_phy->protocol_bitmask, 0);2512		phy_t2 = fns(cdns_phy->protocol_bitmask, 1);2513	}2514 2515	/**2516	 * Configure all links with the protocol phy_t1 first followed by2517	 * configuring all links with the protocol phy_t2.2518	 *2519	 * When phy_t1 = phy_t2, it is a single protocol and configuration2520	 * is performed with a single iteration of the protocol and multiple2521	 * iterations over the sub-nodes (links).2522	 *2523	 * When phy_t1 != phy_t2, there are two protocols and configuration2524	 * is performed by iterating over all sub-nodes matching the first2525	 * protocol and configuring them first, followed by iterating over2526	 * all sub-nodes matching the second protocol and configuring them2527	 * next.2528	 */2529	for (protocol = 0; protocol < num_protocols; protocol++) {2530		/**2531		 * For the case where num_protocols is 1,2532		 * phy_t1 = phy_t2 and the swap is unnecessary.2533		 *2534		 * Swapping phy_t1 and phy_t2 is only required when the2535		 * number of protocols is 2 and there are 2 or more links.2536		 */2537		if (protocol == 1) {2538			/**2539			 * If first protocol with phy_t1 is configured, then2540			 * configure the PHY for second protocol with phy_t2.2541			 * Get the array values as [phy_t2][phy_t1][ssc].2542			 */2543			swap(phy_t1, phy_t2);2544			swap(ref_clk, ref_clk1);2545		}2546 2547		for (node = 0; node < cdns_phy->nsubnodes; node++) {2548			if (cdns_phy->phys[node].phy_type != phy_t1)2549				continue;2550 2551			mlane = cdns_phy->phys[node].mlane;2552			ssc = cdns_phy->phys[node].ssc_mode;2553			num_lanes = cdns_phy->phys[node].num_lanes;2554 2555			/**2556			 * PHY configuration specific registers:2557			 * link_cmn_vals depend on combination of PHY types being2558			 * configured and are common for both PHY types, so array2559			 * values should be same for [phy_t1][phy_t2][ssc] and2560			 * [phy_t2][phy_t1][ssc].2561			 * xcvr_diag_vals also depend on combination of PHY types2562			 * being configured, but these can be different for particular2563			 * PHY type and are per lane.2564			 */2565			link_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->link_cmn_vals_tbl,2566								  CLK_ANY, CLK_ANY,2567								  phy_t1, phy_t2, ANY_SSC);2568			if (link_cmn_vals) {2569				reg_pairs = link_cmn_vals->reg_pairs;2570				num_regs = link_cmn_vals->num_regs;2571				regmap = cdns_phy->regmap_common_cdb;2572 2573				/**2574				 * First array value in link_cmn_vals must be of2575				 * PHY_PLL_CFG register2576				 */2577				regmap_field_write(cdns_phy->phy_pll_cfg,2578						   reg_pairs[0].val);2579 2580				for (i = 1; i < num_regs; i++)2581					regmap_write(regmap, reg_pairs[i].off,2582						     reg_pairs[i].val);2583			}2584 2585			xcvr_diag_vals = cdns_torrent_get_tbl_vals(&init_data->xcvr_diag_vals_tbl,2586								   CLK_ANY, CLK_ANY,2587								   phy_t1, phy_t2, ANY_SSC);2588			if (xcvr_diag_vals) {2589				reg_pairs = xcvr_diag_vals->reg_pairs;2590				num_regs = xcvr_diag_vals->num_regs;2591				for (i = 0; i < num_lanes; i++) {2592					regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];2593					for (j = 0; j < num_regs; j++)2594						regmap_write(regmap, reg_pairs[j].off,2595							     reg_pairs[j].val);2596				}2597			}2598 2599			/* PHY PCS common registers configurations */2600			pcs_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->pcs_cmn_vals_tbl,2601								 CLK_ANY, CLK_ANY,2602								 phy_t1, phy_t2, ANY_SSC);2603			if (pcs_cmn_vals) {2604				reg_pairs = pcs_cmn_vals->reg_pairs;2605				num_regs = pcs_cmn_vals->num_regs;2606				regmap = cdns_phy->regmap_phy_pcs_common_cdb;2607				for (i = 0; i < num_regs; i++)2608					regmap_write(regmap, reg_pairs[i].off,2609						     reg_pairs[i].val);2610			}2611 2612			/* PHY PMA common registers configurations */2613			phy_pma_cmn_vals =2614				cdns_torrent_get_tbl_vals(&init_data->phy_pma_cmn_vals_tbl,2615							  CLK_ANY, CLK_ANY, phy_t1, phy_t2,2616							  ANY_SSC);2617			if (phy_pma_cmn_vals) {2618				reg_pairs = phy_pma_cmn_vals->reg_pairs;2619				num_regs = phy_pma_cmn_vals->num_regs;2620				regmap = cdns_phy->regmap_phy_pma_common_cdb;2621				for (i = 0; i < num_regs; i++)2622					regmap_write(regmap, reg_pairs[i].off,2623						     reg_pairs[i].val);2624			}2625 2626			/* PMA common registers configurations */2627			cmn_vals = cdns_torrent_get_tbl_vals(&init_data->cmn_vals_tbl,2628							     ref_clk, ref_clk1,2629							     phy_t1, phy_t2, ssc);2630			if (cmn_vals) {2631				reg_pairs = cmn_vals->reg_pairs;2632				num_regs = cmn_vals->num_regs;2633				regmap = cdns_phy->regmap_common_cdb;2634				for (i = 0; i < num_regs; i++)2635					regmap_write(regmap, reg_pairs[i].off,2636						     reg_pairs[i].val);2637			}2638 2639			/* PMA TX lane registers configurations */2640			tx_ln_vals = cdns_torrent_get_tbl_vals(&init_data->tx_ln_vals_tbl,2641							       ref_clk, ref_clk1,2642							       phy_t1, phy_t2, ssc);2643			if (tx_ln_vals) {2644				reg_pairs = tx_ln_vals->reg_pairs;2645				num_regs = tx_ln_vals->num_regs;2646				for (i = 0; i < num_lanes; i++) {2647					regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane];2648					for (j = 0; j < num_regs; j++)2649						regmap_write(regmap, reg_pairs[j].off,2650							     reg_pairs[j].val);2651				}2652			}2653 2654			/* PMA RX lane registers configurations */2655			rx_ln_vals = cdns_torrent_get_tbl_vals(&init_data->rx_ln_vals_tbl,2656							       ref_clk, ref_clk1,2657							       phy_t1, phy_t2, ssc);2658			if (rx_ln_vals) {2659				reg_pairs = rx_ln_vals->reg_pairs;2660				num_regs = rx_ln_vals->num_regs;2661				for (i = 0; i < num_lanes; i++) {2662					regmap = cdns_phy->regmap_rx_lane_cdb[i + mlane];2663					for (j = 0; j < num_regs; j++)2664						regmap_write(regmap, reg_pairs[j].off,2665							     reg_pairs[j].val);2666				}2667			}2668 2669			if (phy_t1 == TYPE_DP) {2670				ret = cdns_torrent_dp_get_pll(cdns_phy, phy_t2);2671				if (ret)2672					return ret;2673			}2674 2675			reset_control_deassert(cdns_phy->phys[node].lnk_rst);2676		}2677	}2678 2679	/* Take the PHY out of reset */2680	ret = reset_control_deassert(cdns_phy->phy_rst);2681	if (ret)2682		return ret;2683 2684	return 0;2685}2686 2687static void cdns_torrent_clk_cleanup(struct cdns_torrent_phy *cdns_phy)2688{2689	struct device *dev = cdns_phy->dev;2690 2691	of_clk_del_provider(dev->of_node);2692}2693 2694static int cdns_torrent_clk_register(struct cdns_torrent_phy *cdns_phy)2695{2696	struct device *dev = cdns_phy->dev;2697	struct device_node *node = dev->of_node;2698	struct clk_hw_onecell_data *data;2699	int ret;2700 2701	data = devm_kzalloc(dev, struct_size(data, hws, CDNS_TORRENT_OUTPUT_CLOCKS), GFP_KERNEL);2702	if (!data)2703		return -ENOMEM;2704 2705	data->num = CDNS_TORRENT_OUTPUT_CLOCKS;2706	cdns_phy->clk_hw_data = data;2707 2708	ret = cdns_torrent_derived_refclk_register(cdns_phy);2709	if (ret) {2710		dev_err(dev, "failed to register derived refclk\n");2711		return ret;2712	}2713 2714	ret = cdns_torrent_received_refclk_register(cdns_phy);2715	if (ret) {2716		dev_err(dev, "failed to register received refclk\n");2717		return ret;2718	}2719 2720	ret = cdns_torrent_refclk_driver_register(cdns_phy);2721	if (ret) {2722		dev_err(dev, "failed to register refclk driver\n");2723		return ret;2724	}2725 2726	ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, data);2727	if (ret) {2728		dev_err(dev, "Failed to add clock provider: %s\n", node->name);2729		return ret;2730	}2731 2732	return 0;2733}2734 2735static int cdns_torrent_of_get_reset(struct cdns_torrent_phy *cdns_phy)2736{2737	struct device *dev = cdns_phy->dev;2738 2739	cdns_phy->phy_rst = devm_reset_control_get_exclusive_by_index(dev, 0);2740	if (IS_ERR(cdns_phy->phy_rst)) {2741		dev_err(dev, "%s: failed to get reset\n",2742			dev->of_node->full_name);2743		return PTR_ERR(cdns_phy->phy_rst);2744	}2745 2746	cdns_phy->apb_rst = devm_reset_control_get_optional_exclusive(dev, "torrent_apb");2747	if (IS_ERR(cdns_phy->apb_rst)) {2748		dev_err(dev, "%s: failed to get apb reset\n",2749			dev->of_node->full_name);2750		return PTR_ERR(cdns_phy->apb_rst);2751	}2752 2753	return 0;2754}2755 2756static int cdns_torrent_of_get_clk(struct cdns_torrent_phy *cdns_phy)2757{2758	/* refclk: Input reference clock for PLL0 */2759	cdns_phy->clk = devm_clk_get(cdns_phy->dev, "refclk");2760	if (IS_ERR(cdns_phy->clk))2761		return dev_err_probe(cdns_phy->dev, PTR_ERR(cdns_phy->clk),2762				     "phy ref clock not found\n");2763 2764	/* refclk1: Input reference clock for PLL1 */2765	cdns_phy->clk1 = devm_clk_get_optional(cdns_phy->dev, "pll1_refclk");2766	if (IS_ERR(cdns_phy->clk1))2767		return dev_err_probe(cdns_phy->dev, PTR_ERR(cdns_phy->clk1),2768				     "phy PLL1 ref clock not found\n");2769 2770	return 0;2771}2772 2773static int cdns_torrent_clk(struct cdns_torrent_phy *cdns_phy)2774{2775	unsigned long ref_clk1_rate;2776	unsigned long ref_clk_rate;2777	int ret;2778 2779	ret = clk_prepare_enable(cdns_phy->clk);2780	if (ret) {2781		dev_err(cdns_phy->dev, "Failed to prepare ref clock: %d\n", ret);2782		return ret;2783	}2784 2785	ref_clk_rate = clk_get_rate(cdns_phy->clk);2786	if (!ref_clk_rate) {2787		dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");2788		ret = -EINVAL;2789		goto disable_clk;2790	}2791 2792	switch (ref_clk_rate) {2793	case REF_CLK_19_2MHZ:2794		cdns_phy->ref_clk_rate = CLK_19_2_MHZ;2795		break;2796	case REF_CLK_25MHZ:2797		cdns_phy->ref_clk_rate = CLK_25_MHZ;2798		break;2799	case REF_CLK_100MHZ:2800		cdns_phy->ref_clk_rate = CLK_100_MHZ;2801		break;2802	case REF_CLK_156_25MHZ:2803		cdns_phy->ref_clk_rate = CLK_156_25_MHZ;2804		break;2805	default:2806		dev_err(cdns_phy->dev, "Invalid ref clock rate\n");2807		ret = -EINVAL;2808		goto disable_clk;2809	}2810 2811	if (cdns_phy->clk1) {2812		ret = clk_prepare_enable(cdns_phy->clk1);2813		if (ret) {2814			dev_err(cdns_phy->dev, "Failed to prepare PLL1 ref clock: %d\n", ret);2815			goto disable_clk;2816		}2817 2818		ref_clk1_rate = clk_get_rate(cdns_phy->clk1);2819		if (!ref_clk1_rate) {2820			dev_err(cdns_phy->dev, "Failed to get PLL1 ref clock rate\n");2821			ret = -EINVAL;2822			goto disable_clk1;2823		}2824 2825		switch (ref_clk1_rate) {2826		case REF_CLK_19_2MHZ:2827			cdns_phy->ref_clk1_rate = CLK_19_2_MHZ;2828			break;2829		case REF_CLK_25MHZ:2830			cdns_phy->ref_clk1_rate = CLK_25_MHZ;2831			break;2832		case REF_CLK_100MHZ:2833			cdns_phy->ref_clk1_rate = CLK_100_MHZ;2834			break;2835		case REF_CLK_156_25MHZ:2836			cdns_phy->ref_clk1_rate = CLK_156_25_MHZ;2837			break;2838		default:2839			dev_err(cdns_phy->dev, "Invalid PLL1 ref clock rate\n");2840			ret = -EINVAL;2841			goto disable_clk1;2842		}2843	} else {2844		cdns_phy->ref_clk1_rate = cdns_phy->ref_clk_rate;2845	}2846 2847	return 0;2848 2849disable_clk1:2850	clk_disable_unprepare(cdns_phy->clk1);2851disable_clk:2852	clk_disable_unprepare(cdns_phy->clk);2853	return ret;2854}2855 2856static int cdns_torrent_phy_probe(struct platform_device *pdev)2857{2858	struct cdns_torrent_phy *cdns_phy;2859	struct device *dev = &pdev->dev;2860	struct phy_provider *phy_provider;2861	const struct cdns_torrent_data *data;2862	struct device_node *child;2863	int ret, subnodes, node = 0, i;2864	u32 total_num_lanes = 0;2865	u8 init_dp_regmap = 0;2866	u32 phy_type;2867 2868	/* Get init data for this PHY */2869	data = of_device_get_match_data(dev);2870	if (!data)2871		return -EINVAL;2872 2873	cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL);2874	if (!cdns_phy)2875		return -ENOMEM;2876 2877	dev_set_drvdata(dev, cdns_phy);2878	cdns_phy->dev = dev;2879	cdns_phy->init_data = data;2880	cdns_phy->protocol_bitmask = 0;2881 2882	cdns_phy->sd_base = devm_platform_ioremap_resource(pdev, 0);2883	if (IS_ERR(cdns_phy->sd_base))2884		return PTR_ERR(cdns_phy->sd_base);2885 2886	subnodes = of_get_available_child_count(dev->of_node);2887	if (subnodes == 0) {2888		dev_err(dev, "No available link subnodes found\n");2889		return -EINVAL;2890	}2891 2892	ret = cdns_torrent_regmap_init(cdns_phy);2893	if (ret)2894		return ret;2895 2896	ret = cdns_torrent_regfield_init(cdns_phy);2897	if (ret)2898		return ret;2899 2900	ret = cdns_torrent_clk_register(cdns_phy);2901	if (ret)2902		return ret;2903 2904	ret = cdns_torrent_of_get_reset(cdns_phy);2905	if (ret)2906		goto clk_cleanup;2907 2908	ret = cdns_torrent_of_get_clk(cdns_phy);2909	if (ret)2910		goto clk_cleanup;2911 2912	regmap_field_read(cdns_phy->phy_pma_cmn_ctrl_1, &cdns_phy->already_configured);2913 2914	if (!cdns_phy->already_configured) {2915		ret = cdns_torrent_clk(cdns_phy);2916		if (ret)2917			goto clk_cleanup;2918 2919		/* Enable APB */2920		reset_control_deassert(cdns_phy->apb_rst);2921	}2922 2923	for_each_available_child_of_node(dev->of_node, child) {2924		struct phy *gphy;2925 2926		/* PHY subnode name must be 'phy'. */2927		if (!(of_node_name_eq(child, "phy")))2928			continue;2929 2930		cdns_phy->phys[node].lnk_rst =2931				of_reset_control_array_get_exclusive(child);2932		if (IS_ERR(cdns_phy->phys[node].lnk_rst)) {2933			dev_err(dev, "%s: failed to get reset\n",2934				child->full_name);2935			ret = PTR_ERR(cdns_phy->phys[node].lnk_rst);2936			goto put_lnk_rst;2937		}2938 2939		if (of_property_read_u32(child, "reg",2940					 &cdns_phy->phys[node].mlane)) {2941			dev_err(dev, "%s: No \"reg\"-property.\n",2942				child->full_name);2943			ret = -EINVAL;2944			goto put_child;2945		}2946 2947		if (of_property_read_u32(child, "cdns,phy-type", &phy_type)) {2948			dev_err(dev, "%s: No \"cdns,phy-type\"-property.\n",2949				child->full_name);2950			ret = -EINVAL;2951			goto put_child;2952		}2953 2954		switch (phy_type) {2955		case PHY_TYPE_PCIE:2956			cdns_phy->phys[node].phy_type = TYPE_PCIE;2957			break;2958		case PHY_TYPE_DP:2959			cdns_phy->phys[node].phy_type = TYPE_DP;2960			break;2961		case PHY_TYPE_SGMII:2962			cdns_phy->phys[node].phy_type = TYPE_SGMII;2963			break;2964		case PHY_TYPE_QSGMII:2965			cdns_phy->phys[node].phy_type = TYPE_QSGMII;2966			break;2967		case PHY_TYPE_USB3:2968			cdns_phy->phys[node].phy_type = TYPE_USB;2969			break;2970		case PHY_TYPE_USXGMII:2971			cdns_phy->phys[node].phy_type = TYPE_USXGMII;2972			break;2973		default:2974			dev_err(dev, "Unsupported protocol\n");2975			ret = -EINVAL;2976			goto put_child;2977		}2978 2979		if (of_property_read_u32(child, "cdns,num-lanes",2980					 &cdns_phy->phys[node].num_lanes)) {2981			dev_err(dev, "%s: No \"cdns,num-lanes\"-property.\n",2982				child->full_name);2983			ret = -EINVAL;2984			goto put_child;2985		}2986 2987		total_num_lanes += cdns_phy->phys[node].num_lanes;2988 2989		/* Get SSC mode */2990		cdns_phy->phys[node].ssc_mode = NO_SSC;2991		of_property_read_u32(child, "cdns,ssc-mode",2992				     &cdns_phy->phys[node].ssc_mode);2993 2994		gphy = devm_phy_create(dev, child, &cdns_torrent_phy_ops);2995		if (IS_ERR(gphy)) {2996			ret = PTR_ERR(gphy);2997			goto put_child;2998		}2999 3000		if (cdns_phy->phys[node].phy_type == TYPE_DP) {3001			switch (cdns_phy->phys[node].num_lanes) {3002			case 1:3003			case 2:3004			case 4:3005			/* valid number of lanes */3006				break;3007			default:3008				dev_err(dev, "unsupported number of lanes: %d\n",3009					cdns_phy->phys[node].num_lanes);3010				ret = -EINVAL;3011				goto put_child;3012			}3013 3014			cdns_phy->max_bit_rate = DEFAULT_MAX_BIT_RATE;3015			of_property_read_u32(child, "cdns,max-bit-rate",3016					     &cdns_phy->max_bit_rate);3017 3018			switch (cdns_phy->max_bit_rate) {3019			case 1620:3020			case 2160:3021			case 2430:3022			case 2700:3023			case 3240:3024			case 4320:3025			case 5400:3026			case 8100:3027			/* valid bit rate */3028				break;3029			default:3030				dev_err(dev, "unsupported max bit rate: %dMbps\n",3031					cdns_phy->max_bit_rate);3032				ret = -EINVAL;3033				goto put_child;3034			}3035 3036			/* DPTX registers */3037			cdns_phy->base = devm_platform_ioremap_resource(pdev, 1);3038			if (IS_ERR(cdns_phy->base)) {3039				ret = PTR_ERR(cdns_phy->base);3040				goto put_child;3041			}3042 3043			if (!init_dp_regmap) {3044				ret = cdns_torrent_dp_regmap_init(cdns_phy);3045				if (ret)3046					goto put_child;3047 3048				ret = cdns_torrent_dp_regfield_init(cdns_phy);3049				if (ret)3050					goto put_child;3051 3052				init_dp_regmap++;3053			}3054 3055			dev_dbg(dev, "DP max bit rate %d.%03d Gbps\n",3056				cdns_phy->max_bit_rate / 1000,3057				cdns_phy->max_bit_rate % 1000);3058 3059			gphy->attrs.bus_width = cdns_phy->phys[node].num_lanes;3060			gphy->attrs.max_link_rate = cdns_phy->max_bit_rate;3061			gphy->attrs.mode = PHY_MODE_DP;3062		}3063 3064		cdns_phy->phys[node].phy = gphy;3065		cdns_phy->protocol_bitmask |= BIT(cdns_phy->phys[node].phy_type);3066		phy_set_drvdata(gphy, &cdns_phy->phys[node]);3067 3068		node++;3069	}3070	cdns_phy->nsubnodes = node;3071 3072	if (total_num_lanes > MAX_NUM_LANES) {3073		dev_err(dev, "Invalid lane configuration\n");3074		ret = -EINVAL;3075		goto put_lnk_rst;3076	}3077 3078	if (cdns_phy->nsubnodes > 1 && !cdns_phy->already_configured) {3079		ret = cdns_torrent_phy_configure_multilink(cdns_phy);3080		if (ret)3081			goto put_lnk_rst;3082	}3083 3084	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);3085	if (IS_ERR(phy_provider)) {3086		ret = PTR_ERR(phy_provider);3087		goto put_lnk_rst;3088	}3089 3090	if (cdns_phy->nsubnodes > 1)3091		dev_dbg(dev, "Multi-link: %s (%d lanes) & %s (%d lanes)",3092			cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type),3093			cdns_phy->phys[0].num_lanes,3094			cdns_torrent_get_phy_type(cdns_phy->phys[1].phy_type),3095			cdns_phy->phys[1].num_lanes);3096	else3097		dev_dbg(dev, "Single link: %s (%d lanes)",3098			cdns_torrent_get_phy_type(cdns_phy->phys[0].phy_type),3099			cdns_phy->phys[0].num_lanes);3100 3101	return 0;3102 3103put_child:3104	node++;3105put_lnk_rst:3106	for (i = 0; i < node; i++)3107		reset_control_put(cdns_phy->phys[i].lnk_rst);3108	of_node_put(child);3109	reset_control_assert(cdns_phy->apb_rst);3110	clk_disable_unprepare(cdns_phy->clk1);3111	clk_disable_unprepare(cdns_phy->clk);3112clk_cleanup:3113	cdns_torrent_clk_cleanup(cdns_phy);3114	return ret;3115}3116 3117static void cdns_torrent_phy_remove(struct platform_device *pdev)3118{3119	struct cdns_torrent_phy *cdns_phy = platform_get_drvdata(pdev);3120	int i;3121 3122	reset_control_assert(cdns_phy->phy_rst);3123	reset_control_assert(cdns_phy->apb_rst);3124	for (i = 0; i < cdns_phy->nsubnodes; i++) {3125		reset_control_assert(cdns_phy->phys[i].lnk_rst);3126		reset_control_put(cdns_phy->phys[i].lnk_rst);3127	}3128 3129	clk_disable_unprepare(cdns_phy->clk1);3130	clk_disable_unprepare(cdns_phy->clk);3131	cdns_torrent_clk_cleanup(cdns_phy);3132}3133 3134/* SGMII and QSGMII link configuration */3135static const struct cdns_reg_pairs sgmii_qsgmii_link_cmn_regs[] = {3136	{0x0002, PHY_PLL_CFG}3137};3138 3139static const struct cdns_reg_pairs sgmii_qsgmii_xcvr_diag_ln_regs[] = {3140	{0x0003, XCVR_DIAG_HSCLK_DIV},3141	{0x0113, XCVR_DIAG_PLLDRC_CTRL}3142};3143 3144static const struct cdns_torrent_vals sgmii_qsgmii_link_cmn_vals = {3145	.reg_pairs = sgmii_qsgmii_link_cmn_regs,3146	.num_regs = ARRAY_SIZE(sgmii_qsgmii_link_cmn_regs),3147};3148 3149static const struct cdns_torrent_vals sgmii_qsgmii_xcvr_diag_ln_vals = {3150	.reg_pairs = sgmii_qsgmii_xcvr_diag_ln_regs,3151	.num_regs = ARRAY_SIZE(sgmii_qsgmii_xcvr_diag_ln_regs),3152};3153 3154static int cdns_torrent_phy_suspend_noirq(struct device *dev)3155{3156	struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(dev);3157	int i;3158 3159	reset_control_assert(cdns_phy->phy_rst);3160	reset_control_assert(cdns_phy->apb_rst);3161	for (i = 0; i < cdns_phy->nsubnodes; i++)3162		reset_control_assert(cdns_phy->phys[i].lnk_rst);3163 3164	if (cdns_phy->already_configured)3165		cdns_phy->already_configured = 0;3166	else {3167		clk_disable_unprepare(cdns_phy->clk1);3168		clk_disable_unprepare(cdns_phy->clk);3169	}3170 3171	return 0;3172}3173 3174static int cdns_torrent_phy_resume_noirq(struct device *dev)3175{3176	struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(dev);3177	int node = cdns_phy->nsubnodes;3178	int ret, i;3179 3180	ret = cdns_torrent_clk(cdns_phy);3181	if (ret)3182		return ret;3183 3184	/* Enable APB */3185	reset_control_deassert(cdns_phy->apb_rst);3186 3187	if (cdns_phy->nsubnodes > 1) {3188		ret = cdns_torrent_phy_configure_multilink(cdns_phy);3189		if (ret)3190			goto put_lnk_rst;3191	}3192 3193	return 0;3194 3195put_lnk_rst:3196	for (i = 0; i < node; i++)3197		reset_control_assert(cdns_phy->phys[i].lnk_rst);3198	reset_control_assert(cdns_phy->apb_rst);3199 3200	clk_disable_unprepare(cdns_phy->clk1);3201	clk_disable_unprepare(cdns_phy->clk);3202 3203	return ret;3204}3205 3206static DEFINE_NOIRQ_DEV_PM_OPS(cdns_torrent_phy_pm_ops,3207			       cdns_torrent_phy_suspend_noirq,3208			       cdns_torrent_phy_resume_noirq);3209 3210/* USB and DP link configuration */3211static const struct cdns_reg_pairs usb_dp_link_cmn_regs[] = {3212	{0x0002, PHY_PLL_CFG},3213	{0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}3214};3215 3216static const struct cdns_reg_pairs usb_dp_xcvr_diag_ln_regs[] = {3217	{0x0000, XCVR_DIAG_HSCLK_SEL},3218	{0x0001, XCVR_DIAG_HSCLK_DIV},3219	{0x0041, XCVR_DIAG_PLLDRC_CTRL}3220};3221 3222static const struct cdns_reg_pairs dp_usb_xcvr_diag_ln_regs[] = {3223	{0x0001, XCVR_DIAG_HSCLK_SEL},3224	{0x0009, XCVR_DIAG_PLLDRC_CTRL}3225};3226 3227static const struct cdns_torrent_vals usb_dp_link_cmn_vals = {3228	.reg_pairs = usb_dp_link_cmn_regs,3229	.num_regs = ARRAY_SIZE(usb_dp_link_cmn_regs),3230};3231 3232static const struct cdns_torrent_vals usb_dp_xcvr_diag_ln_vals = {3233	.reg_pairs = usb_dp_xcvr_diag_ln_regs,3234	.num_regs = ARRAY_SIZE(usb_dp_xcvr_diag_ln_regs),3235};3236 3237static const struct cdns_torrent_vals dp_usb_xcvr_diag_ln_vals = {3238	.reg_pairs = dp_usb_xcvr_diag_ln_regs,3239	.num_regs = ARRAY_SIZE(dp_usb_xcvr_diag_ln_regs),3240};3241 3242/* USXGMII and SGMII/QSGMII link configuration */3243static const struct cdns_reg_pairs usxgmii_sgmii_link_cmn_regs[] = {3244	{0x0002, PHY_PLL_CFG},3245	{0x0400, CMN_PDIAG_PLL0_CLK_SEL_M0},3246	{0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}3247};3248 3249static const struct cdns_reg_pairs usxgmii_sgmii_xcvr_diag_ln_regs[] = {3250	{0x0000, XCVR_DIAG_HSCLK_SEL},3251	{0x0001, XCVR_DIAG_HSCLK_DIV},3252	{0x0001, XCVR_DIAG_PLLDRC_CTRL}3253};3254 3255static const struct cdns_reg_pairs sgmii_usxgmii_xcvr_diag_ln_regs[] = {3256	{0x0111, XCVR_DIAG_HSCLK_SEL},3257	{0x0103, XCVR_DIAG_HSCLK_DIV},3258	{0x0A9B, XCVR_DIAG_PLLDRC_CTRL}3259};3260 3261static const struct cdns_torrent_vals usxgmii_sgmii_link_cmn_vals = {3262	.reg_pairs = usxgmii_sgmii_link_cmn_regs,3263	.num_regs = ARRAY_SIZE(usxgmii_sgmii_link_cmn_regs),3264};3265 3266static const struct cdns_torrent_vals usxgmii_sgmii_xcvr_diag_ln_vals = {3267	.reg_pairs = usxgmii_sgmii_xcvr_diag_ln_regs,3268	.num_regs = ARRAY_SIZE(usxgmii_sgmii_xcvr_diag_ln_regs),3269};3270 3271static const struct cdns_torrent_vals sgmii_usxgmii_xcvr_diag_ln_vals = {3272	.reg_pairs = sgmii_usxgmii_xcvr_diag_ln_regs,3273	.num_regs = ARRAY_SIZE(sgmii_usxgmii_xcvr_diag_ln_regs),3274};3275 3276/* Multilink USXGMII, using PLL0, 156.25 MHz Ref clk, no SSC */3277static const struct cdns_reg_pairs ml_usxgmii_pll0_156_25_no_ssc_cmn_regs[] = {3278	{0x0014, CMN_PLL0_DSM_FBH_OVRD_M0},3279	{0x0005, CMN_PLL0_DSM_FBL_OVRD_M0},3280	{0x061B, CMN_PLL0_VCOCAL_INIT_TMR},3281	{0x0019, CMN_PLL0_VCOCAL_ITER_TMR},3282	{0x1354, CMN_PLL0_VCOCAL_REFTIM_START},3283	{0x1354, CMN_PLL0_VCOCAL_PLLCNT_START},3284	{0x0003, CMN_PLL0_VCOCAL_TCTRL},3285	{0x0138, CMN_PLL0_LOCK_REFCNT_START},3286	{0x0138, CMN_PLL0_LOCK_PLLCNT_START}3287};3288 3289static const struct cdns_torrent_vals ml_usxgmii_pll0_156_25_no_ssc_cmn_vals = {3290	.reg_pairs = ml_usxgmii_pll0_156_25_no_ssc_cmn_regs,3291	.num_regs = ARRAY_SIZE(ml_usxgmii_pll0_156_25_no_ssc_cmn_regs),3292};3293 3294/* Multilink SGMII/QSGMII, using PLL1, 100 MHz Ref clk, no SSC */3295static const struct cdns_reg_pairs ml_sgmii_pll1_100_no_ssc_cmn_regs[] = {3296	{0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},3297	{0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},3298	{0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},3299	{0x0003, CMN_PLL1_VCOCAL_TCTRL},3300	{0x007F, CMN_TXPUCAL_TUNE},3301	{0x007F, CMN_TXPDCAL_TUNE}3302};3303 3304static const struct cdns_torrent_vals ml_sgmii_pll1_100_no_ssc_cmn_vals = {3305	.reg_pairs = ml_sgmii_pll1_100_no_ssc_cmn_regs,3306	.num_regs = ARRAY_SIZE(ml_sgmii_pll1_100_no_ssc_cmn_regs),3307};3308 3309/* TI J7200, Multilink USXGMII, using PLL0, 156.25 MHz Ref clk, no SSC */3310static const struct cdns_reg_pairs j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_regs[] = {3311	{0x0014, CMN_SSM_BIAS_TMR},3312	{0x0028, CMN_PLLSM0_PLLPRE_TMR},3313	{0x00A4, CMN_PLLSM0_PLLLOCK_TMR},3314	{0x0062, CMN_BGCAL_INIT_TMR},3315	{0x0062, CMN_BGCAL_ITER_TMR},3316	{0x0014, CMN_IBCAL_INIT_TMR},3317	{0x0018, CMN_TXPUCAL_INIT_TMR},3318	{0x0005, CMN_TXPUCAL_ITER_TMR},3319	{0x0018, CMN_TXPDCAL_INIT_TMR},3320	{0x0005, CMN_TXPDCAL_ITER_TMR},3321	{0x024A, CMN_RXCAL_INIT_TMR},3322	{0x0005, CMN_RXCAL_ITER_TMR},3323	{0x000B, CMN_SD_CAL_REFTIM_START},3324	{0x0132, CMN_SD_CAL_PLLCNT_START},3325	{0x0014, CMN_PLL0_DSM_FBH_OVRD_M0},3326	{0x0005, CMN_PLL0_DSM_FBL_OVRD_M0},3327	{0x061B, CMN_PLL0_VCOCAL_INIT_TMR},3328	{0x0019, CMN_PLL0_VCOCAL_ITER_TMR},3329	{0x1354, CMN_PLL0_VCOCAL_REFTIM_START},3330	{0x1354, CMN_PLL0_VCOCAL_PLLCNT_START},3331	{0x0003, CMN_PLL0_VCOCAL_TCTRL},3332	{0x0138, CMN_PLL0_LOCK_REFCNT_START},3333	{0x0138, CMN_PLL0_LOCK_PLLCNT_START}3334};3335 3336static const struct cdns_torrent_vals j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_vals = {3337	.reg_pairs = j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_regs,3338	.num_regs = ARRAY_SIZE(j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_regs),3339};3340 3341/* TI J7200, Multilink SGMII/QSGMII, using PLL1, 100 MHz Ref clk, no SSC */3342static const struct cdns_reg_pairs j7200_ml_sgmii_pll1_100_no_ssc_cmn_regs[] = {3343	{0x0028, CMN_PLLSM1_PLLPRE_TMR},3344	{0x00A4, CMN_PLLSM1_PLLLOCK_TMR},3345	{0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},3346	{0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},3347	{0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},3348	{0x0003, CMN_PLL1_VCOCAL_TCTRL},3349	{0x007F, CMN_TXPUCAL_TUNE},3350	{0x007F, CMN_TXPDCAL_TUNE}3351};3352 3353static const struct cdns_torrent_vals j7200_ml_sgmii_pll1_100_no_ssc_cmn_vals = {3354	.reg_pairs = j7200_ml_sgmii_pll1_100_no_ssc_cmn_regs,3355	.num_regs = ARRAY_SIZE(j7200_ml_sgmii_pll1_100_no_ssc_cmn_regs),3356};3357 3358/* PCIe and USXGMII link configuration */3359static const struct cdns_reg_pairs pcie_usxgmii_link_cmn_regs[] = {3360	{0x0003, PHY_PLL_CFG},3361	{0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},3362	{0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},3363	{0x0400, CMN_PDIAG_PLL1_CLK_SEL_M0}3364};3365 3366static const struct cdns_reg_pairs pcie_usxgmii_xcvr_diag_ln_regs[] = {3367	{0x0000, XCVR_DIAG_HSCLK_SEL},3368	{0x0001, XCVR_DIAG_HSCLK_DIV},3369	{0x0012, XCVR_DIAG_PLLDRC_CTRL}3370};3371 3372static const struct cdns_reg_pairs usxgmii_pcie_xcvr_diag_ln_regs[] = {3373	{0x0011, XCVR_DIAG_HSCLK_SEL},3374	{0x0001, XCVR_DIAG_HSCLK_DIV},3375	{0x0089, XCVR_DIAG_PLLDRC_CTRL}3376};3377 3378static const struct cdns_torrent_vals pcie_usxgmii_link_cmn_vals = {3379	.reg_pairs = pcie_usxgmii_link_cmn_regs,3380	.num_regs = ARRAY_SIZE(pcie_usxgmii_link_cmn_regs),3381};3382 3383static const struct cdns_torrent_vals pcie_usxgmii_xcvr_diag_ln_vals = {3384	.reg_pairs = pcie_usxgmii_xcvr_diag_ln_regs,3385	.num_regs = ARRAY_SIZE(pcie_usxgmii_xcvr_diag_ln_regs),3386};3387 3388static const struct cdns_torrent_vals usxgmii_pcie_xcvr_diag_ln_vals = {3389	.reg_pairs = usxgmii_pcie_xcvr_diag_ln_regs,3390	.num_regs = ARRAY_SIZE(usxgmii_pcie_xcvr_diag_ln_regs),3391};3392 3393/*3394 * Multilink USXGMII, using PLL1, 156.25 MHz Ref clk, no SSC3395 */3396static const struct cdns_reg_pairs ml_usxgmii_pll1_156_25_no_ssc_cmn_regs[] = {3397	{0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},3398	{0x0014, CMN_PLL1_DSM_FBH_OVRD_M0},3399	{0x0005, CMN_PLL1_DSM_FBL_OVRD_M0},3400	{0x061B, CMN_PLL1_VCOCAL_INIT_TMR},3401	{0x0019, CMN_PLL1_VCOCAL_ITER_TMR},3402	{0x1354, CMN_PLL1_VCOCAL_REFTIM_START},3403	{0x1354, CMN_PLL1_VCOCAL_PLLCNT_START},3404	{0x0003, CMN_PLL1_VCOCAL_TCTRL},3405	{0x0138, CMN_PLL1_LOCK_REFCNT_START},3406	{0x0138, CMN_PLL1_LOCK_PLLCNT_START},3407	{0x007F, CMN_TXPUCAL_TUNE},3408	{0x007F, CMN_TXPDCAL_TUNE}3409};3410 3411static const struct cdns_reg_pairs ml_usxgmii_156_25_no_ssc_tx_ln_regs[] = {3412	{0x00F3, TX_PSC_A0},3413	{0x04A2, TX_PSC_A2},3414	{0x04A2, TX_PSC_A3 },3415	{0x0000, TX_TXCC_CPOST_MULT_00},3416	{0x0000, XCVR_DIAG_PSC_OVRD}3417};3418 3419static const struct cdns_reg_pairs ml_usxgmii_156_25_no_ssc_rx_ln_regs[] = {3420	{0x091D, RX_PSC_A0},3421	{0x0900, RX_PSC_A2},3422	{0x0100, RX_PSC_A3},3423	{0x0030, RX_REE_SMGM_CTRL1},3424	{0x03C7, RX_REE_GCSM1_EQENM_PH1},3425	{0x01C7, RX_REE_GCSM1_EQENM_PH2},3426	{0x0000, RX_DIAG_DFE_CTRL},3427	{0x0019, RX_REE_TAP1_CLIP},3428	{0x0019, RX_REE_TAP2TON_CLIP},3429	{0x00B9, RX_DIAG_NQST_CTRL},3430	{0x0C21, RX_DIAG_DFE_AMP_TUNE_2},3431	{0x0002, RX_DIAG_DFE_AMP_TUNE_3},3432	{0x0033, RX_DIAG_PI_RATE},3433	{0x0001, RX_DIAG_ACYA},3434	{0x018C, RX_CDRLF_CNFG}3435};3436 3437static const struct cdns_torrent_vals ml_usxgmii_pll1_156_25_no_ssc_cmn_vals = {3438	.reg_pairs = ml_usxgmii_pll1_156_25_no_ssc_cmn_regs,3439	.num_regs = ARRAY_SIZE(ml_usxgmii_pll1_156_25_no_ssc_cmn_regs),3440};3441 3442static const struct cdns_torrent_vals ml_usxgmii_156_25_no_ssc_tx_ln_vals = {3443	.reg_pairs = ml_usxgmii_156_25_no_ssc_tx_ln_regs,3444	.num_regs = ARRAY_SIZE(ml_usxgmii_156_25_no_ssc_tx_ln_regs),3445};3446 3447static const struct cdns_torrent_vals ml_usxgmii_156_25_no_ssc_rx_ln_vals = {3448	.reg_pairs = ml_usxgmii_156_25_no_ssc_rx_ln_regs,3449	.num_regs = ARRAY_SIZE(ml_usxgmii_156_25_no_ssc_rx_ln_regs),3450};3451 3452/* TI USXGMII configuration: Enable cmn_refclk_rcv_out_en */3453static const struct cdns_reg_pairs ti_usxgmii_phy_pma_cmn_regs[] = {3454	{0x0040, PHY_PMA_CMN_CTRL1},3455};3456 3457static const struct cdns_torrent_vals ti_usxgmii_phy_pma_cmn_vals = {3458	.reg_pairs = ti_usxgmii_phy_pma_cmn_regs,3459	.num_regs = ARRAY_SIZE(ti_usxgmii_phy_pma_cmn_regs),3460};3461 3462/* Single USXGMII link configuration */3463static const struct cdns_reg_pairs sl_usxgmii_link_cmn_regs[] = {3464	{0x0000, PHY_PLL_CFG},3465	{0x0400, CMN_PDIAG_PLL0_CLK_SEL_M0}3466};3467 3468static const struct cdns_reg_pairs sl_usxgmii_xcvr_diag_ln_regs[] = {3469	{0x0000, XCVR_DIAG_HSCLK_SEL},3470	{0x0001, XCVR_DIAG_HSCLK_DIV},3471	{0x0001, XCVR_DIAG_PLLDRC_CTRL}3472};3473 3474static const struct cdns_torrent_vals sl_usxgmii_link_cmn_vals = {3475	.reg_pairs = sl_usxgmii_link_cmn_regs,3476	.num_regs = ARRAY_SIZE(sl_usxgmii_link_cmn_regs),3477};3478 3479static const struct cdns_torrent_vals sl_usxgmii_xcvr_diag_ln_vals = {3480	.reg_pairs = sl_usxgmii_xcvr_diag_ln_regs,3481	.num_regs = ARRAY_SIZE(sl_usxgmii_xcvr_diag_ln_regs),3482};3483 3484/* Single link USXGMII, 156.25 MHz Ref clk, no SSC */3485static const struct cdns_reg_pairs sl_usxgmii_156_25_no_ssc_cmn_regs[] = {3486	{0x0014, CMN_SSM_BIAS_TMR},3487	{0x0028, CMN_PLLSM0_PLLPRE_TMR},3488	{0x00A4, CMN_PLLSM0_PLLLOCK_TMR},3489	{0x0028, CMN_PLLSM1_PLLPRE_TMR},3490	{0x00A4, CMN_PLLSM1_PLLLOCK_TMR},3491	{0x0062, CMN_BGCAL_INIT_TMR},3492	{0x0062, CMN_BGCAL_ITER_TMR},3493	{0x0014, CMN_IBCAL_INIT_TMR},3494	{0x0018, CMN_TXPUCAL_INIT_TMR},3495	{0x0005, CMN_TXPUCAL_ITER_TMR},3496	{0x0018, CMN_TXPDCAL_INIT_TMR},3497	{0x0005, CMN_TXPDCAL_ITER_TMR},3498	{0x024A, CMN_RXCAL_INIT_TMR},3499	{0x0005, CMN_RXCAL_ITER_TMR},3500	{0x000B, CMN_SD_CAL_REFTIM_START},3501	{0x0132, CMN_SD_CAL_PLLCNT_START},3502	{0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},3503	{0x0014, CMN_PLL0_DSM_FBH_OVRD_M0},3504	{0x0014, CMN_PLL1_DSM_FBH_OVRD_M0},3505	{0x0005, CMN_PLL0_DSM_FBL_OVRD_M0},3506	{0x0005, CMN_PLL1_DSM_FBL_OVRD_M0},3507	{0x061B, CMN_PLL0_VCOCAL_INIT_TMR},3508	{0x061B, CMN_PLL1_VCOCAL_INIT_TMR},3509	{0x0019, CMN_PLL0_VCOCAL_ITER_TMR},3510	{0x0019, CMN_PLL1_VCOCAL_ITER_TMR},3511	{0x1354, CMN_PLL0_VCOCAL_REFTIM_START},3512	{0x1354, CMN_PLL1_VCOCAL_REFTIM_START},3513	{0x1354, CMN_PLL0_VCOCAL_PLLCNT_START},3514	{0x1354, CMN_PLL1_VCOCAL_PLLCNT_START},3515	{0x0003, CMN_PLL0_VCOCAL_TCTRL},3516	{0x0003, CMN_PLL1_VCOCAL_TCTRL},3517	{0x0138, CMN_PLL0_LOCK_REFCNT_START},3518	{0x0138, CMN_PLL1_LOCK_REFCNT_START},3519	{0x0138, CMN_PLL0_LOCK_PLLCNT_START},3520	{0x0138, CMN_PLL1_LOCK_PLLCNT_START}3521};3522 3523static const struct cdns_reg_pairs usxgmii_156_25_no_ssc_tx_ln_regs[] = {3524	{0x07A2, TX_RCVDET_ST_TMR},3525	{0x00F3, TX_PSC_A0},3526	{0x04A2, TX_PSC_A2},3527	{0x04A2, TX_PSC_A3},3528	{0x0000, TX_TXCC_CPOST_MULT_00},3529	{0x0000, XCVR_DIAG_PSC_OVRD}3530};3531 3532static const struct cdns_reg_pairs usxgmii_156_25_no_ssc_rx_ln_regs[] = {3533	{0x0014, RX_SDCAL0_INIT_TMR},3534	{0x0062, RX_SDCAL0_ITER_TMR},3535	{0x0014, RX_SDCAL1_INIT_TMR},3536	{0x0062, RX_SDCAL1_ITER_TMR},3537	{0x091D, RX_PSC_A0},3538	{0x0900, RX_PSC_A2},3539	{0x0100, RX_PSC_A3},3540	{0x0030, RX_REE_SMGM_CTRL1},3541	{0x03C7, RX_REE_GCSM1_EQENM_PH1},3542	{0x01C7, RX_REE_GCSM1_EQENM_PH2},3543	{0x0000, RX_DIAG_DFE_CTRL},3544	{0x0019, RX_REE_TAP1_CLIP},3545	{0x0019, RX_REE_TAP2TON_CLIP},3546	{0x00B9, RX_DIAG_NQST_CTRL},3547	{0x0C21, RX_DIAG_DFE_AMP_TUNE_2},3548	{0x0002, RX_DIAG_DFE_AMP_TUNE_3},3549	{0x0033, RX_DIAG_PI_RATE},3550	{0x0001, RX_DIAG_ACYA},3551	{0x018C, RX_CDRLF_CNFG}3552};3553 3554static const struct cdns_torrent_vals sl_usxgmii_156_25_no_ssc_cmn_vals = {3555	.reg_pairs = sl_usxgmii_156_25_no_ssc_cmn_regs,3556	.num_regs = ARRAY_SIZE(sl_usxgmii_156_25_no_ssc_cmn_regs),3557};3558 3559static const struct cdns_torrent_vals usxgmii_156_25_no_ssc_tx_ln_vals = {3560	.reg_pairs = usxgmii_156_25_no_ssc_tx_ln_regs,3561	.num_regs = ARRAY_SIZE(usxgmii_156_25_no_ssc_tx_ln_regs),3562};3563 3564static const struct cdns_torrent_vals usxgmii_156_25_no_ssc_rx_ln_vals = {3565	.reg_pairs = usxgmii_156_25_no_ssc_rx_ln_regs,3566	.num_regs = ARRAY_SIZE(usxgmii_156_25_no_ssc_rx_ln_regs),3567};3568 3569/* PCIe and DP link configuration */3570static const struct cdns_reg_pairs pcie_dp_link_cmn_regs[] = {3571	{0x0003, PHY_PLL_CFG},3572	{0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},3573	{0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1}3574};3575 3576static const struct cdns_reg_pairs pcie_dp_xcvr_diag_ln_regs[] = {3577	{0x0000, XCVR_DIAG_HSCLK_SEL},3578	{0x0001, XCVR_DIAG_HSCLK_DIV},3579	{0x0012, XCVR_DIAG_PLLDRC_CTRL}3580};3581 3582static const struct cdns_reg_pairs dp_pcie_xcvr_diag_ln_regs[] = {3583	{0x0001, XCVR_DIAG_HSCLK_SEL},3584	{0x0009, XCVR_DIAG_PLLDRC_CTRL}3585};3586 3587static const struct cdns_torrent_vals pcie_dp_link_cmn_vals = {3588	.reg_pairs = pcie_dp_link_cmn_regs,3589	.num_regs = ARRAY_SIZE(pcie_dp_link_cmn_regs),3590};3591 3592static const struct cdns_torrent_vals pcie_dp_xcvr_diag_ln_vals = {3593	.reg_pairs = pcie_dp_xcvr_diag_ln_regs,3594	.num_regs = ARRAY_SIZE(pcie_dp_xcvr_diag_ln_regs),3595};3596 3597static const struct cdns_torrent_vals dp_pcie_xcvr_diag_ln_vals = {3598	.reg_pairs = dp_pcie_xcvr_diag_ln_regs,3599	.num_regs = ARRAY_SIZE(dp_pcie_xcvr_diag_ln_regs),3600};3601 3602/* DP Multilink, 100 MHz Ref clk, no SSC */3603static const struct cdns_reg_pairs dp_100_no_ssc_cmn_regs[] = {3604	{0x007F, CMN_TXPUCAL_TUNE},3605	{0x007F, CMN_TXPDCAL_TUNE}3606};3607 3608static const struct cdns_reg_pairs dp_100_no_ssc_tx_ln_regs[] = {3609	{0x00FB, TX_PSC_A0},3610	{0x04AA, TX_PSC_A2},3611	{0x04AA, TX_PSC_A3},3612	{0x000F, XCVR_DIAG_BIDI_CTRL}3613};3614 3615static const struct cdns_reg_pairs dp_100_no_ssc_rx_ln_regs[] = {3616	{0x0000, RX_PSC_A0},3617	{0x0000, RX_PSC_A2},3618	{0x0000, RX_PSC_A3},3619	{0x0000, RX_PSC_CAL},3620	{0x0000, RX_REE_GCSM1_CTRL},3621	{0x0000, RX_REE_GCSM2_CTRL},3622	{0x0000, RX_REE_PERGCSM_CTRL}3623};3624 3625static const struct cdns_torrent_vals dp_100_no_ssc_cmn_vals = {3626	.reg_pairs = dp_100_no_ssc_cmn_regs,3627	.num_regs = ARRAY_SIZE(dp_100_no_ssc_cmn_regs),3628};3629 3630static const struct cdns_torrent_vals dp_100_no_ssc_tx_ln_vals = {3631	.reg_pairs = dp_100_no_ssc_tx_ln_regs,3632	.num_regs = ARRAY_SIZE(dp_100_no_ssc_tx_ln_regs),3633};3634 3635static const struct cdns_torrent_vals dp_100_no_ssc_rx_ln_vals = {3636	.reg_pairs = dp_100_no_ssc_rx_ln_regs,3637	.num_regs = ARRAY_SIZE(dp_100_no_ssc_rx_ln_regs),3638};3639 3640/* Single DisplayPort(DP) link configuration */3641static const struct cdns_reg_pairs sl_dp_link_cmn_regs[] = {3642	{0x0000, PHY_PLL_CFG},3643};3644 3645static const struct cdns_reg_pairs sl_dp_xcvr_diag_ln_regs[] = {3646	{0x0000, XCVR_DIAG_HSCLK_SEL},3647	{0x0001, XCVR_DIAG_PLLDRC_CTRL}3648};3649 3650static const struct cdns_torrent_vals sl_dp_link_cmn_vals = {3651	.reg_pairs = sl_dp_link_cmn_regs,3652	.num_regs = ARRAY_SIZE(sl_dp_link_cmn_regs),3653};3654 3655static const struct cdns_torrent_vals sl_dp_xcvr_diag_ln_vals = {3656	.reg_pairs = sl_dp_xcvr_diag_ln_regs,3657	.num_regs = ARRAY_SIZE(sl_dp_xcvr_diag_ln_regs),3658};3659 3660/* Single DP, 19.2 MHz Ref clk, no SSC */3661static const struct cdns_reg_pairs sl_dp_19_2_no_ssc_cmn_regs[] = {3662	{0x0014, CMN_SSM_BIAS_TMR},3663	{0x0027, CMN_PLLSM0_PLLPRE_TMR},3664	{0x00A1, CMN_PLLSM0_PLLLOCK_TMR},3665	{0x0027, CMN_PLLSM1_PLLPRE_TMR},3666	{0x00A1, CMN_PLLSM1_PLLLOCK_TMR},3667	{0x0060, CMN_BGCAL_INIT_TMR},3668	{0x0060, CMN_BGCAL_ITER_TMR},3669	{0x0014, CMN_IBCAL_INIT_TMR},3670	{0x0018, CMN_TXPUCAL_INIT_TMR},3671	{0x0005, CMN_TXPUCAL_ITER_TMR},3672	{0x0018, CMN_TXPDCAL_INIT_TMR},3673	{0x0005, CMN_TXPDCAL_ITER_TMR},3674	{0x0240, CMN_RXCAL_INIT_TMR},3675	{0x0005, CMN_RXCAL_ITER_TMR},3676	{0x0002, CMN_SD_CAL_INIT_TMR},3677	{0x0002, CMN_SD_CAL_ITER_TMR},3678	{0x000B, CMN_SD_CAL_REFTIM_START},3679	{0x0137, CMN_SD_CAL_PLLCNT_START},3680	{0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},3681	{0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},3682	{0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},3683	{0x0004, CMN_PLL0_DSM_DIAG_M0},3684	{0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},3685	{0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},3686	{0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},3687	{0x0004, CMN_PLL1_DSM_DIAG_M0},3688	{0x00C0, CMN_PLL0_VCOCAL_INIT_TMR},3689	{0x0004, CMN_PLL0_VCOCAL_ITER_TMR},3690	{0x00C0, CMN_PLL1_VCOCAL_INIT_TMR},3691	{0x0004, CMN_PLL1_VCOCAL_ITER_TMR},3692	{0x0260, CMN_PLL0_VCOCAL_REFTIM_START},3693	{0x0003, CMN_PLL0_VCOCAL_TCTRL},3694	{0x0260, CMN_PLL1_VCOCAL_REFTIM_START},3695	{0x0003, CMN_PLL1_VCOCAL_TCTRL}3696};3697 3698static const struct cdns_reg_pairs sl_dp_19_2_no_ssc_tx_ln_regs[] = {3699	{0x0780, TX_RCVDET_ST_TMR},3700	{0x00FB, TX_PSC_A0},3701	{0x04AA, TX_PSC_A2},3702	{0x04AA, TX_PSC_A3},3703	{0x000F, XCVR_DIAG_BIDI_CTRL}3704};3705 3706static const struct cdns_reg_pairs sl_dp_19_2_no_ssc_rx_ln_regs[] = {3707	{0x0000, RX_PSC_A0},3708	{0x0000, RX_PSC_A2},3709	{0x0000, RX_PSC_A3},3710	{0x0000, RX_PSC_CAL},3711	{0x0000, RX_REE_GCSM1_CTRL},3712	{0x0000, RX_REE_GCSM2_CTRL},3713	{0x0000, RX_REE_PERGCSM_CTRL}3714};3715 3716static const struct cdns_torrent_vals sl_dp_19_2_no_ssc_cmn_vals = {3717	.reg_pairs = sl_dp_19_2_no_ssc_cmn_regs,3718	.num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_cmn_regs),3719};3720 3721static const struct cdns_torrent_vals sl_dp_19_2_no_ssc_tx_ln_vals = {3722	.reg_pairs = sl_dp_19_2_no_ssc_tx_ln_regs,3723	.num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_tx_ln_regs),3724};3725 3726static const struct cdns_torrent_vals sl_dp_19_2_no_ssc_rx_ln_vals = {3727	.reg_pairs = sl_dp_19_2_no_ssc_rx_ln_regs,3728	.num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_rx_ln_regs),3729};3730 3731/* Single DP, 25 MHz Ref clk, no SSC */3732static const struct cdns_reg_pairs sl_dp_25_no_ssc_cmn_regs[] = {3733	{0x0019, CMN_SSM_BIAS_TMR},3734	{0x0032, CMN_PLLSM0_PLLPRE_TMR},3735	{0x00D1, CMN_PLLSM0_PLLLOCK_TMR},3736	{0x0032, CMN_PLLSM1_PLLPRE_TMR},3737	{0x00D1, CMN_PLLSM1_PLLLOCK_TMR},3738	{0x007D, CMN_BGCAL_INIT_TMR},3739	{0x007D, CMN_BGCAL_ITER_TMR},3740	{0x0019, CMN_IBCAL_INIT_TMR},3741	{0x001E, CMN_TXPUCAL_INIT_TMR},3742	{0x0006, CMN_TXPUCAL_ITER_TMR},3743	{0x001E, CMN_TXPDCAL_INIT_TMR},3744	{0x0006, CMN_TXPDCAL_ITER_TMR},3745	{0x02EE, CMN_RXCAL_INIT_TMR},3746	{0x0006, CMN_RXCAL_ITER_TMR},3747	{0x0002, CMN_SD_CAL_INIT_TMR},3748	{0x0002, CMN_SD_CAL_ITER_TMR},3749	{0x000E, CMN_SD_CAL_REFTIM_START},3750	{0x012B, CMN_SD_CAL_PLLCNT_START},3751	{0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},3752	{0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},3753	{0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},3754	{0x0004, CMN_PLL0_DSM_DIAG_M0},3755	{0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},3756	{0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},3757	{0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},3758	{0x0004, CMN_PLL1_DSM_DIAG_M0},3759	{0x00FA, CMN_PLL0_VCOCAL_INIT_TMR},3760	{0x0004, CMN_PLL0_VCOCAL_ITER_TMR},3761	{0x00FA, CMN_PLL1_VCOCAL_INIT_TMR},3762	{0x0004, CMN_PLL1_VCOCAL_ITER_TMR},3763	{0x0317, CMN_PLL0_VCOCAL_REFTIM_START},3764	{0x0003, CMN_PLL0_VCOCAL_TCTRL},3765	{0x0317, CMN_PLL1_VCOCAL_REFTIM_START},3766	{0x0003, CMN_PLL1_VCOCAL_TCTRL}3767};3768 3769static const struct cdns_reg_pairs sl_dp_25_no_ssc_tx_ln_regs[] = {3770	{0x09C4, TX_RCVDET_ST_TMR},3771	{0x00FB, TX_PSC_A0},3772	{0x04AA, TX_PSC_A2},3773	{0x04AA, TX_PSC_A3},3774	{0x000F, XCVR_DIAG_BIDI_CTRL}3775};3776 3777static const struct cdns_reg_pairs sl_dp_25_no_ssc_rx_ln_regs[] = {3778	{0x0000, RX_PSC_A0},3779	{0x0000, RX_PSC_A2},3780	{0x0000, RX_PSC_A3},3781	{0x0000, RX_PSC_CAL},3782	{0x0000, RX_REE_GCSM1_CTRL},3783	{0x0000, RX_REE_GCSM2_CTRL},3784	{0x0000, RX_REE_PERGCSM_CTRL}3785};3786 3787static const struct cdns_torrent_vals sl_dp_25_no_ssc_cmn_vals = {3788	.reg_pairs = sl_dp_25_no_ssc_cmn_regs,3789	.num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_cmn_regs),3790};3791 3792static const struct cdns_torrent_vals sl_dp_25_no_ssc_tx_ln_vals = {3793	.reg_pairs = sl_dp_25_no_ssc_tx_ln_regs,3794	.num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_tx_ln_regs),3795};3796 3797static const struct cdns_torrent_vals sl_dp_25_no_ssc_rx_ln_vals = {3798	.reg_pairs = sl_dp_25_no_ssc_rx_ln_regs,3799	.num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_rx_ln_regs),3800};3801 3802/* Single DP, 100 MHz Ref clk, no SSC */3803static const struct cdns_reg_pairs sl_dp_100_no_ssc_cmn_regs[] = {3804	{0x0003, CMN_PLL0_VCOCAL_TCTRL},3805	{0x0003, CMN_PLL1_VCOCAL_TCTRL}3806};3807 3808static const struct cdns_reg_pairs sl_dp_100_no_ssc_tx_ln_regs[] = {3809	{0x00FB, TX_PSC_A0},3810	{0x04AA, TX_PSC_A2},3811	{0x04AA, TX_PSC_A3},3812	{0x000F, XCVR_DIAG_BIDI_CTRL}3813};3814 3815static const struct cdns_reg_pairs sl_dp_100_no_ssc_rx_ln_regs[] = {3816	{0x0000, RX_PSC_A0},3817	{0x0000, RX_PSC_A2},3818	{0x0000, RX_PSC_A3},3819	{0x0000, RX_PSC_CAL},3820	{0x0000, RX_REE_GCSM1_CTRL},3821	{0x0000, RX_REE_GCSM2_CTRL},3822	{0x0000, RX_REE_PERGCSM_CTRL}3823};3824 3825static const struct cdns_torrent_vals sl_dp_100_no_ssc_cmn_vals = {3826	.reg_pairs = sl_dp_100_no_ssc_cmn_regs,3827	.num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_cmn_regs),3828};3829 3830static const struct cdns_torrent_vals sl_dp_100_no_ssc_tx_ln_vals = {3831	.reg_pairs = sl_dp_100_no_ssc_tx_ln_regs,3832	.num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_tx_ln_regs),3833};3834 3835static const struct cdns_torrent_vals sl_dp_100_no_ssc_rx_ln_vals = {3836	.reg_pairs = sl_dp_100_no_ssc_rx_ln_regs,3837	.num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_rx_ln_regs),3838};3839 3840/* USB and SGMII/QSGMII link configuration */3841static const struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = {3842	{0x0002, PHY_PLL_CFG},3843	{0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0},3844	{0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}3845};3846 3847static const struct cdns_reg_pairs usb_sgmii_xcvr_diag_ln_regs[] = {3848	{0x0000, XCVR_DIAG_HSCLK_SEL},3849	{0x0001, XCVR_DIAG_HSCLK_DIV},3850	{0x0041, XCVR_DIAG_PLLDRC_CTRL}3851};3852 3853static const struct cdns_reg_pairs sgmii_usb_xcvr_diag_ln_regs[] = {3854	{0x0011, XCVR_DIAG_HSCLK_SEL},3855	{0x0003, XCVR_DIAG_HSCLK_DIV},3856	{0x009B, XCVR_DIAG_PLLDRC_CTRL}3857};3858 3859static const struct cdns_torrent_vals usb_sgmii_link_cmn_vals = {3860	.reg_pairs = usb_sgmii_link_cmn_regs,3861	.num_regs = ARRAY_SIZE(usb_sgmii_link_cmn_regs),3862};3863 3864static const struct cdns_torrent_vals usb_sgmii_xcvr_diag_ln_vals = {3865	.reg_pairs = usb_sgmii_xcvr_diag_ln_regs,3866	.num_regs = ARRAY_SIZE(usb_sgmii_xcvr_diag_ln_regs),3867};3868 3869static const struct cdns_torrent_vals sgmii_usb_xcvr_diag_ln_vals = {3870	.reg_pairs = sgmii_usb_xcvr_diag_ln_regs,3871	.num_regs = ARRAY_SIZE(sgmii_usb_xcvr_diag_ln_regs),3872};3873 3874/* PCIe and USB Unique SSC link configuration */3875static const struct cdns_reg_pairs pcie_usb_link_cmn_regs[] = {3876	{0x0003, PHY_PLL_CFG},3877	{0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},3878	{0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},3879	{0x8600, CMN_PDIAG_PLL1_CLK_SEL_M0}3880};3881 3882static const struct cdns_reg_pairs pcie_usb_xcvr_diag_ln_regs[] = {3883	{0x0000, XCVR_DIAG_HSCLK_SEL},3884	{0x0001, XCVR_DIAG_HSCLK_DIV},3885	{0x0012, XCVR_DIAG_PLLDRC_CTRL}3886};3887 3888static const struct cdns_reg_pairs usb_pcie_xcvr_diag_ln_regs[] = {3889	{0x0011, XCVR_DIAG_HSCLK_SEL},3890	{0x0001, XCVR_DIAG_HSCLK_DIV},3891	{0x00C9, XCVR_DIAG_PLLDRC_CTRL}3892};3893 3894static const struct cdns_torrent_vals pcie_usb_link_cmn_vals = {3895	.reg_pairs = pcie_usb_link_cmn_regs,3896	.num_regs = ARRAY_SIZE(pcie_usb_link_cmn_regs),3897};3898 3899static const struct cdns_torrent_vals pcie_usb_xcvr_diag_ln_vals = {3900	.reg_pairs = pcie_usb_xcvr_diag_ln_regs,3901	.num_regs = ARRAY_SIZE(pcie_usb_xcvr_diag_ln_regs),3902};3903 3904static const struct cdns_torrent_vals usb_pcie_xcvr_diag_ln_vals = {3905	.reg_pairs = usb_pcie_xcvr_diag_ln_regs,3906	.num_regs = ARRAY_SIZE(usb_pcie_xcvr_diag_ln_regs),3907};3908 3909/* USB 100 MHz Ref clk, internal SSC */3910static const struct cdns_reg_pairs usb_100_int_ssc_cmn_regs[] = {3911	{0x0004, CMN_PLL0_DSM_DIAG_M0},3912	{0x0004, CMN_PLL0_DSM_DIAG_M1},3913	{0x0004, CMN_PLL1_DSM_DIAG_M0},3914	{0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},3915	{0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},3916	{0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},3917	{0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},3918	{0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},3919	{0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},3920	{0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},3921	{0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},3922	{0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},3923	{0x0064, CMN_PLL0_INTDIV_M0},3924	{0x0050, CMN_PLL0_INTDIV_M1},3925	{0x0064, CMN_PLL1_INTDIV_M0},3926	{0x0002, CMN_PLL0_FRACDIVH_M0},3927	{0x0002, CMN_PLL0_FRACDIVH_M1},3928	{0x0002, CMN_PLL1_FRACDIVH_M0},3929	{0x0044, CMN_PLL0_HIGH_THR_M0},3930	{0x0036, CMN_PLL0_HIGH_THR_M1},3931	{0x0044, CMN_PLL1_HIGH_THR_M0},3932	{0x0002, CMN_PDIAG_PLL0_CTRL_M0},3933	{0x0002, CMN_PDIAG_PLL0_CTRL_M1},3934	{0x0002, CMN_PDIAG_PLL1_CTRL_M0},3935	{0x0001, CMN_PLL0_SS_CTRL1_M0},3936	{0x0001, CMN_PLL0_SS_CTRL1_M1},3937	{0x0001, CMN_PLL1_SS_CTRL1_M0},3938	{0x011B, CMN_PLL0_SS_CTRL2_M0},3939	{0x011B, CMN_PLL0_SS_CTRL2_M1},3940	{0x011B, CMN_PLL1_SS_CTRL2_M0},3941	{0x006E, CMN_PLL0_SS_CTRL3_M0},3942	{0x0058, CMN_PLL0_SS_CTRL3_M1},3943	{0x006E, CMN_PLL1_SS_CTRL3_M0},3944	{0x000E, CMN_PLL0_SS_CTRL4_M0},3945	{0x0012, CMN_PLL0_SS_CTRL4_M1},3946	{0x000E, CMN_PLL1_SS_CTRL4_M0},3947	{0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},3948	{0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},3949	{0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},3950	{0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},3951	{0x00C7, CMN_PLL0_LOCK_REFCNT_START},3952	{0x00C7, CMN_PLL1_LOCK_REFCNT_START},3953	{0x00C7, CMN_PLL0_LOCK_PLLCNT_START},3954	{0x00C7, CMN_PLL1_LOCK_PLLCNT_START},3955	{0x0005, CMN_PLL0_LOCK_PLLCNT_THR},3956	{0x0005, CMN_PLL1_LOCK_PLLCNT_THR},3957	{0x8200, CMN_CDIAG_CDB_PWRI_OVRD},3958	{0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD},3959	{0x007F, CMN_TXPUCAL_TUNE},3960	{0x007F, CMN_TXPDCAL_TUNE}3961};3962 3963static const struct cdns_torrent_vals usb_100_int_ssc_cmn_vals = {3964	.reg_pairs = usb_100_int_ssc_cmn_regs,3965	.num_regs = ARRAY_SIZE(usb_100_int_ssc_cmn_regs),3966};3967 3968/* Single USB link configuration */3969static const struct cdns_reg_pairs sl_usb_link_cmn_regs[] = {3970	{0x0000, PHY_PLL_CFG},3971	{0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}3972};3973 3974static const struct cdns_reg_pairs sl_usb_xcvr_diag_ln_regs[] = {3975	{0x0000, XCVR_DIAG_HSCLK_SEL},3976	{0x0001, XCVR_DIAG_HSCLK_DIV},3977	{0x0041, XCVR_DIAG_PLLDRC_CTRL}3978};3979 3980static const struct cdns_torrent_vals sl_usb_link_cmn_vals = {3981	.reg_pairs = sl_usb_link_cmn_regs,3982	.num_regs = ARRAY_SIZE(sl_usb_link_cmn_regs),3983};3984 3985static const struct cdns_torrent_vals sl_usb_xcvr_diag_ln_vals = {3986	.reg_pairs = sl_usb_xcvr_diag_ln_regs,3987	.num_regs = ARRAY_SIZE(sl_usb_xcvr_diag_ln_regs),3988};3989 3990/* USB PHY PCS common configuration */3991static const struct cdns_reg_pairs usb_phy_pcs_cmn_regs[] = {3992	{0x0A0A, PHY_PIPE_USB3_GEN2_PRE_CFG0},3993	{0x1000, PHY_PIPE_USB3_GEN2_POST_CFG0},3994	{0x0010, PHY_PIPE_USB3_GEN2_POST_CFG1}3995};3996 3997static const struct cdns_torrent_vals usb_phy_pcs_cmn_vals = {3998	.reg_pairs = usb_phy_pcs_cmn_regs,3999	.num_regs = ARRAY_SIZE(usb_phy_pcs_cmn_regs),4000};4001 4002/* USB 100 MHz Ref clk, no SSC */4003static const struct cdns_reg_pairs sl_usb_100_no_ssc_cmn_regs[] = {4004	{0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},4005	{0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},4006	{0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},4007	{0x0003, CMN_PLL0_VCOCAL_TCTRL},4008	{0x0003, CMN_PLL1_VCOCAL_TCTRL},4009	{0x8200, CMN_CDIAG_CDB_PWRI_OVRD},4010	{0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}4011};4012 4013static const struct cdns_torrent_vals sl_usb_100_no_ssc_cmn_vals = {4014	.reg_pairs = sl_usb_100_no_ssc_cmn_regs,4015	.num_regs = ARRAY_SIZE(sl_usb_100_no_ssc_cmn_regs),4016};4017 4018static const struct cdns_reg_pairs usb_100_no_ssc_cmn_regs[] = {4019	{0x8200, CMN_CDIAG_CDB_PWRI_OVRD},4020	{0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD},4021	{0x007F, CMN_TXPUCAL_TUNE},4022	{0x007F, CMN_TXPDCAL_TUNE}4023};4024 4025static const struct cdns_reg_pairs usb_100_no_ssc_tx_ln_regs[] = {4026	{0x02FF, TX_PSC_A0},4027	{0x06AF, TX_PSC_A1},4028	{0x06AE, TX_PSC_A2},4029	{0x06AE, TX_PSC_A3},4030	{0x2A82, TX_TXCC_CTRL},4031	{0x0014, TX_TXCC_CPOST_MULT_01},4032	{0x0003, XCVR_DIAG_PSC_OVRD}4033};4034 4035static const struct cdns_reg_pairs usb_100_no_ssc_rx_ln_regs[] = {4036	{0x0D1D, RX_PSC_A0},4037	{0x0D1D, RX_PSC_A1},4038	{0x0D00, RX_PSC_A2},4039	{0x0500, RX_PSC_A3},4040	{0x0013, RX_SIGDET_HL_FILT_TMR},4041	{0x0000, RX_REE_GCSM1_CTRL},4042	{0x0C02, RX_REE_ATTEN_THR},4043	{0x0330, RX_REE_SMGM_CTRL1},4044	{0x0300, RX_REE_SMGM_CTRL2},4045	{0x0019, RX_REE_TAP1_CLIP},4046	{0x0019, RX_REE_TAP2TON_CLIP},4047	{0x1004, RX_DIAG_SIGDET_TUNE},4048	{0x00F9, RX_DIAG_NQST_CTRL},4049	{0x0C01, RX_DIAG_DFE_AMP_TUNE_2},4050	{0x0002, RX_DIAG_DFE_AMP_TUNE_3},4051	{0x0000, RX_DIAG_PI_CAP},4052	{0x0031, RX_DIAG_PI_RATE},4053	{0x0001, RX_DIAG_ACYA},4054	{0x018C, RX_CDRLF_CNFG},4055	{0x0003, RX_CDRLF_CNFG3}4056};4057 4058static const struct cdns_torrent_vals usb_100_no_ssc_cmn_vals = {4059	.reg_pairs = usb_100_no_ssc_cmn_regs,4060	.num_regs = ARRAY_SIZE(usb_100_no_ssc_cmn_regs),4061};4062 4063static const struct cdns_torrent_vals usb_100_no_ssc_tx_ln_vals = {4064	.reg_pairs = usb_100_no_ssc_tx_ln_regs,4065	.num_regs = ARRAY_SIZE(usb_100_no_ssc_tx_ln_regs),4066};4067 4068static const struct cdns_torrent_vals usb_100_no_ssc_rx_ln_vals = {4069	.reg_pairs = usb_100_no_ssc_rx_ln_regs,4070	.num_regs = ARRAY_SIZE(usb_100_no_ssc_rx_ln_regs),4071};4072 4073/* Single link USB, 100 MHz Ref clk, internal SSC */4074static const struct cdns_reg_pairs sl_usb_100_int_ssc_cmn_regs[] = {4075	{0x0004, CMN_PLL0_DSM_DIAG_M0},4076	{0x0004, CMN_PLL1_DSM_DIAG_M0},4077	{0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},4078	{0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},4079	{0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},4080	{0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},4081	{0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},4082	{0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},4083	{0x0064, CMN_PLL0_INTDIV_M0},4084	{0x0064, CMN_PLL1_INTDIV_M0},4085	{0x0002, CMN_PLL0_FRACDIVH_M0},4086	{0x0002, CMN_PLL1_FRACDIVH_M0},4087	{0x0044, CMN_PLL0_HIGH_THR_M0},4088	{0x0044, CMN_PLL1_HIGH_THR_M0},4089	{0x0002, CMN_PDIAG_PLL0_CTRL_M0},4090	{0x0002, CMN_PDIAG_PLL1_CTRL_M0},4091	{0x0001, CMN_PLL0_SS_CTRL1_M0},4092	{0x0001, CMN_PLL1_SS_CTRL1_M0},4093	{0x011B, CMN_PLL0_SS_CTRL2_M0},4094	{0x011B, CMN_PLL1_SS_CTRL2_M0},4095	{0x006E, CMN_PLL0_SS_CTRL3_M0},4096	{0x006E, CMN_PLL1_SS_CTRL3_M0},4097	{0x000E, CMN_PLL0_SS_CTRL4_M0},4098	{0x000E, CMN_PLL1_SS_CTRL4_M0},4099	{0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},4100	{0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},4101	{0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},4102	{0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},4103	{0x0003, CMN_PLL0_VCOCAL_TCTRL},4104	{0x0003, CMN_PLL1_VCOCAL_TCTRL},4105	{0x00C7, CMN_PLL0_LOCK_REFCNT_START},4106	{0x00C7, CMN_PLL1_LOCK_REFCNT_START},4107	{0x00C7, CMN_PLL0_LOCK_PLLCNT_START},4108	{0x00C7, CMN_PLL1_LOCK_PLLCNT_START},4109	{0x0005, CMN_PLL0_LOCK_PLLCNT_THR},4110	{0x0005, CMN_PLL1_LOCK_PLLCNT_THR},4111	{0x8200, CMN_CDIAG_CDB_PWRI_OVRD},4112	{0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}4113};4114 4115static const struct cdns_torrent_vals sl_usb_100_int_ssc_cmn_vals = {4116	.reg_pairs = sl_usb_100_int_ssc_cmn_regs,4117	.num_regs = ARRAY_SIZE(sl_usb_100_int_ssc_cmn_regs),4118};4119 4120/* PCIe and SGMII/QSGMII Unique SSC link configuration */4121static const struct cdns_reg_pairs pcie_sgmii_link_cmn_regs[] = {4122	{0x0003, PHY_PLL_CFG},4123	{0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0},4124	{0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1},4125	{0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0}4126};4127 4128static const struct cdns_reg_pairs pcie_sgmii_xcvr_diag_ln_regs[] = {4129	{0x0000, XCVR_DIAG_HSCLK_SEL},4130	{0x0001, XCVR_DIAG_HSCLK_DIV},4131	{0x0012, XCVR_DIAG_PLLDRC_CTRL}4132};4133 4134static const struct cdns_reg_pairs sgmii_pcie_xcvr_diag_ln_regs[] = {4135	{0x0011, XCVR_DIAG_HSCLK_SEL},4136	{0x0003, XCVR_DIAG_HSCLK_DIV},4137	{0x009B, XCVR_DIAG_PLLDRC_CTRL}4138};4139 4140static const struct cdns_torrent_vals pcie_sgmii_link_cmn_vals = {4141	.reg_pairs = pcie_sgmii_link_cmn_regs,4142	.num_regs = ARRAY_SIZE(pcie_sgmii_link_cmn_regs),4143};4144 4145static const struct cdns_torrent_vals pcie_sgmii_xcvr_diag_ln_vals = {4146	.reg_pairs = pcie_sgmii_xcvr_diag_ln_regs,4147	.num_regs = ARRAY_SIZE(pcie_sgmii_xcvr_diag_ln_regs),4148};4149 4150static const struct cdns_torrent_vals sgmii_pcie_xcvr_diag_ln_vals = {4151	.reg_pairs = sgmii_pcie_xcvr_diag_ln_regs,4152	.num_regs = ARRAY_SIZE(sgmii_pcie_xcvr_diag_ln_regs),4153};4154 4155/* SGMII 100 MHz Ref clk, no SSC */4156static const struct cdns_reg_pairs sl_sgmii_100_no_ssc_cmn_regs[] = {4157	{0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},4158	{0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},4159	{0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},4160	{0x0003, CMN_PLL0_VCOCAL_TCTRL},4161	{0x0003, CMN_PLL1_VCOCAL_TCTRL}4162};4163 4164static const struct cdns_torrent_vals sl_sgmii_100_no_ssc_cmn_vals = {4165	.reg_pairs = sl_sgmii_100_no_ssc_cmn_regs,4166	.num_regs = ARRAY_SIZE(sl_sgmii_100_no_ssc_cmn_regs),4167};4168 4169static const struct cdns_reg_pairs sgmii_100_no_ssc_cmn_regs[] = {4170	{0x007F, CMN_TXPUCAL_TUNE},4171	{0x007F, CMN_TXPDCAL_TUNE}4172};4173 4174static const struct cdns_reg_pairs sgmii_100_no_ssc_tx_ln_regs[] = {4175	{0x00F3, TX_PSC_A0},4176	{0x04A2, TX_PSC_A2},4177	{0x04A2, TX_PSC_A3},4178	{0x0000, TX_TXCC_CPOST_MULT_00},4179	{0x00B3, DRV_DIAG_TX_DRV},4180	{0x0002, XCVR_DIAG_PSC_OVRD}4181};4182 4183static const struct cdns_reg_pairs ti_sgmii_100_no_ssc_tx_ln_regs[] = {4184	{0x00F3, TX_PSC_A0},4185	{0x04A2, TX_PSC_A2},4186	{0x04A2, TX_PSC_A3},4187	{0x0000, TX_TXCC_CPOST_MULT_00},4188	{0x00B3, DRV_DIAG_TX_DRV},4189	{0x0002, XCVR_DIAG_PSC_OVRD},4190	{0x4000, XCVR_DIAG_RXCLK_CTRL}4191};4192 4193static const struct cdns_reg_pairs sgmii_100_no_ssc_rx_ln_regs[] = {4194	{0x091D, RX_PSC_A0},4195	{0x0900, RX_PSC_A2},4196	{0x0100, RX_PSC_A3},4197	{0x03C7, RX_REE_GCSM1_EQENM_PH1},4198	{0x01C7, RX_REE_GCSM1_EQENM_PH2},4199	{0x0000, RX_DIAG_DFE_CTRL},4200	{0x0019, RX_REE_TAP1_CLIP},4201	{0x0019, RX_REE_TAP2TON_CLIP},4202	{0x0098, RX_DIAG_NQST_CTRL},4203	{0x0C01, RX_DIAG_DFE_AMP_TUNE_2},4204	{0x0000, RX_DIAG_DFE_AMP_TUNE_3},4205	{0x0000, RX_DIAG_PI_CAP},4206	{0x0010, RX_DIAG_PI_RATE},4207	{0x0001, RX_DIAG_ACYA},4208	{0x018C, RX_CDRLF_CNFG},4209};4210 4211static const struct cdns_torrent_vals sgmii_100_no_ssc_cmn_vals = {4212	.reg_pairs = sgmii_100_no_ssc_cmn_regs,4213	.num_regs = ARRAY_SIZE(sgmii_100_no_ssc_cmn_regs),4214};4215 4216static const struct cdns_torrent_vals sgmii_100_no_ssc_tx_ln_vals = {4217	.reg_pairs = sgmii_100_no_ssc_tx_ln_regs,4218	.num_regs = ARRAY_SIZE(sgmii_100_no_ssc_tx_ln_regs),4219};4220 4221static const struct cdns_torrent_vals ti_sgmii_100_no_ssc_tx_ln_vals = {4222	.reg_pairs = ti_sgmii_100_no_ssc_tx_ln_regs,4223	.num_regs = ARRAY_SIZE(ti_sgmii_100_no_ssc_tx_ln_regs),4224};4225 4226static const struct cdns_torrent_vals sgmii_100_no_ssc_rx_ln_vals = {4227	.reg_pairs = sgmii_100_no_ssc_rx_ln_regs,4228	.num_regs = ARRAY_SIZE(sgmii_100_no_ssc_rx_ln_regs),4229};4230 4231/* TI J7200, multilink SGMII */4232static const struct cdns_reg_pairs j7200_sgmii_100_no_ssc_tx_ln_regs[] = {4233	{0x07A2, TX_RCVDET_ST_TMR},4234	{0x00F3, TX_PSC_A0},4235	{0x04A2, TX_PSC_A2},4236	{0x04A2, TX_PSC_A3 },4237	{0x0000, TX_TXCC_CPOST_MULT_00},4238	{0x00B3, DRV_DIAG_TX_DRV},4239	{0x0002, XCVR_DIAG_PSC_OVRD},4240	{0x4000, XCVR_DIAG_RXCLK_CTRL}4241};4242 4243static const struct cdns_torrent_vals j7200_sgmii_100_no_ssc_tx_ln_vals = {4244	.reg_pairs = j7200_sgmii_100_no_ssc_tx_ln_regs,4245	.num_regs = ARRAY_SIZE(j7200_sgmii_100_no_ssc_tx_ln_regs),4246};4247 4248static const struct cdns_reg_pairs j7200_sgmii_100_no_ssc_rx_ln_regs[] = {4249	{0x0014, RX_SDCAL0_INIT_TMR},4250	{0x0062, RX_SDCAL0_ITER_TMR},4251	{0x0014, RX_SDCAL1_INIT_TMR},4252	{0x0062, RX_SDCAL1_ITER_TMR},4253	{0x091D, RX_PSC_A0},4254	{0x0900, RX_PSC_A2},4255	{0x0100, RX_PSC_A3},4256	{0x03C7, RX_REE_GCSM1_EQENM_PH1},4257	{0x01C7, RX_REE_GCSM1_EQENM_PH2},4258	{0x0000, RX_DIAG_DFE_CTRL},4259	{0x0019, RX_REE_TAP1_CLIP},4260	{0x0019, RX_REE_TAP2TON_CLIP},4261	{0x0098, RX_DIAG_NQST_CTRL},4262	{0x0C01, RX_DIAG_DFE_AMP_TUNE_2},4263	{0x0000, RX_DIAG_DFE_AMP_TUNE_3},4264	{0x0000, RX_DIAG_PI_CAP},4265	{0x0010, RX_DIAG_PI_RATE},4266	{0x0001, RX_DIAG_ACYA},4267	{0x018C, RX_CDRLF_CNFG}4268};4269 4270static const struct cdns_torrent_vals j7200_sgmii_100_no_ssc_rx_ln_vals = {4271	.reg_pairs = j7200_sgmii_100_no_ssc_rx_ln_regs,4272	.num_regs = ARRAY_SIZE(j7200_sgmii_100_no_ssc_rx_ln_regs),4273};4274 4275/* SGMII 100 MHz Ref clk, internal SSC */4276static const struct cdns_reg_pairs sgmii_100_int_ssc_cmn_regs[] = {4277	{0x0004, CMN_PLL0_DSM_DIAG_M0},4278	{0x0004, CMN_PLL0_DSM_DIAG_M1},4279	{0x0004, CMN_PLL1_DSM_DIAG_M0},4280	{0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},4281	{0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},4282	{0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},4283	{0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},4284	{0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},4285	{0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},4286	{0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},4287	{0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},4288	{0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},4289	{0x0064, CMN_PLL0_INTDIV_M0},4290	{0x0050, CMN_PLL0_INTDIV_M1},4291	{0x0064, CMN_PLL1_INTDIV_M0},4292	{0x0002, CMN_PLL0_FRACDIVH_M0},4293	{0x0002, CMN_PLL0_FRACDIVH_M1},4294	{0x0002, CMN_PLL1_FRACDIVH_M0},4295	{0x0044, CMN_PLL0_HIGH_THR_M0},4296	{0x0036, CMN_PLL0_HIGH_THR_M1},4297	{0x0044, CMN_PLL1_HIGH_THR_M0},4298	{0x0002, CMN_PDIAG_PLL0_CTRL_M0},4299	{0x0002, CMN_PDIAG_PLL0_CTRL_M1},4300	{0x0002, CMN_PDIAG_PLL1_CTRL_M0},4301	{0x0001, CMN_PLL0_SS_CTRL1_M0},4302	{0x0001, CMN_PLL0_SS_CTRL1_M1},4303	{0x0001, CMN_PLL1_SS_CTRL1_M0},4304	{0x011B, CMN_PLL0_SS_CTRL2_M0},4305	{0x011B, CMN_PLL0_SS_CTRL2_M1},4306	{0x011B, CMN_PLL1_SS_CTRL2_M0},4307	{0x006E, CMN_PLL0_SS_CTRL3_M0},4308	{0x0058, CMN_PLL0_SS_CTRL3_M1},4309	{0x006E, CMN_PLL1_SS_CTRL3_M0},4310	{0x000E, CMN_PLL0_SS_CTRL4_M0},4311	{0x0012, CMN_PLL0_SS_CTRL4_M1},4312	{0x000E, CMN_PLL1_SS_CTRL4_M0},4313	{0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},4314	{0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},4315	{0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},4316	{0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},4317	{0x00C7, CMN_PLL0_LOCK_REFCNT_START},4318	{0x00C7, CMN_PLL1_LOCK_REFCNT_START},4319	{0x00C7, CMN_PLL0_LOCK_PLLCNT_START},4320	{0x00C7, CMN_PLL1_LOCK_PLLCNT_START},4321	{0x0005, CMN_PLL0_LOCK_PLLCNT_THR},4322	{0x0005, CMN_PLL1_LOCK_PLLCNT_THR},4323	{0x007F, CMN_TXPUCAL_TUNE},4324	{0x007F, CMN_TXPDCAL_TUNE}4325};4326 4327static const struct cdns_torrent_vals sgmii_100_int_ssc_cmn_vals = {4328	.reg_pairs = sgmii_100_int_ssc_cmn_regs,4329	.num_regs = ARRAY_SIZE(sgmii_100_int_ssc_cmn_regs),4330};4331 4332/* QSGMII 100 MHz Ref clk, no SSC */4333static const struct cdns_reg_pairs sl_qsgmii_100_no_ssc_cmn_regs[] = {4334	{0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},4335	{0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},4336	{0x000C, CMN_PLL1_DSM_FBL_OVRD_M0},4337	{0x0003, CMN_PLL0_VCOCAL_TCTRL},4338	{0x0003, CMN_PLL1_VCOCAL_TCTRL}4339};4340 4341static const struct cdns_torrent_vals sl_qsgmii_100_no_ssc_cmn_vals = {4342	.reg_pairs = sl_qsgmii_100_no_ssc_cmn_regs,4343	.num_regs = ARRAY_SIZE(sl_qsgmii_100_no_ssc_cmn_regs),4344};4345 4346static const struct cdns_reg_pairs qsgmii_100_no_ssc_cmn_regs[] = {4347	{0x007F, CMN_TXPUCAL_TUNE},4348	{0x007F, CMN_TXPDCAL_TUNE}4349};4350 4351static const struct cdns_reg_pairs qsgmii_100_no_ssc_tx_ln_regs[] = {4352	{0x00F3, TX_PSC_A0},4353	{0x04A2, TX_PSC_A2},4354	{0x04A2, TX_PSC_A3},4355	{0x0000, TX_TXCC_CPOST_MULT_00},4356	{0x0011, TX_TXCC_MGNFS_MULT_100},4357	{0x0003, DRV_DIAG_TX_DRV},4358	{0x0002, XCVR_DIAG_PSC_OVRD}4359};4360 4361static const struct cdns_reg_pairs ti_qsgmii_100_no_ssc_tx_ln_regs[] = {4362	{0x00F3, TX_PSC_A0},4363	{0x04A2, TX_PSC_A2},4364	{0x04A2, TX_PSC_A3},4365	{0x0000, TX_TXCC_CPOST_MULT_00},4366	{0x0011, TX_TXCC_MGNFS_MULT_100},4367	{0x0003, DRV_DIAG_TX_DRV},4368	{0x0002, XCVR_DIAG_PSC_OVRD},4369	{0x4000, XCVR_DIAG_RXCLK_CTRL}4370};4371 4372static const struct cdns_reg_pairs qsgmii_100_no_ssc_rx_ln_regs[] = {4373	{0x091D, RX_PSC_A0},4374	{0x0900, RX_PSC_A2},4375	{0x0100, RX_PSC_A3},4376	{0x03C7, RX_REE_GCSM1_EQENM_PH1},4377	{0x01C7, RX_REE_GCSM1_EQENM_PH2},4378	{0x0000, RX_DIAG_DFE_CTRL},4379	{0x0019, RX_REE_TAP1_CLIP},4380	{0x0019, RX_REE_TAP2TON_CLIP},4381	{0x0098, RX_DIAG_NQST_CTRL},4382	{0x0C01, RX_DIAG_DFE_AMP_TUNE_2},4383	{0x0000, RX_DIAG_DFE_AMP_TUNE_3},4384	{0x0000, RX_DIAG_PI_CAP},4385	{0x0010, RX_DIAG_PI_RATE},4386	{0x0001, RX_DIAG_ACYA},4387	{0x018C, RX_CDRLF_CNFG},4388};4389 4390static const struct cdns_torrent_vals qsgmii_100_no_ssc_cmn_vals = {4391	.reg_pairs = qsgmii_100_no_ssc_cmn_regs,4392	.num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_cmn_regs),4393};4394 4395static const struct cdns_torrent_vals qsgmii_100_no_ssc_tx_ln_vals = {4396	.reg_pairs = qsgmii_100_no_ssc_tx_ln_regs,4397	.num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_tx_ln_regs),4398};4399 4400static const struct cdns_torrent_vals ti_qsgmii_100_no_ssc_tx_ln_vals = {4401	.reg_pairs = ti_qsgmii_100_no_ssc_tx_ln_regs,4402	.num_regs = ARRAY_SIZE(ti_qsgmii_100_no_ssc_tx_ln_regs),4403};4404 4405static const struct cdns_torrent_vals qsgmii_100_no_ssc_rx_ln_vals = {4406	.reg_pairs = qsgmii_100_no_ssc_rx_ln_regs,4407	.num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_rx_ln_regs),4408};4409 4410/* TI J7200, multilink QSGMII */4411static const struct cdns_reg_pairs j7200_qsgmii_100_no_ssc_tx_ln_regs[] = {4412	{0x07A2, TX_RCVDET_ST_TMR},4413	{0x00F3, TX_PSC_A0},4414	{0x04A2, TX_PSC_A2},4415	{0x04A2, TX_PSC_A3 },4416	{0x0000, TX_TXCC_CPOST_MULT_00},4417	{0x0011, TX_TXCC_MGNFS_MULT_100},4418	{0x0003, DRV_DIAG_TX_DRV},4419	{0x0002, XCVR_DIAG_PSC_OVRD},4420	{0x4000, XCVR_DIAG_RXCLK_CTRL}4421};4422 4423static const struct cdns_torrent_vals j7200_qsgmii_100_no_ssc_tx_ln_vals = {4424	.reg_pairs = j7200_qsgmii_100_no_ssc_tx_ln_regs,4425	.num_regs = ARRAY_SIZE(j7200_qsgmii_100_no_ssc_tx_ln_regs),4426};4427 4428static const struct cdns_reg_pairs j7200_qsgmii_100_no_ssc_rx_ln_regs[] = {4429	{0x0014, RX_SDCAL0_INIT_TMR},4430	{0x0062, RX_SDCAL0_ITER_TMR},4431	{0x0014, RX_SDCAL1_INIT_TMR},4432	{0x0062, RX_SDCAL1_ITER_TMR},4433	{0x091D, RX_PSC_A0},4434	{0x0900, RX_PSC_A2},4435	{0x0100, RX_PSC_A3},4436	{0x03C7, RX_REE_GCSM1_EQENM_PH1},4437	{0x01C7, RX_REE_GCSM1_EQENM_PH2},4438	{0x0000, RX_DIAG_DFE_CTRL},4439	{0x0019, RX_REE_TAP1_CLIP},4440	{0x0019, RX_REE_TAP2TON_CLIP},4441	{0x0098, RX_DIAG_NQST_CTRL},4442	{0x0C01, RX_DIAG_DFE_AMP_TUNE_2},4443	{0x0000, RX_DIAG_DFE_AMP_TUNE_3},4444	{0x0000, RX_DIAG_PI_CAP},4445	{0x0010, RX_DIAG_PI_RATE},4446	{0x0001, RX_DIAG_ACYA},4447	{0x018C, RX_CDRLF_CNFG}4448};4449 4450static const struct cdns_torrent_vals j7200_qsgmii_100_no_ssc_rx_ln_vals = {4451	.reg_pairs = j7200_qsgmii_100_no_ssc_rx_ln_regs,4452	.num_regs = ARRAY_SIZE(j7200_qsgmii_100_no_ssc_rx_ln_regs),4453};4454 4455/* QSGMII 100 MHz Ref clk, internal SSC */4456static const struct cdns_reg_pairs qsgmii_100_int_ssc_cmn_regs[] = {4457	{0x0004, CMN_PLL0_DSM_DIAG_M0},4458	{0x0004, CMN_PLL0_DSM_DIAG_M1},4459	{0x0004, CMN_PLL1_DSM_DIAG_M0},4460	{0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},4461	{0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},4462	{0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},4463	{0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},4464	{0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},4465	{0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},4466	{0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},4467	{0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},4468	{0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},4469	{0x0064, CMN_PLL0_INTDIV_M0},4470	{0x0050, CMN_PLL0_INTDIV_M1},4471	{0x0064, CMN_PLL1_INTDIV_M0},4472	{0x0002, CMN_PLL0_FRACDIVH_M0},4473	{0x0002, CMN_PLL0_FRACDIVH_M1},4474	{0x0002, CMN_PLL1_FRACDIVH_M0},4475	{0x0044, CMN_PLL0_HIGH_THR_M0},4476	{0x0036, CMN_PLL0_HIGH_THR_M1},4477	{0x0044, CMN_PLL1_HIGH_THR_M0},4478	{0x0002, CMN_PDIAG_PLL0_CTRL_M0},4479	{0x0002, CMN_PDIAG_PLL0_CTRL_M1},4480	{0x0002, CMN_PDIAG_PLL1_CTRL_M0},4481	{0x0001, CMN_PLL0_SS_CTRL1_M0},4482	{0x0001, CMN_PLL0_SS_CTRL1_M1},4483	{0x0001, CMN_PLL1_SS_CTRL1_M0},4484	{0x011B, CMN_PLL0_SS_CTRL2_M0},4485	{0x011B, CMN_PLL0_SS_CTRL2_M1},4486	{0x011B, CMN_PLL1_SS_CTRL2_M0},4487	{0x006E, CMN_PLL0_SS_CTRL3_M0},4488	{0x0058, CMN_PLL0_SS_CTRL3_M1},4489	{0x006E, CMN_PLL1_SS_CTRL3_M0},4490	{0x000E, CMN_PLL0_SS_CTRL4_M0},4491	{0x0012, CMN_PLL0_SS_CTRL4_M1},4492	{0x000E, CMN_PLL1_SS_CTRL4_M0},4493	{0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},4494	{0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},4495	{0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},4496	{0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},4497	{0x00C7, CMN_PLL0_LOCK_REFCNT_START},4498	{0x00C7, CMN_PLL1_LOCK_REFCNT_START},4499	{0x00C7, CMN_PLL0_LOCK_PLLCNT_START},4500	{0x00C7, CMN_PLL1_LOCK_PLLCNT_START},4501	{0x0005, CMN_PLL0_LOCK_PLLCNT_THR},4502	{0x0005, CMN_PLL1_LOCK_PLLCNT_THR},4503	{0x007F, CMN_TXPUCAL_TUNE},4504	{0x007F, CMN_TXPDCAL_TUNE}4505};4506 4507static const struct cdns_torrent_vals qsgmii_100_int_ssc_cmn_vals = {4508	.reg_pairs = qsgmii_100_int_ssc_cmn_regs,4509	.num_regs = ARRAY_SIZE(qsgmii_100_int_ssc_cmn_regs),4510};4511 4512/* Single SGMII/QSGMII link configuration */4513static const struct cdns_reg_pairs sl_sgmii_link_cmn_regs[] = {4514	{0x0000, PHY_PLL_CFG},4515	{0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}4516};4517 4518static const struct cdns_reg_pairs sl_sgmii_xcvr_diag_ln_regs[] = {4519	{0x0000, XCVR_DIAG_HSCLK_SEL},4520	{0x0003, XCVR_DIAG_HSCLK_DIV},4521	{0x0013, XCVR_DIAG_PLLDRC_CTRL}4522};4523 4524static const struct cdns_torrent_vals sl_sgmii_link_cmn_vals = {4525	.reg_pairs = sl_sgmii_link_cmn_regs,4526	.num_regs = ARRAY_SIZE(sl_sgmii_link_cmn_regs),4527};4528 4529static const struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = {4530	.reg_pairs = sl_sgmii_xcvr_diag_ln_regs,4531	.num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs),4532};4533 4534/* Multi link PCIe, 100 MHz Ref clk, internal SSC */4535static const struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = {4536	{0x0004, CMN_PLL0_DSM_DIAG_M0},4537	{0x0004, CMN_PLL0_DSM_DIAG_M1},4538	{0x0004, CMN_PLL1_DSM_DIAG_M0},4539	{0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},4540	{0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},4541	{0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},4542	{0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},4543	{0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},4544	{0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},4545	{0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},4546	{0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},4547	{0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},4548	{0x0064, CMN_PLL0_INTDIV_M0},4549	{0x0050, CMN_PLL0_INTDIV_M1},4550	{0x0064, CMN_PLL1_INTDIV_M0},4551	{0x0002, CMN_PLL0_FRACDIVH_M0},4552	{0x0002, CMN_PLL0_FRACDIVH_M1},4553	{0x0002, CMN_PLL1_FRACDIVH_M0},4554	{0x0044, CMN_PLL0_HIGH_THR_M0},4555	{0x0036, CMN_PLL0_HIGH_THR_M1},4556	{0x0044, CMN_PLL1_HIGH_THR_M0},4557	{0x0002, CMN_PDIAG_PLL0_CTRL_M0},4558	{0x0002, CMN_PDIAG_PLL0_CTRL_M1},4559	{0x0002, CMN_PDIAG_PLL1_CTRL_M0},4560	{0x0001, CMN_PLL0_SS_CTRL1_M0},4561	{0x0001, CMN_PLL0_SS_CTRL1_M1},4562	{0x0001, CMN_PLL1_SS_CTRL1_M0},4563	{0x011B, CMN_PLL0_SS_CTRL2_M0},4564	{0x011B, CMN_PLL0_SS_CTRL2_M1},4565	{0x011B, CMN_PLL1_SS_CTRL2_M0},4566	{0x006E, CMN_PLL0_SS_CTRL3_M0},4567	{0x0058, CMN_PLL0_SS_CTRL3_M1},4568	{0x006E, CMN_PLL1_SS_CTRL3_M0},4569	{0x000E, CMN_PLL0_SS_CTRL4_M0},4570	{0x0012, CMN_PLL0_SS_CTRL4_M1},4571	{0x000E, CMN_PLL1_SS_CTRL4_M0},4572	{0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},4573	{0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},4574	{0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},4575	{0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},4576	{0x00C7, CMN_PLL0_LOCK_REFCNT_START},4577	{0x00C7, CMN_PLL1_LOCK_REFCNT_START},4578	{0x00C7, CMN_PLL0_LOCK_PLLCNT_START},4579	{0x00C7, CMN_PLL1_LOCK_PLLCNT_START},4580	{0x0005, CMN_PLL0_LOCK_PLLCNT_THR},4581	{0x0005, CMN_PLL1_LOCK_PLLCNT_THR}4582};4583 4584static const struct cdns_torrent_vals pcie_100_int_ssc_cmn_vals = {4585	.reg_pairs = pcie_100_int_ssc_cmn_regs,4586	.num_regs = ARRAY_SIZE(pcie_100_int_ssc_cmn_regs),4587};4588 4589/* Single link PCIe, 100 MHz Ref clk, internal SSC */4590static const struct cdns_reg_pairs sl_pcie_100_int_ssc_cmn_regs[] = {4591	{0x0004, CMN_PLL0_DSM_DIAG_M0},4592	{0x0004, CMN_PLL0_DSM_DIAG_M1},4593	{0x0004, CMN_PLL1_DSM_DIAG_M0},4594	{0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0},4595	{0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1},4596	{0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0},4597	{0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0},4598	{0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1},4599	{0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0},4600	{0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0},4601	{0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1},4602	{0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0},4603	{0x0064, CMN_PLL0_INTDIV_M0},4604	{0x0050, CMN_PLL0_INTDIV_M1},4605	{0x0050, CMN_PLL1_INTDIV_M0},4606	{0x0002, CMN_PLL0_FRACDIVH_M0},4607	{0x0002, CMN_PLL0_FRACDIVH_M1},4608	{0x0002, CMN_PLL1_FRACDIVH_M0},4609	{0x0044, CMN_PLL0_HIGH_THR_M0},4610	{0x0036, CMN_PLL0_HIGH_THR_M1},4611	{0x0036, CMN_PLL1_HIGH_THR_M0},4612	{0x0002, CMN_PDIAG_PLL0_CTRL_M0},4613	{0x0002, CMN_PDIAG_PLL0_CTRL_M1},4614	{0x0002, CMN_PDIAG_PLL1_CTRL_M0},4615	{0x0001, CMN_PLL0_SS_CTRL1_M0},4616	{0x0001, CMN_PLL0_SS_CTRL1_M1},4617	{0x0001, CMN_PLL1_SS_CTRL1_M0},4618	{0x011B, CMN_PLL0_SS_CTRL2_M0},4619	{0x011B, CMN_PLL0_SS_CTRL2_M1},4620	{0x011B, CMN_PLL1_SS_CTRL2_M0},4621	{0x006E, CMN_PLL0_SS_CTRL3_M0},4622	{0x0058, CMN_PLL0_SS_CTRL3_M1},4623	{0x0058, CMN_PLL1_SS_CTRL3_M0},4624	{0x000E, CMN_PLL0_SS_CTRL4_M0},4625	{0x0012, CMN_PLL0_SS_CTRL4_M1},4626	{0x0012, CMN_PLL1_SS_CTRL4_M0},4627	{0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START},4628	{0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START},4629	{0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START},4630	{0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START},4631	{0x00C7, CMN_PLL0_LOCK_REFCNT_START},4632	{0x00C7, CMN_PLL1_LOCK_REFCNT_START},4633	{0x00C7, CMN_PLL0_LOCK_PLLCNT_START},4634	{0x00C7, CMN_PLL1_LOCK_PLLCNT_START},4635	{0x0005, CMN_PLL0_LOCK_PLLCNT_THR},4636	{0x0005, CMN_PLL1_LOCK_PLLCNT_THR}4637};4638 4639static const struct cdns_torrent_vals sl_pcie_100_int_ssc_cmn_vals = {4640	.reg_pairs = sl_pcie_100_int_ssc_cmn_regs,4641	.num_regs = ARRAY_SIZE(sl_pcie_100_int_ssc_cmn_regs),4642};4643 4644/* PCIe, 100 MHz Ref clk, no SSC & external SSC */4645static const struct cdns_reg_pairs pcie_100_ext_no_ssc_cmn_regs[] = {4646	{0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0},4647	{0x001E, CMN_PLL1_DSM_FBH_OVRD_M0},4648	{0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}4649};4650 4651static const struct cdns_reg_pairs pcie_100_ext_no_ssc_rx_ln_regs[] = {4652	{0x0019, RX_REE_TAP1_CLIP},4653	{0x0019, RX_REE_TAP2TON_CLIP},4654	{0x0001, RX_DIAG_ACYA}4655};4656 4657static const struct cdns_torrent_vals pcie_100_no_ssc_cmn_vals = {4658	.reg_pairs = pcie_100_ext_no_ssc_cmn_regs,4659	.num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_cmn_regs),4660};4661 4662static const struct cdns_torrent_vals pcie_100_no_ssc_rx_ln_vals = {4663	.reg_pairs = pcie_100_ext_no_ssc_rx_ln_regs,4664	.num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_rx_ln_regs),4665};4666 4667static const struct cdns_torrent_vals_entry link_cmn_vals_entries[] = {4668	{CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_NONE), &sl_dp_link_cmn_vals},4669	{CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_PCIE), &pcie_dp_link_cmn_vals},4670	{CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_USB), &usb_dp_link_cmn_vals},4671 4672	{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_NONE), NULL},4673	{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_SGMII), &pcie_sgmii_link_cmn_vals},4674	{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_QSGMII), &pcie_sgmii_link_cmn_vals},4675	{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_link_cmn_vals},4676	{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_DP), &pcie_dp_link_cmn_vals},4677	{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USXGMII), &pcie_usxgmii_link_cmn_vals},4678 4679	{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_NONE), &sl_sgmii_link_cmn_vals},4680	{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_PCIE), &pcie_sgmii_link_cmn_vals},4681	{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_QSGMII), &sgmii_qsgmii_link_cmn_vals},4682	{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_USB), &usb_sgmii_link_cmn_vals},4683	{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_USXGMII), &usxgmii_sgmii_link_cmn_vals},4684 4685	{CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_NONE), &sl_sgmii_link_cmn_vals},4686	{CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_PCIE), &pcie_sgmii_link_cmn_vals},4687	{CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_SGMII), &sgmii_qsgmii_link_cmn_vals},4688	{CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_USB), &usb_sgmii_link_cmn_vals},4689	{CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_USXGMII), &usxgmii_sgmii_link_cmn_vals},4690 4691	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_NONE), &sl_usb_link_cmn_vals},4692	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE), &pcie_usb_link_cmn_vals},4693	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_SGMII), &usb_sgmii_link_cmn_vals},4694	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_QSGMII), &usb_sgmii_link_cmn_vals},4695	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_dp_link_cmn_vals},4696 4697	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_NONE), &sl_usxgmii_link_cmn_vals},4698	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_PCIE), &pcie_usxgmii_link_cmn_vals},4699	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_SGMII), &usxgmii_sgmii_link_cmn_vals},4700	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_QSGMII), &usxgmii_sgmii_link_cmn_vals},4701};4702 4703static const struct cdns_torrent_vals_entry xcvr_diag_vals_entries[] = {4704	{CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_NONE), &sl_dp_xcvr_diag_ln_vals},4705	{CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_PCIE), &dp_pcie_xcvr_diag_ln_vals},4706	{CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_USB), &dp_usb_xcvr_diag_ln_vals},4707 4708	{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_NONE), NULL},4709	{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_SGMII), &pcie_sgmii_xcvr_diag_ln_vals},4710	{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_QSGMII), &pcie_sgmii_xcvr_diag_ln_vals},4711	{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_xcvr_diag_ln_vals},4712	{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_DP), &pcie_dp_xcvr_diag_ln_vals},4713	{CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USXGMII), &pcie_usxgmii_xcvr_diag_ln_vals},4714 4715	{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_NONE), &sl_sgmii_xcvr_diag_ln_vals},4716	{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_PCIE), &sgmii_pcie_xcvr_diag_ln_vals},4717	{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_QSGMII), &sgmii_qsgmii_xcvr_diag_ln_vals},4718	{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_USB), &sgmii_usb_xcvr_diag_ln_vals},4719	{CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_USXGMII), &sgmii_usxgmii_xcvr_diag_ln_vals},4720 4721	{CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_NONE), &sl_sgmii_xcvr_diag_ln_vals},4722	{CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_PCIE), &sgmii_pcie_xcvr_diag_ln_vals},4723	{CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_SGMII), &sgmii_qsgmii_xcvr_diag_ln_vals},4724	{CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_USB), &sgmii_usb_xcvr_diag_ln_vals},4725	{CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_USXGMII), &sgmii_usxgmii_xcvr_diag_ln_vals},4726 4727	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_NONE), &sl_usb_xcvr_diag_ln_vals},4728	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE), &usb_pcie_xcvr_diag_ln_vals},4729	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_SGMII), &usb_sgmii_xcvr_diag_ln_vals},4730	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_QSGMII), &usb_sgmii_xcvr_diag_ln_vals},4731	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_dp_xcvr_diag_ln_vals},4732 4733	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_NONE), &sl_usxgmii_xcvr_diag_ln_vals},4734	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_PCIE), &usxgmii_pcie_xcvr_diag_ln_vals},4735	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_SGMII), &usxgmii_sgmii_xcvr_diag_ln_vals},4736	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_QSGMII), &usxgmii_sgmii_xcvr_diag_ln_vals},4737};4738 4739static const struct cdns_torrent_vals_entry pcs_cmn_vals_entries[] = {4740	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_NONE), &usb_phy_pcs_cmn_vals},4741	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE), &usb_phy_pcs_cmn_vals},4742	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_SGMII), &usb_phy_pcs_cmn_vals},4743	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_QSGMII), &usb_phy_pcs_cmn_vals},4744	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_phy_pcs_cmn_vals},4745};4746 4747static const struct cdns_torrent_vals_entry cmn_vals_entries[] = {4748	{CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_cmn_vals},4749	{CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_cmn_vals},4750 4751	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_cmn_vals},4752	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_cmn_vals},4753	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &sl_dp_100_no_ssc_cmn_vals},4754 4755	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), NULL},4756	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},4757	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &sl_pcie_100_int_ssc_cmn_vals},4758 4759	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals},4760	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},4761	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},4762 4763	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals},4764	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},4765	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},4766 4767	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), &pcie_100_no_ssc_cmn_vals},4768	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},4769	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},4770 4771	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},4772 4773	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sl_sgmii_100_no_ssc_cmn_vals},4774 4775	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_cmn_vals},4776	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals},4777	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &sgmii_100_int_ssc_cmn_vals},4778 4779	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_QSGMII, NO_SSC), &sl_sgmii_100_no_ssc_cmn_vals},4780 4781	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &sgmii_100_no_ssc_cmn_vals},4782	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals},4783	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals},4784 4785	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &sl_qsgmii_100_no_ssc_cmn_vals},4786 4787	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &qsgmii_100_no_ssc_cmn_vals},4788	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals},4789	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &qsgmii_100_int_ssc_cmn_vals},4790 4791	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_SGMII, NO_SSC), &sl_qsgmii_100_no_ssc_cmn_vals},4792 4793	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &qsgmii_100_no_ssc_cmn_vals},4794	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals},4795	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals},4796 4797	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &sl_usb_100_no_ssc_cmn_vals},4798	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals},4799	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals},4800 4801	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_cmn_vals},4802	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_cmn_vals},4803	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_int_ssc_cmn_vals},4804 4805	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &sl_usb_100_no_ssc_cmn_vals},4806	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals},4807	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals},4808 4809	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &sl_usb_100_no_ssc_cmn_vals},4810	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals},4811	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals},4812 4813	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_cmn_vals},4814 4815	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &sl_usxgmii_156_25_no_ssc_cmn_vals},4816 4817	/* Dual refclk */4818	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), NULL},4819 4820	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &ml_sgmii_pll1_100_no_ssc_cmn_vals},4821 4822	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &ml_sgmii_pll1_100_no_ssc_cmn_vals},4823 4824	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_pll1_156_25_no_ssc_cmn_vals},4825	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &ml_usxgmii_pll0_156_25_no_ssc_cmn_vals},4826	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &ml_usxgmii_pll0_156_25_no_ssc_cmn_vals},4827};4828 4829static const struct cdns_torrent_vals_entry cdns_tx_ln_vals_entries[] = {4830	{CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_tx_ln_vals},4831	{CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_tx_ln_vals},4832 4833	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_tx_ln_vals},4834	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_tx_ln_vals},4835	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &dp_100_no_ssc_tx_ln_vals},4836 4837	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), NULL},4838	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},4839	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL},4840 4841	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL},4842	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL},4843	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL},4844 4845	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), NULL},4846	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), NULL},4847	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), NULL},4848 4849	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), NULL},4850	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), NULL},4851	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), NULL},4852 4853	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},4854 4855	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sgmii_100_no_ssc_tx_ln_vals},4856 4857	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_tx_ln_vals},4858	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &sgmii_100_no_ssc_tx_ln_vals},4859	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &sgmii_100_no_ssc_tx_ln_vals},4860 4861	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_QSGMII, NO_SSC), &sgmii_100_no_ssc_tx_ln_vals},4862 4863	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &sgmii_100_no_ssc_tx_ln_vals},4864	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &sgmii_100_no_ssc_tx_ln_vals},4865	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &sgmii_100_no_ssc_tx_ln_vals},4866 4867	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &qsgmii_100_no_ssc_tx_ln_vals},4868 4869	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &qsgmii_100_no_ssc_tx_ln_vals},4870	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &qsgmii_100_no_ssc_tx_ln_vals},4871	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &qsgmii_100_no_ssc_tx_ln_vals},4872 4873	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_SGMII, NO_SSC), &qsgmii_100_no_ssc_tx_ln_vals},4874 4875	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &qsgmii_100_no_ssc_tx_ln_vals},4876	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &qsgmii_100_no_ssc_tx_ln_vals},4877	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &qsgmii_100_no_ssc_tx_ln_vals},4878 4879	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &usb_100_no_ssc_tx_ln_vals},4880	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},4881	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},4882 4883	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_tx_ln_vals},4884	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},4885	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},4886 4887	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals},4888	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},4889	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},4890 4891	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals},4892	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},4893	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},4894 4895	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_tx_ln_vals},4896 4897	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals},4898 4899	/* Dual refclk */4900	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), NULL},4901 4902	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &sgmii_100_no_ssc_tx_ln_vals},4903 4904	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &qsgmii_100_no_ssc_tx_ln_vals},4905 4906	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals},4907	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals},4908	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals},4909};4910 4911static const struct cdns_torrent_vals_entry cdns_rx_ln_vals_entries[] = {4912	{CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_rx_ln_vals},4913	{CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_rx_ln_vals},4914 4915	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_rx_ln_vals},4916	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_rx_ln_vals},4917	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &dp_100_no_ssc_rx_ln_vals},4918 4919	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},4920	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},4921	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},4922 4923	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},4924	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},4925	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},4926 4927	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},4928	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},4929	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},4930 4931	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},4932	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},4933	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},4934 4935	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},4936 4937	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},4938 4939	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},4940	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals},4941	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals},4942 4943	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_QSGMII, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},4944 4945	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},4946	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals},4947	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals},4948 4949	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals},4950 4951	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals},4952	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals},4953	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals},4954 4955	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_SGMII, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals},4956 4957	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals},4958	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals},4959	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals},4960 4961	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &usb_100_no_ssc_rx_ln_vals},4962	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},4963	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},4964 4965	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_rx_ln_vals},4966	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},4967	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},4968 4969	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_rx_ln_vals},4970	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},4971	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},4972 4973	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &usb_100_no_ssc_rx_ln_vals},4974	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},4975	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},4976 4977	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_rx_ln_vals},4978 4979	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_rx_ln_vals},4980 4981	/* Dual refclk */4982	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},4983 4984	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},4985 4986	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals},4987 4988	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_156_25_no_ssc_rx_ln_vals},4989	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &ml_usxgmii_156_25_no_ssc_rx_ln_vals},4990	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &ml_usxgmii_156_25_no_ssc_rx_ln_vals},4991};4992 4993static const struct cdns_torrent_data cdns_map_torrent = {4994	.block_offset_shift = 0x2,4995	.reg_offset_shift = 0x2,4996	.link_cmn_vals_tbl = {4997		.entries = link_cmn_vals_entries,4998		.num_entries = ARRAY_SIZE(link_cmn_vals_entries),4999	},5000	.xcvr_diag_vals_tbl = {5001		.entries = xcvr_diag_vals_entries,5002		.num_entries = ARRAY_SIZE(xcvr_diag_vals_entries),5003	},5004	.pcs_cmn_vals_tbl = {5005		.entries = pcs_cmn_vals_entries,5006		.num_entries = ARRAY_SIZE(pcs_cmn_vals_entries),5007	},5008	.cmn_vals_tbl = {5009		.entries = cmn_vals_entries,5010		.num_entries = ARRAY_SIZE(cmn_vals_entries),5011	},5012	.tx_ln_vals_tbl = {5013		.entries = cdns_tx_ln_vals_entries,5014		.num_entries = ARRAY_SIZE(cdns_tx_ln_vals_entries),5015	},5016	.rx_ln_vals_tbl = {5017		.entries = cdns_rx_ln_vals_entries,5018		.num_entries = ARRAY_SIZE(cdns_rx_ln_vals_entries),5019	},5020};5021 5022static const struct cdns_torrent_vals_entry j721e_phy_pma_cmn_vals_entries[] = {5023	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_NONE), &ti_usxgmii_phy_pma_cmn_vals},5024	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_PCIE), &ti_usxgmii_phy_pma_cmn_vals},5025	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_SGMII), &ti_usxgmii_phy_pma_cmn_vals},5026	{CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_QSGMII), &ti_usxgmii_phy_pma_cmn_vals},5027};5028 5029static const struct cdns_torrent_vals_entry ti_tx_ln_vals_entries[] = {5030	{CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_tx_ln_vals},5031	{CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_tx_ln_vals},5032 5033	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_tx_ln_vals},5034	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_tx_ln_vals},5035	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &dp_100_no_ssc_tx_ln_vals},5036 5037	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), NULL},5038	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},5039	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL},5040 5041	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL},5042	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL},5043	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL},5044 5045	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), NULL},5046	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), NULL},5047	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), NULL},5048 5049	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), NULL},5050	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), NULL},5051	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), NULL},5052 5053	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},5054 5055	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},5056 5057	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},5058	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},5059	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},5060 5061	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_QSGMII, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},5062 5063	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},5064	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},5065	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},5066 5067	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},5068 5069	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},5070	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},5071	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},5072 5073	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_SGMII, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},5074 5075	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},5076	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},5077	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},5078 5079	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &usb_100_no_ssc_tx_ln_vals},5080	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},5081	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},5082 5083	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_tx_ln_vals},5084	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},5085	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},5086 5087	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals},5088	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},5089	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},5090 5091	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals},5092	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},5093	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},5094 5095	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_tx_ln_vals},5096 5097	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals},5098 5099	/* Dual refclk */5100	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), NULL},5101 5102	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},5103 5104	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},5105 5106	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals},5107	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals},5108	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals},5109};5110 5111static const struct cdns_torrent_data ti_j721e_map_torrent = {5112	.block_offset_shift = 0x0,5113	.reg_offset_shift = 0x1,5114	.link_cmn_vals_tbl = {5115		.entries = link_cmn_vals_entries,5116		.num_entries = ARRAY_SIZE(link_cmn_vals_entries),5117	},5118	.xcvr_diag_vals_tbl = {5119		.entries = xcvr_diag_vals_entries,5120		.num_entries = ARRAY_SIZE(xcvr_diag_vals_entries),5121	},5122	.pcs_cmn_vals_tbl = {5123		.entries = pcs_cmn_vals_entries,5124		.num_entries = ARRAY_SIZE(pcs_cmn_vals_entries),5125	},5126	.phy_pma_cmn_vals_tbl = {5127		.entries = j721e_phy_pma_cmn_vals_entries,5128		.num_entries = ARRAY_SIZE(j721e_phy_pma_cmn_vals_entries),5129	},5130	.cmn_vals_tbl = {5131		.entries = cmn_vals_entries,5132		.num_entries = ARRAY_SIZE(cmn_vals_entries),5133	},5134	.tx_ln_vals_tbl = {5135		.entries = ti_tx_ln_vals_entries,5136		.num_entries = ARRAY_SIZE(ti_tx_ln_vals_entries),5137	},5138	.rx_ln_vals_tbl = {5139		.entries = cdns_rx_ln_vals_entries,5140		.num_entries = ARRAY_SIZE(cdns_rx_ln_vals_entries),5141	},5142};5143 5144/* TI J7200 (Torrent SD0805) */5145static const struct cdns_torrent_vals_entry ti_j7200_cmn_vals_entries[] = {5146	{CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_cmn_vals},5147	{CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_cmn_vals},5148 5149	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_cmn_vals},5150	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_cmn_vals},5151	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &sl_dp_100_no_ssc_cmn_vals},5152 5153	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), NULL},5154	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},5155	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &sl_pcie_100_int_ssc_cmn_vals},5156 5157	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals},5158	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},5159	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},5160 5161	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals},5162	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},5163	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},5164 5165	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), &pcie_100_no_ssc_cmn_vals},5166	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals},5167	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals},5168 5169	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},5170 5171	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sl_sgmii_100_no_ssc_cmn_vals},5172 5173	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_cmn_vals},5174	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals},5175	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &sgmii_100_int_ssc_cmn_vals},5176 5177	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_QSGMII, NO_SSC), &sl_sgmii_100_no_ssc_cmn_vals},5178 5179	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &sgmii_100_no_ssc_cmn_vals},5180	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals},5181	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals},5182 5183	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &sl_qsgmii_100_no_ssc_cmn_vals},5184 5185	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &qsgmii_100_no_ssc_cmn_vals},5186	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals},5187	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &qsgmii_100_int_ssc_cmn_vals},5188 5189	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_SGMII, NO_SSC), &sl_qsgmii_100_no_ssc_cmn_vals},5190 5191	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &qsgmii_100_no_ssc_cmn_vals},5192	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals},5193	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals},5194 5195	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &sl_usb_100_no_ssc_cmn_vals},5196	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals},5197	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals},5198 5199	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_cmn_vals},5200	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_cmn_vals},5201	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_int_ssc_cmn_vals},5202 5203	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &sl_usb_100_no_ssc_cmn_vals},5204	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals},5205	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals},5206 5207	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &sl_usb_100_no_ssc_cmn_vals},5208	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals},5209	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals},5210 5211	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_cmn_vals},5212 5213	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &sl_usxgmii_156_25_no_ssc_cmn_vals},5214 5215	/* Dual refclk */5216	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), NULL},5217 5218	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &j7200_ml_sgmii_pll1_100_no_ssc_cmn_vals},5219 5220	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &j7200_ml_sgmii_pll1_100_no_ssc_cmn_vals},5221 5222	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_pll1_156_25_no_ssc_cmn_vals},5223	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_vals},5224	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_vals},5225};5226 5227static const struct cdns_torrent_vals_entry ti_j7200_tx_ln_vals_entries[] = {5228	{CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_tx_ln_vals},5229	{CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_tx_ln_vals},5230 5231	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_tx_ln_vals},5232	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_tx_ln_vals},5233	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &dp_100_no_ssc_tx_ln_vals},5234 5235	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), NULL},5236	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL},5237	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL},5238 5239	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL},5240	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL},5241	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL},5242 5243	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), NULL},5244	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), NULL},5245	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), NULL},5246 5247	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), NULL},5248	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), NULL},5249	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), NULL},5250 5251	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL},5252 5253	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},5254 5255	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},5256	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},5257	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},5258 5259	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_QSGMII, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},5260 5261	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},5262	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},5263	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals},5264 5265	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},5266 5267	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},5268	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},5269	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},5270 5271	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_SGMII, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},5272 5273	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},5274	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},5275	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals},5276 5277	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &usb_100_no_ssc_tx_ln_vals},5278	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},5279	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},5280 5281	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_tx_ln_vals},5282	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},5283	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},5284 5285	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals},5286	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},5287	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},5288 5289	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals},5290	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},5291	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals},5292 5293	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_tx_ln_vals},5294 5295	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals},5296 5297	/* Dual refclk */5298	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), NULL},5299 5300	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &j7200_sgmii_100_no_ssc_tx_ln_vals},5301 5302	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &j7200_qsgmii_100_no_ssc_tx_ln_vals},5303 5304	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals},5305	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals},5306	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals},5307};5308 5309static const struct cdns_torrent_vals_entry ti_j7200_rx_ln_vals_entries[] = {5310	{CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_rx_ln_vals},5311	{CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_rx_ln_vals},5312 5313	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_rx_ln_vals},5314	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_rx_ln_vals},5315	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &dp_100_no_ssc_rx_ln_vals},5316 5317	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},5318	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},5319	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},5320 5321	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},5322	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},5323	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},5324 5325	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},5326	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},5327	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},5328 5329	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},5330	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},5331	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals},5332 5333	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},5334 5335	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},5336 5337	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},5338	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals},5339	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals},5340 5341	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_QSGMII, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},5342 5343	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals},5344	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals},5345	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals},5346 5347	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals},5348 5349	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals},5350	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals},5351	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals},5352 5353	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_SGMII, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals},5354 5355	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals},5356	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals},5357	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals},5358 5359	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &usb_100_no_ssc_rx_ln_vals},5360	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},5361	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},5362 5363	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_rx_ln_vals},5364	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},5365	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},5366 5367	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_rx_ln_vals},5368	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},5369	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},5370 5371	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &usb_100_no_ssc_rx_ln_vals},5372	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},5373	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals},5374 5375	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_rx_ln_vals},5376 5377	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_rx_ln_vals},5378 5379	/* Dual refclk */5380	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals},5381 5382	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &j7200_sgmii_100_no_ssc_rx_ln_vals},5383 5384	{CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &j7200_qsgmii_100_no_ssc_rx_ln_vals},5385 5386	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_156_25_no_ssc_rx_ln_vals},5387	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &usxgmii_156_25_no_ssc_rx_ln_vals},5388	{CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &usxgmii_156_25_no_ssc_rx_ln_vals},5389};5390 5391static const struct cdns_torrent_data ti_j7200_map_torrent = {5392	.block_offset_shift = 0x0,5393	.reg_offset_shift = 0x1,5394	.link_cmn_vals_tbl = {5395		.entries = link_cmn_vals_entries,5396		.num_entries = ARRAY_SIZE(link_cmn_vals_entries),5397	},5398	.xcvr_diag_vals_tbl = {5399		.entries = xcvr_diag_vals_entries,5400		.num_entries = ARRAY_SIZE(xcvr_diag_vals_entries),5401	},5402	.pcs_cmn_vals_tbl = {5403		.entries = pcs_cmn_vals_entries,5404		.num_entries = ARRAY_SIZE(pcs_cmn_vals_entries),5405	},5406	.phy_pma_cmn_vals_tbl = {5407		.entries = j721e_phy_pma_cmn_vals_entries,5408		.num_entries = ARRAY_SIZE(j721e_phy_pma_cmn_vals_entries),5409	},5410	.cmn_vals_tbl = {5411		.entries = ti_j7200_cmn_vals_entries,5412		.num_entries = ARRAY_SIZE(ti_j7200_cmn_vals_entries),5413	},5414	.tx_ln_vals_tbl = {5415		.entries = ti_j7200_tx_ln_vals_entries,5416		.num_entries = ARRAY_SIZE(ti_j7200_tx_ln_vals_entries),5417	},5418	.rx_ln_vals_tbl = {5419		.entries = ti_j7200_rx_ln_vals_entries,5420		.num_entries = ARRAY_SIZE(ti_j7200_rx_ln_vals_entries),5421	},5422};5423 5424static const struct of_device_id cdns_torrent_phy_of_match[] = {5425	{5426		.compatible = "cdns,torrent-phy",5427		.data = &cdns_map_torrent,5428	},5429	{5430		.compatible = "ti,j721e-serdes-10g",5431		.data = &ti_j721e_map_torrent,5432	},5433	{5434		.compatible = "ti,j7200-serdes-10g",5435		.data = &ti_j7200_map_torrent,5436	},5437	{}5438};5439MODULE_DEVICE_TABLE(of, cdns_torrent_phy_of_match);5440 5441static struct platform_driver cdns_torrent_phy_driver = {5442	.probe	= cdns_torrent_phy_probe,5443	.remove_new = cdns_torrent_phy_remove,5444	.driver = {5445		.name	= "cdns-torrent-phy",5446		.of_match_table	= cdns_torrent_phy_of_match,5447		.pm	= pm_sleep_ptr(&cdns_torrent_phy_pm_ops),5448	}5449};5450module_platform_driver(cdns_torrent_phy_driver);5451 5452MODULE_AUTHOR("Cadence Design Systems, Inc.");5453MODULE_DESCRIPTION("Cadence Torrent PHY driver");5454MODULE_LICENSE("GPL v2");5455