719 lines · c
1// SPDX-License-Identifier: GPL-2.0+2/*3 * Copyright 2020 NXP4 * Copyright 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de>5 */6 7#include <linux/bitfield.h>8#include <linux/bits.h>9#include <linux/clk.h>10#include <linux/clk-provider.h>11#include <linux/delay.h>12#include <linux/iopoll.h>13#include <linux/module.h>14#include <linux/platform_device.h>15#include <linux/pm_runtime.h>16 17#define PHY_REG_00 0x0018#define PHY_REG_01 0x0419#define PHY_REG_02 0x0820#define PHY_REG_08 0x2021#define PHY_REG_09 0x2422#define PHY_REG_10 0x2823#define PHY_REG_11 0x2c24 25#define PHY_REG_12 0x3026#define REG12_CK_DIV_MASK GENMASK(5, 4)27 28#define PHY_REG_13 0x3429#define REG13_TG_CODE_LOW_MASK GENMASK(7, 0)30 31#define PHY_REG_14 0x3832#define REG14_TOL_MASK GENMASK(7, 4)33#define REG14_RP_CODE_MASK GENMASK(3, 1)34#define REG14_TG_CODE_HIGH_MASK GENMASK(0, 0)35 36#define PHY_REG_15 0x3c37#define PHY_REG_16 0x4038#define PHY_REG_17 0x4439#define PHY_REG_18 0x4840#define PHY_REG_19 0x4c41#define PHY_REG_20 0x5042 43#define PHY_REG_21 0x5444#define REG21_SEL_TX_CK_INV BIT(7)45#define REG21_PMS_S_MASK GENMASK(3, 0)46 47#define PHY_REG_22 0x5848#define PHY_REG_23 0x5c49#define PHY_REG_24 0x6050#define PHY_REG_25 0x6451#define PHY_REG_26 0x6852#define PHY_REG_27 0x6c53#define PHY_REG_28 0x7054#define PHY_REG_29 0x7455#define PHY_REG_30 0x7856#define PHY_REG_31 0x7c57#define PHY_REG_32 0x8058 59/*60 * REG33 does not match the ref manual. According to Sandor Yu from NXP,61 * "There is a doc issue on the i.MX8MP latest RM"62 * REG33 is being used per guidance from Sandor63 */64 65#define PHY_REG_33 0x8466#define REG33_MODE_SET_DONE BIT(7)67#define REG33_FIX_DA BIT(1)68 69#define PHY_REG_34 0x8870#define REG34_PHY_READY BIT(7)71#define REG34_PLL_LOCK BIT(6)72#define REG34_PHY_CLK_READY BIT(5)73 74#define PHY_REG_35 0x8c75#define PHY_REG_36 0x9076#define PHY_REG_37 0x9477#define PHY_REG_38 0x9878#define PHY_REG_39 0x9c79#define PHY_REG_40 0xa080#define PHY_REG_41 0xa481#define PHY_REG_42 0xa882#define PHY_REG_43 0xac83#define PHY_REG_44 0xb084#define PHY_REG_45 0xb485#define PHY_REG_46 0xb886#define PHY_REG_47 0xbc87 88#define PHY_PLL_DIV_REGS_NUM 689 90struct phy_config {91 u32 pixclk;92 u8 pll_div_regs[PHY_PLL_DIV_REGS_NUM];93};94 95static const struct phy_config phy_pll_cfg[] = {96 {97 .pixclk = 22250000,98 .pll_div_regs = { 0x4b, 0xf1, 0x89, 0x88, 0x80, 0x40 },99 }, {100 .pixclk = 23750000,101 .pll_div_regs = { 0x50, 0xf1, 0x86, 0x85, 0x80, 0x40 },102 }, {103 .pixclk = 24000000,104 .pll_div_regs = { 0x50, 0xf0, 0x00, 0x00, 0x80, 0x00 },105 }, {106 .pixclk = 24024000,107 .pll_div_regs = { 0x50, 0xf1, 0x99, 0x02, 0x80, 0x40 },108 }, {109 .pixclk = 25175000,110 .pll_div_regs = { 0x54, 0xfc, 0xcc, 0x91, 0x80, 0x40 },111 }, {112 .pixclk = 25200000,113 .pll_div_regs = { 0x54, 0xf0, 0x00, 0x00, 0x80, 0x00 },114 }, {115 .pixclk = 26750000,116 .pll_div_regs = { 0x5a, 0xf2, 0x89, 0x88, 0x80, 0x40 },117 }, {118 .pixclk = 27000000,119 .pll_div_regs = { 0x5a, 0xf0, 0x00, 0x00, 0x80, 0x00 },120 }, {121 .pixclk = 27027000,122 .pll_div_regs = { 0x5a, 0xf2, 0xfd, 0x0c, 0x80, 0x40 },123 }, {124 .pixclk = 29500000,125 .pll_div_regs = { 0x62, 0xf4, 0x95, 0x08, 0x80, 0x40 },126 }, {127 .pixclk = 30750000,128 .pll_div_regs = { 0x66, 0xf4, 0x82, 0x01, 0x88, 0x45 },129 }, {130 .pixclk = 30888000,131 .pll_div_regs = { 0x66, 0xf4, 0x99, 0x18, 0x88, 0x45 },132 }, {133 .pixclk = 33750000,134 .pll_div_regs = { 0x70, 0xf4, 0x82, 0x01, 0x80, 0x40 },135 }, {136 .pixclk = 35000000,137 .pll_div_regs = { 0x58, 0xb8, 0x8b, 0x88, 0x80, 0x40 },138 }, {139 .pixclk = 36000000,140 .pll_div_regs = { 0x5a, 0xb0, 0x00, 0x00, 0x80, 0x00 },141 }, {142 .pixclk = 36036000,143 .pll_div_regs = { 0x5a, 0xb2, 0xfd, 0x0c, 0x80, 0x40 },144 }, {145 .pixclk = 40000000,146 .pll_div_regs = { 0x64, 0xb0, 0x00, 0x00, 0x80, 0x00 },147 }, {148 .pixclk = 43200000,149 .pll_div_regs = { 0x5a, 0x90, 0x00, 0x00, 0x80, 0x00 },150 }, {151 .pixclk = 43243200,152 .pll_div_regs = { 0x5a, 0x92, 0xfd, 0x0c, 0x80, 0x40 },153 }, {154 .pixclk = 44500000,155 .pll_div_regs = { 0x5c, 0x92, 0x98, 0x11, 0x84, 0x41 },156 }, {157 .pixclk = 47000000,158 .pll_div_regs = { 0x62, 0x94, 0x95, 0x82, 0x80, 0x40 },159 }, {160 .pixclk = 47500000,161 .pll_div_regs = { 0x63, 0x96, 0xa1, 0x82, 0x80, 0x40 },162 }, {163 .pixclk = 50349650,164 .pll_div_regs = { 0x54, 0x7c, 0xc3, 0x8f, 0x80, 0x40 },165 }, {166 .pixclk = 50400000,167 .pll_div_regs = { 0x54, 0x70, 0x00, 0x00, 0x80, 0x00 },168 }, {169 .pixclk = 53250000,170 .pll_div_regs = { 0x58, 0x72, 0x84, 0x03, 0x82, 0x41 },171 }, {172 .pixclk = 53500000,173 .pll_div_regs = { 0x5a, 0x72, 0x89, 0x88, 0x80, 0x40 },174 }, {175 .pixclk = 54000000,176 .pll_div_regs = { 0x5a, 0x70, 0x00, 0x00, 0x80, 0x00 },177 }, {178 .pixclk = 54054000,179 .pll_div_regs = { 0x5a, 0x72, 0xfd, 0x0c, 0x80, 0x40 },180 }, {181 .pixclk = 59000000,182 .pll_div_regs = { 0x62, 0x74, 0x95, 0x08, 0x80, 0x40 },183 }, {184 .pixclk = 59340659,185 .pll_div_regs = { 0x62, 0x74, 0xdb, 0x52, 0x88, 0x47 },186 }, {187 .pixclk = 59400000,188 .pll_div_regs = { 0x63, 0x70, 0x00, 0x00, 0x80, 0x00 },189 }, {190 .pixclk = 61500000,191 .pll_div_regs = { 0x66, 0x74, 0x82, 0x01, 0x88, 0x45 },192 }, {193 .pixclk = 63500000,194 .pll_div_regs = { 0x69, 0x74, 0x89, 0x08, 0x80, 0x40 },195 }, {196 .pixclk = 67500000,197 .pll_div_regs = { 0x54, 0x52, 0x87, 0x03, 0x80, 0x40 },198 }, {199 .pixclk = 70000000,200 .pll_div_regs = { 0x58, 0x58, 0x8b, 0x88, 0x80, 0x40 },201 }, {202 .pixclk = 72000000,203 .pll_div_regs = { 0x5a, 0x50, 0x00, 0x00, 0x80, 0x00 },204 }, {205 .pixclk = 72072000,206 .pll_div_regs = { 0x5a, 0x52, 0xfd, 0x0c, 0x80, 0x40 },207 }, {208 .pixclk = 74176000,209 .pll_div_regs = { 0x5d, 0x58, 0xdb, 0xA2, 0x88, 0x41 },210 }, {211 .pixclk = 74250000,212 .pll_div_regs = { 0x5c, 0x52, 0x90, 0x0d, 0x84, 0x41 },213 }, {214 .pixclk = 78500000,215 .pll_div_regs = { 0x62, 0x54, 0x87, 0x01, 0x80, 0x40 },216 }, {217 .pixclk = 80000000,218 .pll_div_regs = { 0x64, 0x50, 0x00, 0x00, 0x80, 0x00 },219 }, {220 .pixclk = 82000000,221 .pll_div_regs = { 0x66, 0x54, 0x82, 0x01, 0x88, 0x45 },222 }, {223 .pixclk = 82500000,224 .pll_div_regs = { 0x67, 0x54, 0x88, 0x01, 0x90, 0x49 },225 }, {226 .pixclk = 89000000,227 .pll_div_regs = { 0x70, 0x54, 0x84, 0x83, 0x80, 0x40 },228 }, {229 .pixclk = 90000000,230 .pll_div_regs = { 0x70, 0x54, 0x82, 0x01, 0x80, 0x40 },231 }, {232 .pixclk = 94000000,233 .pll_div_regs = { 0x4e, 0x32, 0xa7, 0x10, 0x80, 0x40 },234 }, {235 .pixclk = 95000000,236 .pll_div_regs = { 0x50, 0x31, 0x86, 0x85, 0x80, 0x40 },237 }, {238 .pixclk = 98901099,239 .pll_div_regs = { 0x52, 0x3a, 0xdb, 0x4c, 0x88, 0x47 },240 }, {241 .pixclk = 99000000,242 .pll_div_regs = { 0x52, 0x32, 0x82, 0x01, 0x88, 0x47 },243 }, {244 .pixclk = 100699300,245 .pll_div_regs = { 0x54, 0x3c, 0xc3, 0x8f, 0x80, 0x40 },246 }, {247 .pixclk = 100800000,248 .pll_div_regs = { 0x54, 0x30, 0x00, 0x00, 0x80, 0x00 },249 }, {250 .pixclk = 102500000,251 .pll_div_regs = { 0x55, 0x32, 0x8c, 0x05, 0x90, 0x4b },252 }, {253 .pixclk = 104750000,254 .pll_div_regs = { 0x57, 0x32, 0x98, 0x07, 0x90, 0x49 },255 }, {256 .pixclk = 106500000,257 .pll_div_regs = { 0x58, 0x32, 0x84, 0x03, 0x82, 0x41 },258 }, {259 .pixclk = 107000000,260 .pll_div_regs = { 0x5a, 0x32, 0x89, 0x88, 0x80, 0x40 },261 }, {262 .pixclk = 108000000,263 .pll_div_regs = { 0x5a, 0x30, 0x00, 0x00, 0x80, 0x00 },264 }, {265 .pixclk = 108108000,266 .pll_div_regs = { 0x5a, 0x32, 0xfd, 0x0c, 0x80, 0x40 },267 }, {268 .pixclk = 118000000,269 .pll_div_regs = { 0x62, 0x34, 0x95, 0x08, 0x80, 0x40 },270 }, {271 .pixclk = 118800000,272 .pll_div_regs = { 0x63, 0x30, 0x00, 0x00, 0x80, 0x00 },273 }, {274 .pixclk = 123000000,275 .pll_div_regs = { 0x66, 0x34, 0x82, 0x01, 0x88, 0x45 },276 }, {277 .pixclk = 127000000,278 .pll_div_regs = { 0x69, 0x34, 0x89, 0x08, 0x80, 0x40 },279 }, {280 .pixclk = 135000000,281 .pll_div_regs = { 0x70, 0x34, 0x82, 0x01, 0x80, 0x40 },282 }, {283 .pixclk = 135580000,284 .pll_div_regs = { 0x71, 0x39, 0xe9, 0x82, 0x9c, 0x5b },285 }, {286 .pixclk = 137520000,287 .pll_div_regs = { 0x72, 0x38, 0x99, 0x10, 0x85, 0x41 },288 }, {289 .pixclk = 138750000,290 .pll_div_regs = { 0x73, 0x35, 0x88, 0x05, 0x90, 0x4d },291 }, {292 .pixclk = 140000000,293 .pll_div_regs = { 0x75, 0x36, 0xa7, 0x90, 0x80, 0x40 },294 }, {295 .pixclk = 144000000,296 .pll_div_regs = { 0x78, 0x30, 0x00, 0x00, 0x80, 0x00 },297 }, {298 .pixclk = 148352000,299 .pll_div_regs = { 0x7b, 0x35, 0xdb, 0x39, 0x90, 0x45 },300 }, {301 .pixclk = 148500000,302 .pll_div_regs = { 0x7b, 0x35, 0x84, 0x03, 0x90, 0x45 },303 }, {304 .pixclk = 154000000,305 .pll_div_regs = { 0x40, 0x18, 0x83, 0x01, 0x00, 0x40 },306 }, {307 .pixclk = 157000000,308 .pll_div_regs = { 0x41, 0x11, 0xa7, 0x14, 0x80, 0x40 },309 }, {310 .pixclk = 160000000,311 .pll_div_regs = { 0x42, 0x12, 0xa1, 0x20, 0x80, 0x40 },312 }, {313 .pixclk = 162000000,314 .pll_div_regs = { 0x43, 0x18, 0x8b, 0x08, 0x96, 0x55 },315 }, {316 .pixclk = 164000000,317 .pll_div_regs = { 0x45, 0x11, 0x83, 0x82, 0x90, 0x4b },318 }, {319 .pixclk = 165000000,320 .pll_div_regs = { 0x45, 0x11, 0x84, 0x81, 0x90, 0x4b },321 }, {322 .pixclk = 180000000,323 .pll_div_regs = { 0x4b, 0x10, 0x00, 0x00, 0x80, 0x00 },324 }, {325 .pixclk = 185625000,326 .pll_div_regs = { 0x4e, 0x12, 0x9a, 0x95, 0x80, 0x40 },327 }, {328 .pixclk = 188000000,329 .pll_div_regs = { 0x4e, 0x12, 0xa7, 0x10, 0x80, 0x40 },330 }, {331 .pixclk = 198000000,332 .pll_div_regs = { 0x52, 0x12, 0x82, 0x01, 0x88, 0x47 },333 }, {334 .pixclk = 205000000,335 .pll_div_regs = { 0x55, 0x12, 0x8c, 0x05, 0x90, 0x4b },336 }, {337 .pixclk = 209500000,338 .pll_div_regs = { 0x57, 0x12, 0x98, 0x07, 0x90, 0x49 },339 }, {340 .pixclk = 213000000,341 .pll_div_regs = { 0x58, 0x12, 0x84, 0x03, 0x82, 0x41 },342 }, {343 .pixclk = 216000000,344 .pll_div_regs = { 0x5a, 0x10, 0x00, 0x00, 0x80, 0x00 },345 }, {346 .pixclk = 216216000,347 .pll_div_regs = { 0x5a, 0x12, 0xfd, 0x0c, 0x80, 0x40 },348 }, {349 .pixclk = 237600000,350 .pll_div_regs = { 0x63, 0x10, 0x00, 0x00, 0x80, 0x00 },351 }, {352 .pixclk = 254000000,353 .pll_div_regs = { 0x69, 0x14, 0x89, 0x08, 0x80, 0x40 },354 }, {355 .pixclk = 277500000,356 .pll_div_regs = { 0x73, 0x15, 0x88, 0x05, 0x90, 0x4d },357 }, {358 .pixclk = 288000000,359 .pll_div_regs = { 0x78, 0x10, 0x00, 0x00, 0x80, 0x00 },360 }, {361 .pixclk = 297000000,362 .pll_div_regs = { 0x7b, 0x15, 0x84, 0x03, 0x90, 0x45 },363 },364};365 366struct reg_settings {367 u8 reg;368 u8 val;369};370 371static const struct reg_settings common_phy_cfg[] = {372 { PHY_REG_00, 0x00 }, { PHY_REG_01, 0xd1 },373 { PHY_REG_08, 0x4f }, { PHY_REG_09, 0x30 },374 { PHY_REG_10, 0x33 }, { PHY_REG_11, 0x65 },375 /* REG12 pixclk specific */376 /* REG13 pixclk specific */377 /* REG14 pixclk specific */378 { PHY_REG_15, 0x80 }, { PHY_REG_16, 0x6c },379 { PHY_REG_17, 0xf2 }, { PHY_REG_18, 0x67 },380 { PHY_REG_19, 0x00 }, { PHY_REG_20, 0x10 },381 /* REG21 pixclk specific */382 { PHY_REG_22, 0x30 }, { PHY_REG_23, 0x32 },383 { PHY_REG_24, 0x60 }, { PHY_REG_25, 0x8f },384 { PHY_REG_26, 0x00 }, { PHY_REG_27, 0x00 },385 { PHY_REG_28, 0x08 }, { PHY_REG_29, 0x00 },386 { PHY_REG_30, 0x00 }, { PHY_REG_31, 0x00 },387 { PHY_REG_32, 0x00 }, { PHY_REG_33, 0x80 },388 { PHY_REG_34, 0x00 }, { PHY_REG_35, 0x00 },389 { PHY_REG_36, 0x00 }, { PHY_REG_37, 0x00 },390 { PHY_REG_38, 0x00 }, { PHY_REG_39, 0x00 },391 { PHY_REG_40, 0x00 }, { PHY_REG_41, 0xe0 },392 { PHY_REG_42, 0x83 }, { PHY_REG_43, 0x0f },393 { PHY_REG_44, 0x3E }, { PHY_REG_45, 0xf8 },394 { PHY_REG_46, 0x00 }, { PHY_REG_47, 0x00 }395};396 397struct fsl_samsung_hdmi_phy {398 struct device *dev;399 void __iomem *regs;400 struct clk *apbclk;401 struct clk *refclk;402 403 /* clk provider */404 struct clk_hw hw;405 const struct phy_config *cur_cfg;406};407 408static inline struct fsl_samsung_hdmi_phy *409to_fsl_samsung_hdmi_phy(struct clk_hw *hw)410{411 return container_of(hw, struct fsl_samsung_hdmi_phy, hw);412}413 414static void415fsl_samsung_hdmi_phy_configure_pixclk(struct fsl_samsung_hdmi_phy *phy,416 const struct phy_config *cfg)417{418 u8 div = 0x1;419 420 switch (cfg->pixclk) {421 case 22250000 ... 33750000:422 div = 0xf;423 break;424 case 35000000 ... 40000000:425 div = 0xb;426 break;427 case 43200000 ... 47500000:428 div = 0x9;429 break;430 case 50349650 ... 63500000:431 div = 0x7;432 break;433 case 67500000 ... 90000000:434 div = 0x5;435 break;436 case 94000000 ... 148500000:437 div = 0x3;438 break;439 case 154000000 ... 297000000:440 div = 0x1;441 break;442 }443 444 writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, div),445 phy->regs + PHY_REG_21);446}447 448static void449fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy,450 const struct phy_config *cfg)451{452 u32 pclk = cfg->pixclk;453 u32 fld_tg_code;454 u32 pclk_khz;455 u8 div = 1;456 457 switch (cfg->pixclk) {458 case 22250000 ... 47500000:459 div = 1;460 break;461 case 50349650 ... 99000000:462 div = 2;463 break;464 case 100699300 ... 198000000:465 div = 4;466 break;467 case 205000000 ... 297000000:468 div = 8;469 break;470 }471 472 writeb(FIELD_PREP(REG12_CK_DIV_MASK, ilog2(div)), phy->regs + PHY_REG_12);473 474 /*475 * Calculation for the frequency lock detector target code (fld_tg_code)476 * is based on reference manual register description of PHY_REG13477 * (13.10.3.1.14.2):478 * 1st) Calculate int_pllclk which is determinded by FLD_CK_DIV479 * 2nd) Increase resolution to avoid rounding issues480 * 3th) Do the div (256 / Freq. of int_pllclk) * 24481 * 4th) Reduce the resolution and always round up since the NXP482 * settings rounding up always too. TODO: Check if that is483 * correct.484 */485 pclk /= div;486 pclk_khz = pclk / 1000;487 fld_tg_code = 256 * 1000 * 1000 / pclk_khz * 24;488 fld_tg_code = DIV_ROUND_UP(fld_tg_code, 1000);489 490 /* FLD_TOL and FLD_RP_CODE taken from downstream driver */491 writeb(FIELD_PREP(REG13_TG_CODE_LOW_MASK, fld_tg_code),492 phy->regs + PHY_REG_13);493 writeb(FIELD_PREP(REG14_TOL_MASK, 2) |494 FIELD_PREP(REG14_RP_CODE_MASK, 2) |495 FIELD_PREP(REG14_TG_CODE_HIGH_MASK, fld_tg_code >> 8),496 phy->regs + PHY_REG_14);497}498 499static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy,500 const struct phy_config *cfg)501{502 int i, ret;503 u8 val;504 505 /* HDMI PHY init */506 writeb(REG33_FIX_DA, phy->regs + PHY_REG_33);507 508 /* common PHY registers */509 for (i = 0; i < ARRAY_SIZE(common_phy_cfg); i++)510 writeb(common_phy_cfg[i].val, phy->regs + common_phy_cfg[i].reg);511 512 /* set individual PLL registers PHY_REG2 ... PHY_REG7 */513 for (i = 0; i < PHY_PLL_DIV_REGS_NUM; i++)514 writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG_02 + i * 4);515 516 fsl_samsung_hdmi_phy_configure_pixclk(phy, cfg);517 fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg);518 519 writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG_33);520 521 ret = readb_poll_timeout(phy->regs + PHY_REG_34, val,522 val & REG34_PLL_LOCK, 50, 20000);523 if (ret)524 dev_err(phy->dev, "PLL failed to lock\n");525 526 return ret;527}528 529static unsigned long phy_clk_recalc_rate(struct clk_hw *hw,530 unsigned long parent_rate)531{532 struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw);533 534 if (!phy->cur_cfg)535 return 74250000;536 537 return phy->cur_cfg->pixclk;538}539 540static long phy_clk_round_rate(struct clk_hw *hw,541 unsigned long rate, unsigned long *parent_rate)542{543 int i;544 545 for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--)546 if (phy_pll_cfg[i].pixclk <= rate)547 return phy_pll_cfg[i].pixclk;548 549 return -EINVAL;550}551 552static int phy_clk_set_rate(struct clk_hw *hw,553 unsigned long rate, unsigned long parent_rate)554{555 struct fsl_samsung_hdmi_phy *phy = to_fsl_samsung_hdmi_phy(hw);556 int i;557 558 for (i = ARRAY_SIZE(phy_pll_cfg) - 1; i >= 0; i--)559 if (phy_pll_cfg[i].pixclk <= rate)560 break;561 562 if (i < 0)563 return -EINVAL;564 565 phy->cur_cfg = &phy_pll_cfg[i];566 567 return fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg);568}569 570static const struct clk_ops phy_clk_ops = {571 .recalc_rate = phy_clk_recalc_rate,572 .round_rate = phy_clk_round_rate,573 .set_rate = phy_clk_set_rate,574};575 576static int phy_clk_register(struct fsl_samsung_hdmi_phy *phy)577{578 struct device *dev = phy->dev;579 struct device_node *np = dev->of_node;580 struct clk_init_data init;581 const char *parent_name;582 struct clk *phyclk;583 int ret;584 585 parent_name = __clk_get_name(phy->refclk);586 587 init.parent_names = &parent_name;588 init.num_parents = 1;589 init.flags = 0;590 init.name = "hdmi_pclk";591 init.ops = &phy_clk_ops;592 593 phy->hw.init = &init;594 595 phyclk = devm_clk_register(dev, &phy->hw);596 if (IS_ERR(phyclk))597 return dev_err_probe(dev, PTR_ERR(phyclk),598 "failed to register clock\n");599 600 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, phyclk);601 if (ret)602 return dev_err_probe(dev, ret,603 "failed to register clock provider\n");604 605 return 0;606}607 608static int fsl_samsung_hdmi_phy_probe(struct platform_device *pdev)609{610 struct fsl_samsung_hdmi_phy *phy;611 int ret;612 613 phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);614 if (!phy)615 return -ENOMEM;616 617 platform_set_drvdata(pdev, phy);618 phy->dev = &pdev->dev;619 620 phy->regs = devm_platform_ioremap_resource(pdev, 0);621 if (IS_ERR(phy->regs))622 return PTR_ERR(phy->regs);623 624 phy->apbclk = devm_clk_get(phy->dev, "apb");625 if (IS_ERR(phy->apbclk))626 return dev_err_probe(phy->dev, PTR_ERR(phy->apbclk),627 "failed to get apb clk\n");628 629 phy->refclk = devm_clk_get(phy->dev, "ref");630 if (IS_ERR(phy->refclk))631 return dev_err_probe(phy->dev, PTR_ERR(phy->refclk),632 "failed to get ref clk\n");633 634 ret = clk_prepare_enable(phy->apbclk);635 if (ret) {636 dev_err(phy->dev, "failed to enable apbclk\n");637 return ret;638 }639 640 pm_runtime_get_noresume(phy->dev);641 pm_runtime_set_active(phy->dev);642 pm_runtime_enable(phy->dev);643 644 ret = phy_clk_register(phy);645 if (ret) {646 dev_err(&pdev->dev, "register clk failed\n");647 goto register_clk_failed;648 }649 650 pm_runtime_put(phy->dev);651 652 return 0;653 654register_clk_failed:655 clk_disable_unprepare(phy->apbclk);656 657 return ret;658}659 660static void fsl_samsung_hdmi_phy_remove(struct platform_device *pdev)661{662 of_clk_del_provider(pdev->dev.of_node);663}664 665static int __maybe_unused fsl_samsung_hdmi_phy_suspend(struct device *dev)666{667 struct fsl_samsung_hdmi_phy *phy = dev_get_drvdata(dev);668 669 clk_disable_unprepare(phy->apbclk);670 671 return 0;672}673 674static int __maybe_unused fsl_samsung_hdmi_phy_resume(struct device *dev)675{676 struct fsl_samsung_hdmi_phy *phy = dev_get_drvdata(dev);677 int ret = 0;678 679 ret = clk_prepare_enable(phy->apbclk);680 if (ret) {681 dev_err(phy->dev, "failed to enable apbclk\n");682 return ret;683 }684 685 if (phy->cur_cfg)686 ret = fsl_samsung_hdmi_phy_configure(phy, phy->cur_cfg);687 688 return ret;689 690}691 692static DEFINE_RUNTIME_DEV_PM_OPS(fsl_samsung_hdmi_phy_pm_ops,693 fsl_samsung_hdmi_phy_suspend,694 fsl_samsung_hdmi_phy_resume, NULL);695 696static const struct of_device_id fsl_samsung_hdmi_phy_of_match[] = {697 {698 .compatible = "fsl,imx8mp-hdmi-phy",699 }, {700 /* sentinel */701 }702};703MODULE_DEVICE_TABLE(of, fsl_samsung_hdmi_phy_of_match);704 705static struct platform_driver fsl_samsung_hdmi_phy_driver = {706 .probe = fsl_samsung_hdmi_phy_probe,707 .remove_new = fsl_samsung_hdmi_phy_remove,708 .driver = {709 .name = "fsl-samsung-hdmi-phy",710 .of_match_table = fsl_samsung_hdmi_phy_of_match,711 .pm = pm_ptr(&fsl_samsung_hdmi_phy_pm_ops),712 },713};714module_platform_driver(fsl_samsung_hdmi_phy_driver);715 716MODULE_AUTHOR("Sandor Yu <Sandor.yu@nxp.com>");717MODULE_DESCRIPTION("SAMSUNG HDMI 2.0 Transmitter PHY Driver");718MODULE_LICENSE("GPL");719