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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * Copyright (c) 2014 Linaro Ltd.4 * Copyright (c) 2014 HiSilicon Limited.5 */6 7#include <linux/delay.h>8#include <linux/io.h>9#include <linux/mfd/syscon.h>10#include <linux/module.h>11#include <linux/of.h>12#include <linux/phy/phy.h>13#include <linux/platform_device.h>14#include <linux/regmap.h>15 16#define SATA_PHY0_CTLL 0xa017#define MPLL_MULTIPLIER_SHIFT 118#define MPLL_MULTIPLIER_MASK 0xfe19#define MPLL_MULTIPLIER_50M 0x3c20#define MPLL_MULTIPLIER_100M 0x1e21#define PHY_RESET BIT(0)22#define REF_SSP_EN BIT(9)23#define SSC_EN BIT(10)24#define REF_USE_PAD BIT(23)25 26#define SATA_PORT_PHYCTL 0x17427#define SPEED_MODE_MASK 0x6f000028#define HALF_RATE_SHIFT 1629#define PHY_CONFIG_SHIFT 1830#define GEN2_EN_SHIFT 2131#define SPEED_CTRL BIT(20)32 33#define SATA_PORT_PHYCTL1 0x14834#define AMPLITUDE_MASK 0x3ffffe35#define AMPLITUDE_GEN3 0x6836#define AMPLITUDE_GEN3_SHIFT 1537#define AMPLITUDE_GEN2 0x5638#define AMPLITUDE_GEN2_SHIFT 839#define AMPLITUDE_GEN1 0x5640#define AMPLITUDE_GEN1_SHIFT 141 42#define SATA_PORT_PHYCTL2 0x14c43#define PREEMPH_MASK 0x3ffff44#define PREEMPH_GEN3 0x2045#define PREEMPH_GEN3_SHIFT 1246#define PREEMPH_GEN2 0x1547#define PREEMPH_GEN2_SHIFT 648#define PREEMPH_GEN1 0x549#define PREEMPH_GEN1_SHIFT 050 51struct hix5hd2_priv {52 void __iomem *base;53 struct regmap *peri_ctrl;54};55 56enum phy_speed_mode {57 SPEED_MODE_GEN1 = 0,58 SPEED_MODE_GEN2 = 1,59 SPEED_MODE_GEN3 = 2,60};61 62static int hix5hd2_sata_phy_init(struct phy *phy)63{64 struct hix5hd2_priv *priv = phy_get_drvdata(phy);65 u32 val, data[2];66 int ret;67 68 if (priv->peri_ctrl) {69 ret = of_property_read_u32_array(phy->dev.of_node,70 "hisilicon,power-reg",71 &data[0], 2);72 if (ret) {73 dev_err(&phy->dev, "Fail read hisilicon,power-reg\n");74 return ret;75 }76 77 regmap_update_bits(priv->peri_ctrl, data[0],78 BIT(data[1]), BIT(data[1]));79 }80 81 /* reset phy */82 val = readl_relaxed(priv->base + SATA_PHY0_CTLL);83 val &= ~(MPLL_MULTIPLIER_MASK | REF_USE_PAD);84 val |= MPLL_MULTIPLIER_50M << MPLL_MULTIPLIER_SHIFT |85 REF_SSP_EN | PHY_RESET;86 writel_relaxed(val, priv->base + SATA_PHY0_CTLL);87 msleep(20);88 val &= ~PHY_RESET;89 writel_relaxed(val, priv->base + SATA_PHY0_CTLL);90 91 val = readl_relaxed(priv->base + SATA_PORT_PHYCTL1);92 val &= ~AMPLITUDE_MASK;93 val |= AMPLITUDE_GEN3 << AMPLITUDE_GEN3_SHIFT |94 AMPLITUDE_GEN2 << AMPLITUDE_GEN2_SHIFT |95 AMPLITUDE_GEN1 << AMPLITUDE_GEN1_SHIFT;96 writel_relaxed(val, priv->base + SATA_PORT_PHYCTL1);97 98 val = readl_relaxed(priv->base + SATA_PORT_PHYCTL2);99 val &= ~PREEMPH_MASK;100 val |= PREEMPH_GEN3 << PREEMPH_GEN3_SHIFT |101 PREEMPH_GEN2 << PREEMPH_GEN2_SHIFT |102 PREEMPH_GEN1 << PREEMPH_GEN1_SHIFT;103 writel_relaxed(val, priv->base + SATA_PORT_PHYCTL2);104 105 /* ensure PHYCTRL setting takes effect */106 val = readl_relaxed(priv->base + SATA_PORT_PHYCTL);107 val &= ~SPEED_MODE_MASK;108 val |= SPEED_MODE_GEN1 << HALF_RATE_SHIFT |109 SPEED_MODE_GEN1 << PHY_CONFIG_SHIFT |110 SPEED_MODE_GEN1 << GEN2_EN_SHIFT | SPEED_CTRL;111 writel_relaxed(val, priv->base + SATA_PORT_PHYCTL);112 113 msleep(20);114 val &= ~SPEED_MODE_MASK;115 val |= SPEED_MODE_GEN3 << HALF_RATE_SHIFT |116 SPEED_MODE_GEN3 << PHY_CONFIG_SHIFT |117 SPEED_MODE_GEN3 << GEN2_EN_SHIFT | SPEED_CTRL;118 writel_relaxed(val, priv->base + SATA_PORT_PHYCTL);119 120 val &= ~(SPEED_MODE_MASK | SPEED_CTRL);121 val |= SPEED_MODE_GEN2 << HALF_RATE_SHIFT |122 SPEED_MODE_GEN2 << PHY_CONFIG_SHIFT |123 SPEED_MODE_GEN2 << GEN2_EN_SHIFT;124 writel_relaxed(val, priv->base + SATA_PORT_PHYCTL);125 126 return 0;127}128 129static const struct phy_ops hix5hd2_sata_phy_ops = {130 .init = hix5hd2_sata_phy_init,131 .owner = THIS_MODULE,132};133 134static int hix5hd2_sata_phy_probe(struct platform_device *pdev)135{136 struct phy_provider *phy_provider;137 struct device *dev = &pdev->dev;138 struct resource *res;139 struct phy *phy;140 struct hix5hd2_priv *priv;141 142 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);143 if (!priv)144 return -ENOMEM;145 146 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);147 if (!res)148 return -EINVAL;149 150 priv->base = devm_ioremap(dev, res->start, resource_size(res));151 if (!priv->base)152 return -ENOMEM;153 154 priv->peri_ctrl = syscon_regmap_lookup_by_phandle(dev->of_node,155 "hisilicon,peripheral-syscon");156 if (IS_ERR(priv->peri_ctrl))157 priv->peri_ctrl = NULL;158 159 phy = devm_phy_create(dev, NULL, &hix5hd2_sata_phy_ops);160 if (IS_ERR(phy)) {161 dev_err(dev, "failed to create PHY\n");162 return PTR_ERR(phy);163 }164 165 phy_set_drvdata(phy, priv);166 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);167 return PTR_ERR_OR_ZERO(phy_provider);168}169 170static const struct of_device_id hix5hd2_sata_phy_of_match[] = {171 {.compatible = "hisilicon,hix5hd2-sata-phy",},172 { },173};174MODULE_DEVICE_TABLE(of, hix5hd2_sata_phy_of_match);175 176static struct platform_driver hix5hd2_sata_phy_driver = {177 .probe = hix5hd2_sata_phy_probe,178 .driver = {179 .name = "hix5hd2-sata-phy",180 .of_match_table = hix5hd2_sata_phy_of_match,181 }182};183module_platform_driver(hix5hd2_sata_phy_driver);184 185MODULE_AUTHOR("Jiancheng Xue <xuejiancheng@huawei.com>");186MODULE_DESCRIPTION("HISILICON HIX5HD2 SATA PHY driver");187MODULE_ALIAS("platform:hix5hd2-sata-phy");188MODULE_LICENSE("GPL v2");189