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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (C) 2015 Linaro, Ltd.4 * Rob Herring <robh@kernel.org>5 *6 * Based on vendor driver:7 * Copyright (C) 2013 Marvell Inc.8 * Author: Chao Xie <xiechao.mail@gmail.com>9 */10 11#include <linux/delay.h>12#include <linux/slab.h>13#include <linux/of.h>14#include <linux/io.h>15#include <linux/iopoll.h>16#include <linux/err.h>17#include <linux/clk.h>18#include <linux/module.h>19#include <linux/platform_device.h>20#include <linux/phy/phy.h>21 22/* USB PXA1928 PHY mapping */23#define PHY_28NM_PLL_REG0 0x024#define PHY_28NM_PLL_REG1 0x425#define PHY_28NM_CAL_REG 0x826#define PHY_28NM_TX_REG0 0x0c27#define PHY_28NM_TX_REG1 0x1028#define PHY_28NM_RX_REG0 0x1429#define PHY_28NM_RX_REG1 0x1830#define PHY_28NM_DIG_REG0 0x1c31#define PHY_28NM_DIG_REG1 0x2032#define PHY_28NM_TEST_REG0 0x2433#define PHY_28NM_TEST_REG1 0x2834#define PHY_28NM_MOC_REG 0x2c35#define PHY_28NM_PHY_RESERVE 0x3036#define PHY_28NM_OTG_REG 0x3437#define PHY_28NM_CHRG_DET 0x3838#define PHY_28NM_CTRL_REG0 0xc439#define PHY_28NM_CTRL_REG1 0xc840#define PHY_28NM_CTRL_REG2 0xd441#define PHY_28NM_CTRL_REG3 0xdc42 43/* PHY_28NM_PLL_REG0 */44#define PHY_28NM_PLL_READY BIT(31)45 46#define PHY_28NM_PLL_SELLPFR_SHIFT 2847#define PHY_28NM_PLL_SELLPFR_MASK (0x3 << 28)48 49#define PHY_28NM_PLL_FBDIV_SHIFT 1650#define PHY_28NM_PLL_FBDIV_MASK (0x1ff << 16)51 52#define PHY_28NM_PLL_ICP_SHIFT 853#define PHY_28NM_PLL_ICP_MASK (0x7 << 8)54 55#define PHY_28NM_PLL_REFDIV_SHIFT 056#define PHY_28NM_PLL_REFDIV_MASK 0x7f57 58/* PHY_28NM_PLL_REG1 */59#define PHY_28NM_PLL_PU_BY_REG BIT(1)60 61#define PHY_28NM_PLL_PU_PLL BIT(0)62 63/* PHY_28NM_CAL_REG */64#define PHY_28NM_PLL_PLLCAL_DONE BIT(31)65 66#define PHY_28NM_PLL_IMPCAL_DONE BIT(23)67 68#define PHY_28NM_PLL_KVCO_SHIFT 1669#define PHY_28NM_PLL_KVCO_MASK (0x7 << 16)70 71#define PHY_28NM_PLL_CAL12_SHIFT 2072#define PHY_28NM_PLL_CAL12_MASK (0x3 << 20)73 74#define PHY_28NM_IMPCAL_VTH_SHIFT 875#define PHY_28NM_IMPCAL_VTH_MASK (0x7 << 8)76 77#define PHY_28NM_PLLCAL_START_SHIFT 2278#define PHY_28NM_IMPCAL_START_SHIFT 1379 80/* PHY_28NM_TX_REG0 */81#define PHY_28NM_TX_PU_BY_REG BIT(25)82 83#define PHY_28NM_TX_PU_ANA BIT(24)84 85#define PHY_28NM_TX_AMP_SHIFT 2086#define PHY_28NM_TX_AMP_MASK (0x7 << 20)87 88/* PHY_28NM_RX_REG0 */89#define PHY_28NM_RX_SQ_THRESH_SHIFT 090#define PHY_28NM_RX_SQ_THRESH_MASK (0xf << 0)91 92/* PHY_28NM_RX_REG1 */93#define PHY_28NM_RX_SQCAL_DONE BIT(31)94 95/* PHY_28NM_DIG_REG0 */96#define PHY_28NM_DIG_BITSTAFFING_ERR BIT(31)97#define PHY_28NM_DIG_SYNC_ERR BIT(30)98 99#define PHY_28NM_DIG_SQ_FILT_SHIFT 16100#define PHY_28NM_DIG_SQ_FILT_MASK (0x7 << 16)101 102#define PHY_28NM_DIG_SQ_BLK_SHIFT 12103#define PHY_28NM_DIG_SQ_BLK_MASK (0x7 << 12)104 105#define PHY_28NM_DIG_SYNC_NUM_SHIFT 0106#define PHY_28NM_DIG_SYNC_NUM_MASK (0x3 << 0)107 108#define PHY_28NM_PLL_LOCK_BYPASS BIT(7)109 110/* PHY_28NM_OTG_REG */111#define PHY_28NM_OTG_CONTROL_BY_PIN BIT(5)112#define PHY_28NM_OTG_PU_OTG BIT(4)113 114#define PHY_28NM_CHGDTC_ENABLE_SWITCH_DM_SHIFT_28 13115#define PHY_28NM_CHGDTC_ENABLE_SWITCH_DP_SHIFT_28 12116#define PHY_28NM_CHGDTC_VSRC_CHARGE_SHIFT_28 10117#define PHY_28NM_CHGDTC_VDAT_CHARGE_SHIFT_28 8118#define PHY_28NM_CHGDTC_CDP_DM_AUTO_SWITCH_SHIFT_28 7119#define PHY_28NM_CHGDTC_DP_DM_SWAP_SHIFT_28 6120#define PHY_28NM_CHGDTC_PU_CHRG_DTC_SHIFT_28 5121#define PHY_28NM_CHGDTC_PD_EN_SHIFT_28 4122#define PHY_28NM_CHGDTC_DCP_EN_SHIFT_28 3123#define PHY_28NM_CHGDTC_CDP_EN_SHIFT_28 2124#define PHY_28NM_CHGDTC_TESTMON_CHRGDTC_SHIFT_28 0125 126#define PHY_28NM_CTRL1_CHRG_DTC_OUT_SHIFT_28 4127#define PHY_28NM_CTRL1_VBUSDTC_OUT_SHIFT_28 2128 129#define PHY_28NM_CTRL3_OVERWRITE BIT(0)130#define PHY_28NM_CTRL3_VBUS_VALID BIT(4)131#define PHY_28NM_CTRL3_AVALID BIT(5)132#define PHY_28NM_CTRL3_BVALID BIT(6)133 134struct mv_usb2_phy {135 struct phy *phy;136 struct platform_device *pdev;137 void __iomem *base;138 struct clk *clk;139};140 141static int wait_for_reg(void __iomem *reg, u32 mask, u32 ms)142{143 u32 val;144 145 return readl_poll_timeout(reg, val, ((val & mask) == mask),146 1000, 1000 * ms);147}148 149static int mv_usb2_phy_28nm_init(struct phy *phy)150{151 struct mv_usb2_phy *mv_phy = phy_get_drvdata(phy);152 struct platform_device *pdev = mv_phy->pdev;153 void __iomem *base = mv_phy->base;154 u32 reg;155 int ret;156 157 clk_prepare_enable(mv_phy->clk);158 159 /* PHY_28NM_PLL_REG0 */160 reg = readl(base + PHY_28NM_PLL_REG0) &161 ~(PHY_28NM_PLL_SELLPFR_MASK | PHY_28NM_PLL_FBDIV_MASK162 | PHY_28NM_PLL_ICP_MASK | PHY_28NM_PLL_REFDIV_MASK);163 writel(reg | (0x1 << PHY_28NM_PLL_SELLPFR_SHIFT164 | 0xf0 << PHY_28NM_PLL_FBDIV_SHIFT165 | 0x3 << PHY_28NM_PLL_ICP_SHIFT166 | 0xd << PHY_28NM_PLL_REFDIV_SHIFT),167 base + PHY_28NM_PLL_REG0);168 169 /* PHY_28NM_PLL_REG1 */170 reg = readl(base + PHY_28NM_PLL_REG1);171 writel(reg | PHY_28NM_PLL_PU_PLL | PHY_28NM_PLL_PU_BY_REG,172 base + PHY_28NM_PLL_REG1);173 174 /* PHY_28NM_TX_REG0 */175 reg = readl(base + PHY_28NM_TX_REG0) & ~PHY_28NM_TX_AMP_MASK;176 writel(reg | PHY_28NM_TX_PU_BY_REG | 0x3 << PHY_28NM_TX_AMP_SHIFT |177 PHY_28NM_TX_PU_ANA,178 base + PHY_28NM_TX_REG0);179 180 /* PHY_28NM_RX_REG0 */181 reg = readl(base + PHY_28NM_RX_REG0) & ~PHY_28NM_RX_SQ_THRESH_MASK;182 writel(reg | 0xa << PHY_28NM_RX_SQ_THRESH_SHIFT,183 base + PHY_28NM_RX_REG0);184 185 /* PHY_28NM_DIG_REG0 */186 reg = readl(base + PHY_28NM_DIG_REG0) &187 ~(PHY_28NM_DIG_BITSTAFFING_ERR | PHY_28NM_DIG_SYNC_ERR |188 PHY_28NM_DIG_SQ_FILT_MASK | PHY_28NM_DIG_SQ_BLK_MASK |189 PHY_28NM_DIG_SYNC_NUM_MASK);190 writel(reg | (0x1 << PHY_28NM_DIG_SYNC_NUM_SHIFT |191 PHY_28NM_PLL_LOCK_BYPASS),192 base + PHY_28NM_DIG_REG0);193 194 /* PHY_28NM_OTG_REG */195 reg = readl(base + PHY_28NM_OTG_REG) | PHY_28NM_OTG_PU_OTG;196 writel(reg & ~PHY_28NM_OTG_CONTROL_BY_PIN, base + PHY_28NM_OTG_REG);197 198 /*199 * Calibration Timing200 * ____________________________201 * CAL START ___|202 * ____________________203 * CAL_DONE ___________|204 * | 400us |205 */206 207 /* Make sure PHY Calibration is ready */208 ret = wait_for_reg(base + PHY_28NM_CAL_REG,209 PHY_28NM_PLL_PLLCAL_DONE | PHY_28NM_PLL_IMPCAL_DONE,210 100);211 if (ret) {212 dev_warn(&pdev->dev, "USB PHY PLL calibrate not done after 100mS.");213 goto err_clk;214 }215 ret = wait_for_reg(base + PHY_28NM_RX_REG1,216 PHY_28NM_RX_SQCAL_DONE, 100);217 if (ret) {218 dev_warn(&pdev->dev, "USB PHY RX SQ calibrate not done after 100mS.");219 goto err_clk;220 }221 /* Make sure PHY PLL is ready */222 ret = wait_for_reg(base + PHY_28NM_PLL_REG0, PHY_28NM_PLL_READY, 100);223 if (ret) {224 dev_warn(&pdev->dev, "PLL_READY not set after 100mS.");225 goto err_clk;226 }227 228 return 0;229err_clk:230 clk_disable_unprepare(mv_phy->clk);231 return ret;232}233 234static int mv_usb2_phy_28nm_power_on(struct phy *phy)235{236 struct mv_usb2_phy *mv_phy = phy_get_drvdata(phy);237 void __iomem *base = mv_phy->base;238 239 writel(readl(base + PHY_28NM_CTRL_REG3) |240 (PHY_28NM_CTRL3_OVERWRITE | PHY_28NM_CTRL3_VBUS_VALID |241 PHY_28NM_CTRL3_AVALID | PHY_28NM_CTRL3_BVALID),242 base + PHY_28NM_CTRL_REG3);243 244 return 0;245}246 247static int mv_usb2_phy_28nm_power_off(struct phy *phy)248{249 struct mv_usb2_phy *mv_phy = phy_get_drvdata(phy);250 void __iomem *base = mv_phy->base;251 252 writel(readl(base + PHY_28NM_CTRL_REG3) |253 ~(PHY_28NM_CTRL3_OVERWRITE | PHY_28NM_CTRL3_VBUS_VALID254 | PHY_28NM_CTRL3_AVALID | PHY_28NM_CTRL3_BVALID),255 base + PHY_28NM_CTRL_REG3);256 257 return 0;258}259 260static int mv_usb2_phy_28nm_exit(struct phy *phy)261{262 struct mv_usb2_phy *mv_phy = phy_get_drvdata(phy);263 void __iomem *base = mv_phy->base;264 unsigned int val;265 266 val = readw(base + PHY_28NM_PLL_REG1);267 val &= ~PHY_28NM_PLL_PU_PLL;268 writew(val, base + PHY_28NM_PLL_REG1);269 270 /* power down PHY Analog part */271 val = readw(base + PHY_28NM_TX_REG0);272 val &= ~PHY_28NM_TX_PU_ANA;273 writew(val, base + PHY_28NM_TX_REG0);274 275 /* power down PHY OTG part */276 val = readw(base + PHY_28NM_OTG_REG);277 val &= ~PHY_28NM_OTG_PU_OTG;278 writew(val, base + PHY_28NM_OTG_REG);279 280 clk_disable_unprepare(mv_phy->clk);281 return 0;282}283 284static const struct phy_ops usb_ops = {285 .init = mv_usb2_phy_28nm_init,286 .power_on = mv_usb2_phy_28nm_power_on,287 .power_off = mv_usb2_phy_28nm_power_off,288 .exit = mv_usb2_phy_28nm_exit,289 .owner = THIS_MODULE,290};291 292static int mv_usb2_phy_probe(struct platform_device *pdev)293{294 struct phy_provider *phy_provider;295 struct mv_usb2_phy *mv_phy;296 297 mv_phy = devm_kzalloc(&pdev->dev, sizeof(*mv_phy), GFP_KERNEL);298 if (!mv_phy)299 return -ENOMEM;300 301 mv_phy->pdev = pdev;302 303 mv_phy->clk = devm_clk_get(&pdev->dev, NULL);304 if (IS_ERR(mv_phy->clk)) {305 dev_err(&pdev->dev, "failed to get clock.\n");306 return PTR_ERR(mv_phy->clk);307 }308 309 mv_phy->base = devm_platform_ioremap_resource(pdev, 0);310 if (IS_ERR(mv_phy->base))311 return PTR_ERR(mv_phy->base);312 313 mv_phy->phy = devm_phy_create(&pdev->dev, pdev->dev.of_node, &usb_ops);314 if (IS_ERR(mv_phy->phy))315 return PTR_ERR(mv_phy->phy);316 317 phy_set_drvdata(mv_phy->phy, mv_phy);318 319 phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);320 return PTR_ERR_OR_ZERO(phy_provider);321}322 323static const struct of_device_id mv_usbphy_dt_match[] = {324 { .compatible = "marvell,pxa1928-usb-phy", },325 {},326};327MODULE_DEVICE_TABLE(of, mv_usbphy_dt_match);328 329static struct platform_driver mv_usb2_phy_driver = {330 .probe = mv_usb2_phy_probe,331 .driver = {332 .name = "mv-usb2-phy",333 .of_match_table = mv_usbphy_dt_match,334 },335};336module_platform_driver(mv_usb2_phy_driver);337 338MODULE_AUTHOR("Rob Herring <robh@kernel.org>");339MODULE_DESCRIPTION("Marvell USB2 phy driver");340MODULE_LICENSE("GPL v2");341