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1/* SPDX-License-Identifier: GPL-2.0+2 * Microchip Sparx5 SerDes driver3 *4 * Copyright (c) 2020 Microchip Technology Inc.5 */6 7/* This file is autogenerated by cml-utils 2020-11-16 13:11:27 +0100.8 * Commit ID: 13bdf073131d8bf40c54901df6988ae4e9c8f29f9 */10 11#ifndef _SPARX5_SERDES_REGS_H_12#define _SPARX5_SERDES_REGS_H_13 14#include <linux/bitfield.h>15#include <linux/types.h>16#include <linux/bug.h>17 18enum sparx5_serdes_target {19 TARGET_SD10G_LANE = 200,20 TARGET_SD25G_LANE = 212,21 TARGET_SD6G_LANE = 233,22 TARGET_SD_CMU = 248,23 TARGET_SD_CMU_CFG = 262,24 TARGET_SD_LANE = 276,25 TARGET_SD_LANE_25G = 301,26 NUM_TARGETS = 33227};28 29#define __REG(...) __VA_ARGS__30 31/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_01 */32#define SD10G_LANE_LANE_01(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 4, 0, 1, 4)33 34#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0)35#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\36 FIELD_PREP(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)37#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\38 FIELD_GET(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)39 40#define SD10G_LANE_LANE_01_CFG_RXDET_EN BIT(4)41#define SD10G_LANE_LANE_01_CFG_RXDET_EN_SET(x)\42 FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)43#define SD10G_LANE_LANE_01_CFG_RXDET_EN_GET(x)\44 FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)45 46#define SD10G_LANE_LANE_01_CFG_RXDET_STR BIT(5)47#define SD10G_LANE_LANE_01_CFG_RXDET_STR_SET(x)\48 FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)49#define SD10G_LANE_LANE_01_CFG_RXDET_STR_GET(x)\50 FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)51 52/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_02 */53#define SD10G_LANE_LANE_02(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 8, 0, 1, 4)54 55#define SD10G_LANE_LANE_02_CFG_EN_ADV BIT(0)56#define SD10G_LANE_LANE_02_CFG_EN_ADV_SET(x)\57 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_ADV, x)58#define SD10G_LANE_LANE_02_CFG_EN_ADV_GET(x)\59 FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_ADV, x)60 61#define SD10G_LANE_LANE_02_CFG_EN_MAIN BIT(1)62#define SD10G_LANE_LANE_02_CFG_EN_MAIN_SET(x)\63 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_MAIN, x)64#define SD10G_LANE_LANE_02_CFG_EN_MAIN_GET(x)\65 FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_MAIN, x)66 67#define SD10G_LANE_LANE_02_CFG_EN_DLY BIT(2)68#define SD10G_LANE_LANE_02_CFG_EN_DLY_SET(x)\69 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY, x)70#define SD10G_LANE_LANE_02_CFG_EN_DLY_GET(x)\71 FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_DLY, x)72 73#define SD10G_LANE_LANE_02_CFG_EN_DLY2 BIT(3)74#define SD10G_LANE_LANE_02_CFG_EN_DLY2_SET(x)\75 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY2, x)76#define SD10G_LANE_LANE_02_CFG_EN_DLY2_GET(x)\77 FIELD_GET(SD10G_LANE_LANE_02_CFG_EN_DLY2, x)78 79#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0 GENMASK(7, 4)80#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_SET(x)\81 FIELD_PREP(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x)82#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_GET(x)\83 FIELD_GET(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x)84 85/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_03 */86#define SD10G_LANE_LANE_03(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 12, 0, 1, 4)87 88#define SD10G_LANE_LANE_03_CFG_TAP_MAIN BIT(0)89#define SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(x)\90 FIELD_PREP(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x)91#define SD10G_LANE_LANE_03_CFG_TAP_MAIN_GET(x)\92 FIELD_GET(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x)93 94/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_04 */95#define SD10G_LANE_LANE_04(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 16, 0, 1, 4)96 97#define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0 GENMASK(4, 0)98#define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_SET(x)\99 FIELD_PREP(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x)100#define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_GET(x)\101 FIELD_GET(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x)102 103/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_06 */104#define SD10G_LANE_LANE_06(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 24, 0, 1, 4)105 106#define SD10G_LANE_LANE_06_CFG_PD_DRIVER BIT(0)107#define SD10G_LANE_LANE_06_CFG_PD_DRIVER_SET(x)\108 FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_DRIVER, x)109#define SD10G_LANE_LANE_06_CFG_PD_DRIVER_GET(x)\110 FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_DRIVER, x)111 112#define SD10G_LANE_LANE_06_CFG_PD_CLK BIT(1)113#define SD10G_LANE_LANE_06_CFG_PD_CLK_SET(x)\114 FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_CLK, x)115#define SD10G_LANE_LANE_06_CFG_PD_CLK_GET(x)\116 FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_CLK, x)117 118#define SD10G_LANE_LANE_06_CFG_PD_CML BIT(2)119#define SD10G_LANE_LANE_06_CFG_PD_CML_SET(x)\120 FIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_CML, x)121#define SD10G_LANE_LANE_06_CFG_PD_CML_GET(x)\122 FIELD_GET(SD10G_LANE_LANE_06_CFG_PD_CML, x)123 124#define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN BIT(3)125#define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_SET(x)\126 FIELD_PREP(SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN, x)127#define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_GET(x)\128 FIELD_GET(SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN, x)129 130#define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN BIT(4)131#define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_SET(x)\132 FIELD_PREP(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN, x)133#define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_GET(x)\134 FIELD_GET(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN, x)135 136#define SD10G_LANE_LANE_06_CFG_EN_PREEMPH BIT(5)137#define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_SET(x)\138 FIELD_PREP(SD10G_LANE_LANE_06_CFG_EN_PREEMPH, x)139#define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_GET(x)\140 FIELD_GET(SD10G_LANE_LANE_06_CFG_EN_PREEMPH, x)141 142/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0B */143#define SD10G_LANE_LANE_0B(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 44, 0, 1, 4)144 145#define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0 GENMASK(3, 0)146#define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_SET(x)\147 FIELD_PREP(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0, x)148#define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_GET(x)\149 FIELD_GET(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0, x)150 151#define SD10G_LANE_LANE_0B_CFG_PD_CTLE BIT(4)152#define SD10G_LANE_LANE_0B_CFG_PD_CTLE_SET(x)\153 FIELD_PREP(SD10G_LANE_LANE_0B_CFG_PD_CTLE, x)154#define SD10G_LANE_LANE_0B_CFG_PD_CTLE_GET(x)\155 FIELD_GET(SD10G_LANE_LANE_0B_CFG_PD_CTLE, x)156 157#define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN BIT(5)158#define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_SET(x)\159 FIELD_PREP(SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN, x)160#define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_GET(x)\161 FIELD_GET(SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN, x)162 163#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE BIT(6)164#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET(x)\165 FIELD_PREP(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE, x)166#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_GET(x)\167 FIELD_GET(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE, x)168 169#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ BIT(7)170#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_SET(x)\171 FIELD_PREP(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ, x)172#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_GET(x)\173 FIELD_GET(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ, x)174 175/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0C */176#define SD10G_LANE_LANE_0C(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 48, 0, 1, 4)177 178#define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE BIT(0)179#define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_SET(x)\180 FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE, x)181#define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_GET(x)\182 FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE, x)183 184#define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ BIT(1)185#define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_SET(x)\186 FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSCAL_SQ, x)187#define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_GET(x)\188 FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSCAL_SQ, x)189 190#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE BIT(2)191#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_SET(x)\192 FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE, x)193#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_GET(x)\194 FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE, x)195 196#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ BIT(3)197#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_SET(x)\198 FIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ, x)199#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_GET(x)\200 FIELD_GET(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ, x)201 202#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE BIT(4)203#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_SET(x)\204 FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE, x)205#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_GET(x)\206 FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE, x)207 208#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ BIT(5)209#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_SET(x)\210 FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ, x)211#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_GET(x)\212 FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ, x)213 214#define SD10G_LANE_LANE_0C_CFG_PD_RX_LS BIT(6)215#define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_SET(x)\216 FIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_RX_LS, x)217#define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_GET(x)\218 FIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_RX_LS, x)219 220#define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12 BIT(7)221#define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_SET(x)\222 FIELD_PREP(SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12, x)223#define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_GET(x)\224 FIELD_GET(SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12, x)225 226/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0D */227#define SD10G_LANE_LANE_0D(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 52, 0, 1, 4)228 229#define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0 GENMASK(1, 0)230#define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_SET(x)\231 FIELD_PREP(SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0, x)232#define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_GET(x)\233 FIELD_GET(SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0, x)234 235#define SD10G_LANE_LANE_0D_CFG_EQR_BYP BIT(4)236#define SD10G_LANE_LANE_0D_CFG_EQR_BYP_SET(x)\237 FIELD_PREP(SD10G_LANE_LANE_0D_CFG_EQR_BYP, x)238#define SD10G_LANE_LANE_0D_CFG_EQR_BYP_GET(x)\239 FIELD_GET(SD10G_LANE_LANE_0D_CFG_EQR_BYP, x)240 241/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0E */242#define SD10G_LANE_LANE_0E(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 56, 0, 1, 4)243 244#define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0 GENMASK(3, 0)245#define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_SET(x)\246 FIELD_PREP(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0, x)247#define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_GET(x)\248 FIELD_GET(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0, x)249 250#define SD10G_LANE_LANE_0E_CFG_RXLB_EN BIT(4)251#define SD10G_LANE_LANE_0E_CFG_RXLB_EN_SET(x)\252 FIELD_PREP(SD10G_LANE_LANE_0E_CFG_RXLB_EN, x)253#define SD10G_LANE_LANE_0E_CFG_RXLB_EN_GET(x)\254 FIELD_GET(SD10G_LANE_LANE_0E_CFG_RXLB_EN, x)255 256#define SD10G_LANE_LANE_0E_CFG_TXLB_EN BIT(5)257#define SD10G_LANE_LANE_0E_CFG_TXLB_EN_SET(x)\258 FIELD_PREP(SD10G_LANE_LANE_0E_CFG_TXLB_EN, x)259#define SD10G_LANE_LANE_0E_CFG_TXLB_EN_GET(x)\260 FIELD_GET(SD10G_LANE_LANE_0E_CFG_TXLB_EN, x)261 262#define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN BIT(6)263#define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_SET(x)\264 FIELD_PREP(SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, x)265#define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_GET(x)\266 FIELD_GET(SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, x)267 268/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0F */269#define SD10G_LANE_LANE_0F(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 60, 0, 1, 4)270 271#define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0 GENMASK(7, 0)272#define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_SET(x)\273 FIELD_PREP(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, x)274#define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_GET(x)\275 FIELD_GET(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, x)276 277/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_13 */278#define SD10G_LANE_LANE_13(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 76, 0, 1, 4)279 280#define SD10G_LANE_LANE_13_CFG_DCDR_PD BIT(0)281#define SD10G_LANE_LANE_13_CFG_DCDR_PD_SET(x)\282 FIELD_PREP(SD10G_LANE_LANE_13_CFG_DCDR_PD, x)283#define SD10G_LANE_LANE_13_CFG_DCDR_PD_GET(x)\284 FIELD_GET(SD10G_LANE_LANE_13_CFG_DCDR_PD, x)285 286#define SD10G_LANE_LANE_13_CFG_PHID_1T BIT(1)287#define SD10G_LANE_LANE_13_CFG_PHID_1T_SET(x)\288 FIELD_PREP(SD10G_LANE_LANE_13_CFG_PHID_1T, x)289#define SD10G_LANE_LANE_13_CFG_PHID_1T_GET(x)\290 FIELD_GET(SD10G_LANE_LANE_13_CFG_PHID_1T, x)291 292#define SD10G_LANE_LANE_13_CFG_CDRCK_EN BIT(2)293#define SD10G_LANE_LANE_13_CFG_CDRCK_EN_SET(x)\294 FIELD_PREP(SD10G_LANE_LANE_13_CFG_CDRCK_EN, x)295#define SD10G_LANE_LANE_13_CFG_CDRCK_EN_GET(x)\296 FIELD_GET(SD10G_LANE_LANE_13_CFG_CDRCK_EN, x)297 298/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_14 */299#define SD10G_LANE_LANE_14(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 80, 0, 1, 4)300 301#define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0 GENMASK(7, 0)302#define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_SET(x)\303 FIELD_PREP(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, x)304#define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_GET(x)\305 FIELD_GET(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, x)306 307/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_15 */308#define SD10G_LANE_LANE_15(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 84, 0, 1, 4)309 310#define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8 GENMASK(7, 0)311#define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_SET(x)\312 FIELD_PREP(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, x)313#define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_GET(x)\314 FIELD_GET(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, x)315 316/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_16 */317#define SD10G_LANE_LANE_16(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 88, 0, 1, 4)318 319#define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16 GENMASK(7, 0)320#define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_SET(x)\321 FIELD_PREP(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, x)322#define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_GET(x)\323 FIELD_GET(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, x)324 325/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_1A */326#define SD10G_LANE_LANE_1A(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 104, 0, 1, 4)327 328#define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN BIT(0)329#define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_SET(x)\330 FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN, x)331#define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_GET(x)\332 FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN, x)333 334#define SD10G_LANE_LANE_1A_CFG_PI_EN BIT(1)335#define SD10G_LANE_LANE_1A_CFG_PI_EN_SET(x)\336 FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_EN, x)337#define SD10G_LANE_LANE_1A_CFG_PI_EN_GET(x)\338 FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_EN, x)339 340#define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN BIT(2)341#define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_SET(x)\342 FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN, x)343#define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_GET(x)\344 FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN, x)345 346#define SD10G_LANE_LANE_1A_CFG_PI_STEPS BIT(3)347#define SD10G_LANE_LANE_1A_CFG_PI_STEPS_SET(x)\348 FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_STEPS, x)349#define SD10G_LANE_LANE_1A_CFG_PI_STEPS_GET(x)\350 FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_STEPS, x)351 352#define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0 GENMASK(5, 4)353#define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_SET(x)\354 FIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, x)355#define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_GET(x)\356 FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, x)357 358/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_22 */359#define SD10G_LANE_LANE_22(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 136, 0, 1, 4)360 361#define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1 GENMASK(4, 0)362#define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_SET(x)\363 FIELD_PREP(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, x)364#define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_GET(x)\365 FIELD_GET(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, x)366 367/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_23 */368#define SD10G_LANE_LANE_23(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 140, 0, 1, 4)369 370#define SD10G_LANE_LANE_23_CFG_DFE_PD BIT(0)371#define SD10G_LANE_LANE_23_CFG_DFE_PD_SET(x)\372 FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFE_PD, x)373#define SD10G_LANE_LANE_23_CFG_DFE_PD_GET(x)\374 FIELD_GET(SD10G_LANE_LANE_23_CFG_DFE_PD, x)375 376#define SD10G_LANE_LANE_23_CFG_EN_DFEDIG BIT(1)377#define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_SET(x)\378 FIELD_PREP(SD10G_LANE_LANE_23_CFG_EN_DFEDIG, x)379#define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_GET(x)\380 FIELD_GET(SD10G_LANE_LANE_23_CFG_EN_DFEDIG, x)381 382#define SD10G_LANE_LANE_23_CFG_DFECK_EN BIT(2)383#define SD10G_LANE_LANE_23_CFG_DFECK_EN_SET(x)\384 FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFECK_EN, x)385#define SD10G_LANE_LANE_23_CFG_DFECK_EN_GET(x)\386 FIELD_GET(SD10G_LANE_LANE_23_CFG_DFECK_EN, x)387 388#define SD10G_LANE_LANE_23_CFG_ERRAMP_PD BIT(3)389#define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_SET(x)\390 FIELD_PREP(SD10G_LANE_LANE_23_CFG_ERRAMP_PD, x)391#define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_GET(x)\392 FIELD_GET(SD10G_LANE_LANE_23_CFG_ERRAMP_PD, x)393 394#define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0 GENMASK(6, 4)395#define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_SET(x)\396 FIELD_PREP(SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0, x)397#define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_GET(x)\398 FIELD_GET(SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0, x)399 400/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_24 */401#define SD10G_LANE_LANE_24(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 144, 0, 1, 4)402 403#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0 GENMASK(3, 0)404#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_SET(x)\405 FIELD_PREP(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0, x)406#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_GET(x)\407 FIELD_GET(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0, x)408 409#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0 GENMASK(7, 4)410#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_SET(x)\411 FIELD_PREP(SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0, x)412#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_GET(x)\413 FIELD_GET(SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0, x)414 415/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_26 */416#define SD10G_LANE_LANE_26(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 152, 0, 1, 4)417 418#define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0 GENMASK(7, 0)419#define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_SET(x)\420 FIELD_PREP(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, x)421#define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_GET(x)\422 FIELD_GET(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, x)423 424/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_2F */425#define SD10G_LANE_LANE_2F(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 188, 0, 1, 4)426 427#define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0 GENMASK(2, 0)428#define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_SET(x)\429 FIELD_PREP(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0, x)430#define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_GET(x)\431 FIELD_GET(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0, x)432 433#define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0 GENMASK(7, 4)434#define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_SET(x)\435 FIELD_PREP(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, x)436#define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_GET(x)\437 FIELD_GET(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, x)438 439/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_30 */440#define SD10G_LANE_LANE_30(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 192, 0, 1, 4)441 442#define SD10G_LANE_LANE_30_CFG_SUMMER_EN BIT(0)443#define SD10G_LANE_LANE_30_CFG_SUMMER_EN_SET(x)\444 FIELD_PREP(SD10G_LANE_LANE_30_CFG_SUMMER_EN, x)445#define SD10G_LANE_LANE_30_CFG_SUMMER_EN_GET(x)\446 FIELD_GET(SD10G_LANE_LANE_30_CFG_SUMMER_EN, x)447 448#define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0 GENMASK(6, 4)449#define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_SET(x)\450 FIELD_PREP(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, x)451#define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_GET(x)\452 FIELD_GET(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, x)453 454/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_31 */455#define SD10G_LANE_LANE_31(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 196, 0, 1, 4)456 457#define SD10G_LANE_LANE_31_CFG_PI_RSTN BIT(0)458#define SD10G_LANE_LANE_31_CFG_PI_RSTN_SET(x)\459 FIELD_PREP(SD10G_LANE_LANE_31_CFG_PI_RSTN, x)460#define SD10G_LANE_LANE_31_CFG_PI_RSTN_GET(x)\461 FIELD_GET(SD10G_LANE_LANE_31_CFG_PI_RSTN, x)462 463#define SD10G_LANE_LANE_31_CFG_CDR_RSTN BIT(1)464#define SD10G_LANE_LANE_31_CFG_CDR_RSTN_SET(x)\465 FIELD_PREP(SD10G_LANE_LANE_31_CFG_CDR_RSTN, x)466#define SD10G_LANE_LANE_31_CFG_CDR_RSTN_GET(x)\467 FIELD_GET(SD10G_LANE_LANE_31_CFG_CDR_RSTN, x)468 469#define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG BIT(2)470#define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_SET(x)\471 FIELD_PREP(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG, x)472#define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_GET(x)\473 FIELD_GET(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG, x)474 475#define SD10G_LANE_LANE_31_CFG_CTLE_RSTN BIT(3)476#define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_SET(x)\477 FIELD_PREP(SD10G_LANE_LANE_31_CFG_CTLE_RSTN, x)478#define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_GET(x)\479 FIELD_GET(SD10G_LANE_LANE_31_CFG_CTLE_RSTN, x)480 481#define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8 BIT(4)482#define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_SET(x)\483 FIELD_PREP(SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8, x)484#define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_GET(x)\485 FIELD_GET(SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8, x)486 487#define SD10G_LANE_LANE_31_CFG_R50_EN BIT(5)488#define SD10G_LANE_LANE_31_CFG_R50_EN_SET(x)\489 FIELD_PREP(SD10G_LANE_LANE_31_CFG_R50_EN, x)490#define SD10G_LANE_LANE_31_CFG_R50_EN_GET(x)\491 FIELD_GET(SD10G_LANE_LANE_31_CFG_R50_EN, x)492 493/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_32 */494#define SD10G_LANE_LANE_32(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 200, 0, 1, 4)495 496#define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0 GENMASK(1, 0)497#define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_SET(x)\498 FIELD_PREP(SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0, x)499#define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_GET(x)\500 FIELD_GET(SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0, x)501 502#define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0 GENMASK(5, 4)503#define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_SET(x)\504 FIELD_PREP(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, x)505#define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_GET(x)\506 FIELD_GET(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, x)507 508/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_33 */509#define SD10G_LANE_LANE_33(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 204, 0, 1, 4)510 511#define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0)512#define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\513 FIELD_PREP(SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0, x)514#define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\515 FIELD_GET(SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0, x)516 517#define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0 GENMASK(5, 4)518#define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_SET(x)\519 FIELD_PREP(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0, x)520#define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_GET(x)\521 FIELD_GET(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0, x)522 523/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_35 */524#define SD10G_LANE_LANE_35(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 212, 0, 1, 4)525 526#define SD10G_LANE_LANE_35_CFG_TXRATE_1_0 GENMASK(1, 0)527#define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_SET(x)\528 FIELD_PREP(SD10G_LANE_LANE_35_CFG_TXRATE_1_0, x)529#define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_GET(x)\530 FIELD_GET(SD10G_LANE_LANE_35_CFG_TXRATE_1_0, x)531 532#define SD10G_LANE_LANE_35_CFG_RXRATE_1_0 GENMASK(5, 4)533#define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_SET(x)\534 FIELD_PREP(SD10G_LANE_LANE_35_CFG_RXRATE_1_0, x)535#define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_GET(x)\536 FIELD_GET(SD10G_LANE_LANE_35_CFG_RXRATE_1_0, x)537 538/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_36 */539#define SD10G_LANE_LANE_36(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 216, 0, 1, 4)540 541#define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0 GENMASK(1, 0)542#define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_SET(x)\543 FIELD_PREP(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0, x)544#define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_GET(x)\545 FIELD_GET(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0, x)546 547#define SD10G_LANE_LANE_36_CFG_EID_LP BIT(4)548#define SD10G_LANE_LANE_36_CFG_EID_LP_SET(x)\549 FIELD_PREP(SD10G_LANE_LANE_36_CFG_EID_LP, x)550#define SD10G_LANE_LANE_36_CFG_EID_LP_GET(x)\551 FIELD_GET(SD10G_LANE_LANE_36_CFG_EID_LP, x)552 553#define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH BIT(5)554#define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_SET(x)\555 FIELD_PREP(SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH, x)556#define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_GET(x)\557 FIELD_GET(SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH, x)558 559#define SD10G_LANE_LANE_36_CFG_PRBS_SEL BIT(6)560#define SD10G_LANE_LANE_36_CFG_PRBS_SEL_SET(x)\561 FIELD_PREP(SD10G_LANE_LANE_36_CFG_PRBS_SEL, x)562#define SD10G_LANE_LANE_36_CFG_PRBS_SEL_GET(x)\563 FIELD_GET(SD10G_LANE_LANE_36_CFG_PRBS_SEL, x)564 565#define SD10G_LANE_LANE_36_CFG_PRBS_SETB BIT(7)566#define SD10G_LANE_LANE_36_CFG_PRBS_SETB_SET(x)\567 FIELD_PREP(SD10G_LANE_LANE_36_CFG_PRBS_SETB, x)568#define SD10G_LANE_LANE_36_CFG_PRBS_SETB_GET(x)\569 FIELD_GET(SD10G_LANE_LANE_36_CFG_PRBS_SETB, x)570 571/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_37 */572#define SD10G_LANE_LANE_37(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 220, 0, 1, 4)573 574#define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD BIT(0)575#define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_SET(x)\576 FIELD_PREP(SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD, x)577#define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_GET(x)\578 FIELD_GET(SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD, x)579 580#define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE BIT(1)581#define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_SET(x)\582 FIELD_PREP(SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE, x)583#define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_GET(x)\584 FIELD_GET(SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE, x)585 586#define SD10G_LANE_LANE_37_CFG_TXSWING_HALF BIT(2)587#define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_SET(x)\588 FIELD_PREP(SD10G_LANE_LANE_37_CFG_TXSWING_HALF, x)589#define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_GET(x)\590 FIELD_GET(SD10G_LANE_LANE_37_CFG_TXSWING_HALF, x)591 592#define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0 GENMASK(5, 4)593#define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_SET(x)\594 FIELD_PREP(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, x)595#define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_GET(x)\596 FIELD_GET(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, x)597 598/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_39 */599#define SD10G_LANE_LANE_39(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 228, 0, 1, 4)600 601#define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0 GENMASK(2, 0)602#define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_SET(x)\603 FIELD_PREP(SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0, x)604#define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_GET(x)\605 FIELD_GET(SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0, x)606 607#define SD10G_LANE_LANE_39_CFG_RX_SSC_LH BIT(4)608#define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_SET(x)\609 FIELD_PREP(SD10G_LANE_LANE_39_CFG_RX_SSC_LH, x)610#define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_GET(x)\611 FIELD_GET(SD10G_LANE_LANE_39_CFG_RX_SSC_LH, x)612 613/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3A */614#define SD10G_LANE_LANE_3A(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 232, 0, 1, 4)615 616#define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0 GENMASK(3, 0)617#define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_SET(x)\618 FIELD_PREP(SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0, x)619#define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_GET(x)\620 FIELD_GET(SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0, x)621 622#define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0 GENMASK(7, 4)623#define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_SET(x)\624 FIELD_PREP(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, x)625#define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_GET(x)\626 FIELD_GET(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, x)627 628/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3C */629#define SD10G_LANE_LANE_3C(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 240, 0, 1, 4)630 631#define SD10G_LANE_LANE_3C_CFG_DIS_ACC BIT(0)632#define SD10G_LANE_LANE_3C_CFG_DIS_ACC_SET(x)\633 FIELD_PREP(SD10G_LANE_LANE_3C_CFG_DIS_ACC, x)634#define SD10G_LANE_LANE_3C_CFG_DIS_ACC_GET(x)\635 FIELD_GET(SD10G_LANE_LANE_3C_CFG_DIS_ACC, x)636 637#define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER BIT(1)638#define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_SET(x)\639 FIELD_PREP(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, x)640#define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_GET(x)\641 FIELD_GET(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, x)642 643/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_40 */644#define SD10G_LANE_LANE_40(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 256, 0, 1, 4)645 646#define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0 GENMASK(7, 0)647#define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_SET(x)\648 FIELD_PREP(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, x)649#define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_GET(x)\650 FIELD_GET(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, x)651 652/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_41 */653#define SD10G_LANE_LANE_41(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 260, 0, 1, 4)654 655#define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8 GENMASK(7, 0)656#define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_SET(x)\657 FIELD_PREP(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, x)658#define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_GET(x)\659 FIELD_GET(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, x)660 661/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_42 */662#define SD10G_LANE_LANE_42(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 264, 0, 1, 4)663 664#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0 GENMASK(2, 0)665#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_SET(x)\666 FIELD_PREP(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0, x)667#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_GET(x)\668 FIELD_GET(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0, x)669 670#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0 GENMASK(6, 4)671#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_SET(x)\672 FIELD_PREP(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0, x)673#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_GET(x)\674 FIELD_GET(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0, x)675 676/* SD10G_LANE_TARGET:LANE_GRP_1:LANE_48 */677#define SD10G_LANE_LANE_48(t) __REG(TARGET_SD10G_LANE, t, 12, 288, 0, 1, 40, 0, 0, 1, 4)678 679#define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0 GENMASK(3, 0)680#define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_SET(x)\681 FIELD_PREP(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0, x)682#define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_GET(x)\683 FIELD_GET(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0, x)684 685#define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL BIT(4)686#define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_SET(x)\687 FIELD_PREP(SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL, x)688#define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_GET(x)\689 FIELD_GET(SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL, x)690 691#define SD10G_LANE_LANE_48_CFG_CLK_ENQ BIT(5)692#define SD10G_LANE_LANE_48_CFG_CLK_ENQ_SET(x)\693 FIELD_PREP(SD10G_LANE_LANE_48_CFG_CLK_ENQ, x)694#define SD10G_LANE_LANE_48_CFG_CLK_ENQ_GET(x)\695 FIELD_GET(SD10G_LANE_LANE_48_CFG_CLK_ENQ, x)696 697/* SD10G_LANE_TARGET:LANE_GRP_1:LANE_50 */698#define SD10G_LANE_LANE_50(t) __REG(TARGET_SD10G_LANE, t, 12, 288, 0, 1, 40, 32, 0, 1, 4)699 700#define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0 GENMASK(1, 0)701#define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_SET(x)\702 FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0, x)703#define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_GET(x)\704 FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0, x)705 706#define SD10G_LANE_LANE_50_CFG_SSC_RESETB BIT(4)707#define SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(x)\708 FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_RESETB, x)709#define SD10G_LANE_LANE_50_CFG_SSC_RESETB_GET(x)\710 FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_RESETB, x)711 712#define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL BIT(5)713#define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_SET(x)\714 FIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL, x)715#define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_GET(x)\716 FIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL, x)717 718#define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL BIT(6)719#define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_SET(x)\720 FIELD_PREP(SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL, x)721#define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_GET(x)\722 FIELD_GET(SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL, x)723 724#define SD10G_LANE_LANE_50_CFG_JT_EN BIT(7)725#define SD10G_LANE_LANE_50_CFG_JT_EN_SET(x)\726 FIELD_PREP(SD10G_LANE_LANE_50_CFG_JT_EN, x)727#define SD10G_LANE_LANE_50_CFG_JT_EN_GET(x)\728 FIELD_GET(SD10G_LANE_LANE_50_CFG_JT_EN, x)729 730/* SD10G_LANE_TARGET:LANE_GRP_2:LANE_52 */731#define SD10G_LANE_LANE_52(t) __REG(TARGET_SD10G_LANE, t, 12, 328, 0, 1, 24, 0, 0, 1, 4)732 733#define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0 GENMASK(5, 0)734#define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_SET(x)\735 FIELD_PREP(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, x)736#define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_GET(x)\737 FIELD_GET(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, x)738 739/* SD10G_LANE_TARGET:LANE_GRP_4:LANE_83 */740#define SD10G_LANE_LANE_83(t) __REG(TARGET_SD10G_LANE, t, 12, 464, 0, 1, 112, 60, 0, 1, 4)741 742#define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE BIT(0)743#define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_SET(x)\744 FIELD_PREP(SD10G_LANE_LANE_83_R_TX_BIT_REVERSE, x)745#define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_GET(x)\746 FIELD_GET(SD10G_LANE_LANE_83_R_TX_BIT_REVERSE, x)747 748#define SD10G_LANE_LANE_83_R_TX_POL_INV BIT(1)749#define SD10G_LANE_LANE_83_R_TX_POL_INV_SET(x)\750 FIELD_PREP(SD10G_LANE_LANE_83_R_TX_POL_INV, x)751#define SD10G_LANE_LANE_83_R_TX_POL_INV_GET(x)\752 FIELD_GET(SD10G_LANE_LANE_83_R_TX_POL_INV, x)753 754#define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE BIT(2)755#define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_SET(x)\756 FIELD_PREP(SD10G_LANE_LANE_83_R_RX_BIT_REVERSE, x)757#define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_GET(x)\758 FIELD_GET(SD10G_LANE_LANE_83_R_RX_BIT_REVERSE, x)759 760#define SD10G_LANE_LANE_83_R_RX_POL_INV BIT(3)761#define SD10G_LANE_LANE_83_R_RX_POL_INV_SET(x)\762 FIELD_PREP(SD10G_LANE_LANE_83_R_RX_POL_INV, x)763#define SD10G_LANE_LANE_83_R_RX_POL_INV_GET(x)\764 FIELD_GET(SD10G_LANE_LANE_83_R_RX_POL_INV, x)765 766#define SD10G_LANE_LANE_83_R_DFE_RSTN BIT(4)767#define SD10G_LANE_LANE_83_R_DFE_RSTN_SET(x)\768 FIELD_PREP(SD10G_LANE_LANE_83_R_DFE_RSTN, x)769#define SD10G_LANE_LANE_83_R_DFE_RSTN_GET(x)\770 FIELD_GET(SD10G_LANE_LANE_83_R_DFE_RSTN, x)771 772#define SD10G_LANE_LANE_83_R_CDR_RSTN BIT(5)773#define SD10G_LANE_LANE_83_R_CDR_RSTN_SET(x)\774 FIELD_PREP(SD10G_LANE_LANE_83_R_CDR_RSTN, x)775#define SD10G_LANE_LANE_83_R_CDR_RSTN_GET(x)\776 FIELD_GET(SD10G_LANE_LANE_83_R_CDR_RSTN, x)777 778#define SD10G_LANE_LANE_83_R_CTLE_RSTN BIT(6)779#define SD10G_LANE_LANE_83_R_CTLE_RSTN_SET(x)\780 FIELD_PREP(SD10G_LANE_LANE_83_R_CTLE_RSTN, x)781#define SD10G_LANE_LANE_83_R_CTLE_RSTN_GET(x)\782 FIELD_GET(SD10G_LANE_LANE_83_R_CTLE_RSTN, x)783 784/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_93 */785#define SD10G_LANE_LANE_93(t) __REG(TARGET_SD10G_LANE, t, 12, 576, 0, 1, 64, 12, 0, 1, 4)786 787#define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN BIT(0)788#define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_SET(x)\789 FIELD_PREP(SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN, x)790#define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_GET(x)\791 FIELD_GET(SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN, x)792 793#define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT BIT(1)794#define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_SET(x)\795 FIELD_PREP(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT, x)796#define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_GET(x)\797 FIELD_GET(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT, x)798 799#define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE BIT(2)800#define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_SET(x)\801 FIELD_PREP(SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE, x)802#define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_GET(x)\803 FIELD_GET(SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE, x)804 805#define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL BIT(3)806#define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_SET(x)\807 FIELD_PREP(SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL, x)808#define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_GET(x)\809 FIELD_GET(SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL, x)810 811#define SD10G_LANE_LANE_93_R_REG_MANUAL BIT(4)812#define SD10G_LANE_LANE_93_R_REG_MANUAL_SET(x)\813 FIELD_PREP(SD10G_LANE_LANE_93_R_REG_MANUAL, x)814#define SD10G_LANE_LANE_93_R_REG_MANUAL_GET(x)\815 FIELD_GET(SD10G_LANE_LANE_93_R_REG_MANUAL, x)816 817#define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT BIT(5)818#define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_SET(x)\819 FIELD_PREP(SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT, x)820#define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_GET(x)\821 FIELD_GET(SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT, x)822 823#define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT BIT(6)824#define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_SET(x)\825 FIELD_PREP(SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT, x)826#define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_GET(x)\827 FIELD_GET(SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT, x)828 829#define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT BIT(7)830#define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_SET(x)\831 FIELD_PREP(SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT, x)832#define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_GET(x)\833 FIELD_GET(SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT, x)834 835/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_94 */836#define SD10G_LANE_LANE_94(t) __REG(TARGET_SD10G_LANE, t, 12, 576, 0, 1, 64, 16, 0, 1, 4)837 838#define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0 GENMASK(2, 0)839#define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_SET(x)\840 FIELD_PREP(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0, x)841#define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_GET(x)\842 FIELD_GET(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0, x)843 844#define SD10G_LANE_LANE_94_R_ISCAN_REG BIT(4)845#define SD10G_LANE_LANE_94_R_ISCAN_REG_SET(x)\846 FIELD_PREP(SD10G_LANE_LANE_94_R_ISCAN_REG, x)847#define SD10G_LANE_LANE_94_R_ISCAN_REG_GET(x)\848 FIELD_GET(SD10G_LANE_LANE_94_R_ISCAN_REG, x)849 850#define SD10G_LANE_LANE_94_R_TXEQ_REG BIT(5)851#define SD10G_LANE_LANE_94_R_TXEQ_REG_SET(x)\852 FIELD_PREP(SD10G_LANE_LANE_94_R_TXEQ_REG, x)853#define SD10G_LANE_LANE_94_R_TXEQ_REG_GET(x)\854 FIELD_GET(SD10G_LANE_LANE_94_R_TXEQ_REG, x)855 856#define SD10G_LANE_LANE_94_R_MISC_REG BIT(6)857#define SD10G_LANE_LANE_94_R_MISC_REG_SET(x)\858 FIELD_PREP(SD10G_LANE_LANE_94_R_MISC_REG, x)859#define SD10G_LANE_LANE_94_R_MISC_REG_GET(x)\860 FIELD_GET(SD10G_LANE_LANE_94_R_MISC_REG, x)861 862#define SD10G_LANE_LANE_94_R_SWING_REG BIT(7)863#define SD10G_LANE_LANE_94_R_SWING_REG_SET(x)\864 FIELD_PREP(SD10G_LANE_LANE_94_R_SWING_REG, x)865#define SD10G_LANE_LANE_94_R_SWING_REG_GET(x)\866 FIELD_GET(SD10G_LANE_LANE_94_R_SWING_REG, x)867 868/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_9E */869#define SD10G_LANE_LANE_9E(t) __REG(TARGET_SD10G_LANE, t, 12, 576, 0, 1, 64, 56, 0, 1, 4)870 871#define SD10G_LANE_LANE_9E_R_RXEQ_REG BIT(0)872#define SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(x)\873 FIELD_PREP(SD10G_LANE_LANE_9E_R_RXEQ_REG, x)874#define SD10G_LANE_LANE_9E_R_RXEQ_REG_GET(x)\875 FIELD_GET(SD10G_LANE_LANE_9E_R_RXEQ_REG, x)876 877#define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN BIT(1)878#define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_SET(x)\879 FIELD_PREP(SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN, x)880#define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_GET(x)\881 FIELD_GET(SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN, x)882 883#define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN BIT(2)884#define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_SET(x)\885 FIELD_PREP(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, x)886#define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_GET(x)\887 FIELD_GET(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, x)888 889/* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A1 */890#define SD10G_LANE_LANE_A1(t) __REG(TARGET_SD10G_LANE, t, 12, 640, 0, 1, 128, 4, 0, 1, 4)891 892#define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0 GENMASK(1, 0)893#define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_SET(x)\894 FIELD_PREP(SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0, x)895#define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_GET(x)\896 FIELD_GET(SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0, x)897 898#define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT BIT(4)899#define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_SET(x)\900 FIELD_PREP(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT, x)901#define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_GET(x)\902 FIELD_GET(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT, x)903 904#define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT BIT(5)905#define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_SET(x)\906 FIELD_PREP(SD10G_LANE_LANE_A1_R_CDR_FROM_HWT, x)907#define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_GET(x)\908 FIELD_GET(SD10G_LANE_LANE_A1_R_CDR_FROM_HWT, x)909 910#define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT BIT(6)911#define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_SET(x)\912 FIELD_PREP(SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT, x)913#define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_GET(x)\914 FIELD_GET(SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT, x)915 916#define SD10G_LANE_LANE_A1_R_PCLK_GATING BIT(7)917#define SD10G_LANE_LANE_A1_R_PCLK_GATING_SET(x)\918 FIELD_PREP(SD10G_LANE_LANE_A1_R_PCLK_GATING, x)919#define SD10G_LANE_LANE_A1_R_PCLK_GATING_GET(x)\920 FIELD_GET(SD10G_LANE_LANE_A1_R_PCLK_GATING, x)921 922/* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A2 */923#define SD10G_LANE_LANE_A2(t) __REG(TARGET_SD10G_LANE, t, 12, 640, 0, 1, 128, 8, 0, 1, 4)924 925#define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0 GENMASK(4, 0)926#define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_SET(x)\927 FIELD_PREP(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, x)928#define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_GET(x)\929 FIELD_GET(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, x)930 931/* SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */932#define SD10G_LANE_LANE_DF(t) __REG(TARGET_SD10G_LANE, t, 12, 832, 0, 1, 84, 60, 0, 1, 4)933 934#define SD10G_LANE_LANE_DF_LOL_UDL BIT(0)935#define SD10G_LANE_LANE_DF_LOL_UDL_SET(x)\936 FIELD_PREP(SD10G_LANE_LANE_DF_LOL_UDL, x)937#define SD10G_LANE_LANE_DF_LOL_UDL_GET(x)\938 FIELD_GET(SD10G_LANE_LANE_DF_LOL_UDL, x)939 940#define SD10G_LANE_LANE_DF_LOL BIT(1)941#define SD10G_LANE_LANE_DF_LOL_SET(x)\942 FIELD_PREP(SD10G_LANE_LANE_DF_LOL, x)943#define SD10G_LANE_LANE_DF_LOL_GET(x)\944 FIELD_GET(SD10G_LANE_LANE_DF_LOL, x)945 946#define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED BIT(2)947#define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_SET(x)\948 FIELD_PREP(SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)949#define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(x)\950 FIELD_GET(SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)951 952#define SD10G_LANE_LANE_DF_SQUELCH BIT(3)953#define SD10G_LANE_LANE_DF_SQUELCH_SET(x)\954 FIELD_PREP(SD10G_LANE_LANE_DF_SQUELCH, x)955#define SD10G_LANE_LANE_DF_SQUELCH_GET(x)\956 FIELD_GET(SD10G_LANE_LANE_DF_SQUELCH, x)957 958/* SD25G_TARGET:CMU_GRP_0:CMU_09 */959#define SD25G_LANE_CMU_09(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 36, 0, 1, 4)960 961#define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN BIT(0)962#define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_SET(x)\963 FIELD_PREP(SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN, x)964#define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_GET(x)\965 FIELD_GET(SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN, x)966 967#define SD25G_LANE_CMU_09_CFG_EN_DUMMY BIT(1)968#define SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(x)\969 FIELD_PREP(SD25G_LANE_CMU_09_CFG_EN_DUMMY, x)970#define SD25G_LANE_CMU_09_CFG_EN_DUMMY_GET(x)\971 FIELD_GET(SD25G_LANE_CMU_09_CFG_EN_DUMMY, x)972 973#define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET BIT(2)974#define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_SET(x)\975 FIELD_PREP(SD25G_LANE_CMU_09_CFG_PLL_LOS_SET, x)976#define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_GET(x)\977 FIELD_GET(SD25G_LANE_CMU_09_CFG_PLL_LOS_SET, x)978 979#define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD BIT(3)980#define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_SET(x)\981 FIELD_PREP(SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD, x)982#define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_GET(x)\983 FIELD_GET(SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD, x)984 985#define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0 GENMASK(5, 4)986#define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_SET(x)\987 FIELD_PREP(SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0, x)988#define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_GET(x)\989 FIELD_GET(SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0, x)990 991/* SD25G_TARGET:CMU_GRP_0:CMU_0B */992#define SD25G_LANE_CMU_0B(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 44, 0, 1, 4)993 994#define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT BIT(0)995#define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_SET(x)\996 FIELD_PREP(SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT, x)997#define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_GET(x)\998 FIELD_GET(SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT, x)999 1000#define SD25G_LANE_CMU_0B_CFG_DISLOL BIT(1)1001#define SD25G_LANE_CMU_0B_CFG_DISLOL_SET(x)\1002 FIELD_PREP(SD25G_LANE_CMU_0B_CFG_DISLOL, x)1003#define SD25G_LANE_CMU_0B_CFG_DISLOL_GET(x)\1004 FIELD_GET(SD25G_LANE_CMU_0B_CFG_DISLOL, x)1005 1006#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN BIT(2)1007#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN_SET(x)\1008 FIELD_PREP(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN, x)1009#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN_GET(x)\1010 FIELD_GET(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN, x)1011 1012#define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN BIT(3)1013#define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(x)\1014 FIELD_PREP(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN, x)1015#define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_GET(x)\1016 FIELD_GET(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN, x)1017 1018#define SD25G_LANE_CMU_0B_CFG_VFILT2PAD BIT(4)1019#define SD25G_LANE_CMU_0B_CFG_VFILT2PAD_SET(x)\1020 FIELD_PREP(SD25G_LANE_CMU_0B_CFG_VFILT2PAD, x)1021#define SD25G_LANE_CMU_0B_CFG_VFILT2PAD_GET(x)\1022 FIELD_GET(SD25G_LANE_CMU_0B_CFG_VFILT2PAD, x)1023 1024#define SD25G_LANE_CMU_0B_CFG_DISLOS BIT(5)1025#define SD25G_LANE_CMU_0B_CFG_DISLOS_SET(x)\1026 FIELD_PREP(SD25G_LANE_CMU_0B_CFG_DISLOS, x)1027#define SD25G_LANE_CMU_0B_CFG_DISLOS_GET(x)\1028 FIELD_GET(SD25G_LANE_CMU_0B_CFG_DISLOS, x)1029 1030#define SD25G_LANE_CMU_0B_CFG_DCLOL BIT(6)1031#define SD25G_LANE_CMU_0B_CFG_DCLOL_SET(x)\1032 FIELD_PREP(SD25G_LANE_CMU_0B_CFG_DCLOL, x)1033#define SD25G_LANE_CMU_0B_CFG_DCLOL_GET(x)\1034 FIELD_GET(SD25G_LANE_CMU_0B_CFG_DCLOL, x)1035 1036#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN BIT(7)1037#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_SET(x)\1038 FIELD_PREP(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN, x)1039#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_GET(x)\1040 FIELD_GET(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN, x)1041 1042/* SD25G_TARGET:CMU_GRP_0:CMU_0C */1043#define SD25G_LANE_CMU_0C(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 48, 0, 1, 4)1044 1045#define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET BIT(0)1046#define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(x)\1047 FIELD_PREP(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET, x)1048#define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_GET(x)\1049 FIELD_GET(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET, x)1050 1051#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN BIT(1)1052#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN_SET(x)\1053 FIELD_PREP(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN, x)1054#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN_GET(x)\1055 FIELD_GET(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN, x)1056 1057#define SD25G_LANE_CMU_0C_CFG_VCO_PD BIT(2)1058#define SD25G_LANE_CMU_0C_CFG_VCO_PD_SET(x)\1059 FIELD_PREP(SD25G_LANE_CMU_0C_CFG_VCO_PD, x)1060#define SD25G_LANE_CMU_0C_CFG_VCO_PD_GET(x)\1061 FIELD_GET(SD25G_LANE_CMU_0C_CFG_VCO_PD, x)1062 1063#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP BIT(3)1064#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP_SET(x)\1065 FIELD_PREP(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP, x)1066#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP_GET(x)\1067 FIELD_GET(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP, x)1068 1069#define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0 GENMASK(5, 4)1070#define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_SET(x)\1071 FIELD_PREP(SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0, x)1072#define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_GET(x)\1073 FIELD_GET(SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0, x)1074 1075/* SD25G_TARGET:CMU_GRP_0:CMU_0D */1076#define SD25G_LANE_CMU_0D(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 52, 0, 1, 4)1077 1078#define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD BIT(0)1079#define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_SET(x)\1080 FIELD_PREP(SD25G_LANE_CMU_0D_CFG_CK_TREE_PD, x)1081#define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_GET(x)\1082 FIELD_GET(SD25G_LANE_CMU_0D_CFG_CK_TREE_PD, x)1083 1084#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN BIT(1)1085#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN_SET(x)\1086 FIELD_PREP(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN, x)1087#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN_GET(x)\1088 FIELD_GET(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN, x)1089 1090#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP BIT(2)1091#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP_SET(x)\1092 FIELD_PREP(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP, x)1093#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP_GET(x)\1094 FIELD_GET(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP, x)1095 1096#define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP BIT(3)1097#define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP_SET(x)\1098 FIELD_PREP(SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP, x)1099#define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP_GET(x)\1100 FIELD_GET(SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP, x)1101 1102#define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0 GENMASK(5, 4)1103#define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_SET(x)\1104 FIELD_PREP(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0, x)1105#define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_GET(x)\1106 FIELD_GET(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0, x)1107 1108/* SD25G_TARGET:CMU_GRP_0:CMU_0E */1109#define SD25G_LANE_CMU_0E(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 56, 0, 1, 4)1110 1111#define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0 GENMASK(3, 0)1112#define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(x)\1113 FIELD_PREP(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0, x)1114#define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_GET(x)\1115 FIELD_GET(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0, x)1116 1117#define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD BIT(4)1118#define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_SET(x)\1119 FIELD_PREP(SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD, x)1120#define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_GET(x)\1121 FIELD_GET(SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD, x)1122 1123/* SD25G_TARGET:CMU_GRP_0:CMU_13 */1124#define SD25G_LANE_CMU_13(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 76, 0, 1, 4)1125 1126#define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0 GENMASK(3, 0)1127#define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET(x)\1128 FIELD_PREP(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0, x)1129#define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_GET(x)\1130 FIELD_GET(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0, x)1131 1132#define SD25G_LANE_CMU_13_CFG_JT_EN BIT(4)1133#define SD25G_LANE_CMU_13_CFG_JT_EN_SET(x)\1134 FIELD_PREP(SD25G_LANE_CMU_13_CFG_JT_EN, x)1135#define SD25G_LANE_CMU_13_CFG_JT_EN_GET(x)\1136 FIELD_GET(SD25G_LANE_CMU_13_CFG_JT_EN, x)1137 1138/* SD25G_TARGET:CMU_GRP_0:CMU_18 */1139#define SD25G_LANE_CMU_18(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 96, 0, 1, 4)1140 1141#define SD25G_LANE_CMU_18_R_PLL_RSTN BIT(0)1142#define SD25G_LANE_CMU_18_R_PLL_RSTN_SET(x)\1143 FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_RSTN, x)1144#define SD25G_LANE_CMU_18_R_PLL_RSTN_GET(x)\1145 FIELD_GET(SD25G_LANE_CMU_18_R_PLL_RSTN, x)1146 1147#define SD25G_LANE_CMU_18_R_PLL_LOL_SET BIT(1)1148#define SD25G_LANE_CMU_18_R_PLL_LOL_SET_SET(x)\1149 FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_LOL_SET, x)1150#define SD25G_LANE_CMU_18_R_PLL_LOL_SET_GET(x)\1151 FIELD_GET(SD25G_LANE_CMU_18_R_PLL_LOL_SET, x)1152 1153#define SD25G_LANE_CMU_18_R_PLL_LOS_SET BIT(2)1154#define SD25G_LANE_CMU_18_R_PLL_LOS_SET_SET(x)\1155 FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_LOS_SET, x)1156#define SD25G_LANE_CMU_18_R_PLL_LOS_SET_GET(x)\1157 FIELD_GET(SD25G_LANE_CMU_18_R_PLL_LOS_SET, x)1158 1159#define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0 GENMASK(5, 4)1160#define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_SET(x)\1161 FIELD_PREP(SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0, x)1162#define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_GET(x)\1163 FIELD_GET(SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0, x)1164 1165/* SD25G_TARGET:CMU_GRP_0:CMU_19 */1166#define SD25G_LANE_CMU_19(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 100, 0, 1, 4)1167 1168#define SD25G_LANE_CMU_19_R_CK_RESETB BIT(0)1169#define SD25G_LANE_CMU_19_R_CK_RESETB_SET(x)\1170 FIELD_PREP(SD25G_LANE_CMU_19_R_CK_RESETB, x)1171#define SD25G_LANE_CMU_19_R_CK_RESETB_GET(x)\1172 FIELD_GET(SD25G_LANE_CMU_19_R_CK_RESETB, x)1173 1174#define SD25G_LANE_CMU_19_R_PLL_DLOL_EN BIT(1)1175#define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_SET(x)\1176 FIELD_PREP(SD25G_LANE_CMU_19_R_PLL_DLOL_EN, x)1177#define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_GET(x)\1178 FIELD_GET(SD25G_LANE_CMU_19_R_PLL_DLOL_EN, x)1179 1180/* SD25G_TARGET:CMU_GRP_0:CMU_1A */1181#define SD25G_LANE_CMU_1A(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 104, 0, 1, 4)1182 1183#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0 GENMASK(2, 0)1184#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(x)\1185 FIELD_PREP(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0, x)1186#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_GET(x)\1187 FIELD_GET(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0, x)1188 1189#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT BIT(4)1190#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_SET(x)\1191 FIELD_PREP(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT, x)1192#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_GET(x)\1193 FIELD_GET(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT, x)1194 1195#define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE BIT(5)1196#define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE_SET(x)\1197 FIELD_PREP(SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE, x)1198#define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE_GET(x)\1199 FIELD_GET(SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE, x)1200 1201#define SD25G_LANE_CMU_1A_R_REG_MANUAL BIT(6)1202#define SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(x)\1203 FIELD_PREP(SD25G_LANE_CMU_1A_R_REG_MANUAL, x)1204#define SD25G_LANE_CMU_1A_R_REG_MANUAL_GET(x)\1205 FIELD_GET(SD25G_LANE_CMU_1A_R_REG_MANUAL, x)1206 1207/* SD25G_TARGET:CMU_GRP_1:CMU_2A */1208#define SD25G_LANE_CMU_2A(t) __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 36, 0, 1, 4)1209 1210#define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0 GENMASK(1, 0)1211#define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_SET(x)\1212 FIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_SEL_1_0, x)1213#define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_GET(x)\1214 FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_SEL_1_0, x)1215 1216#define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE BIT(4)1217#define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE_SET(x)\1218 FIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_LINK_LANE, x)1219#define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE_GET(x)\1220 FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_LINK_LANE, x)1221 1222#define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS BIT(5)1223#define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_SET(x)\1224 FIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS, x)1225#define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_GET(x)\1226 FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS, x)1227 1228/* SD25G_TARGET:CMU_GRP_1:CMU_30 */1229#define SD25G_LANE_CMU_30(t) __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 60, 0, 1, 4)1230 1231#define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0 GENMASK(2, 0)1232#define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_SET(x)\1233 FIELD_PREP(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0, x)1234#define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_GET(x)\1235 FIELD_GET(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0, x)1236 1237#define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0 GENMASK(6, 4)1238#define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_SET(x)\1239 FIELD_PREP(SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0, x)1240#define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_GET(x)\1241 FIELD_GET(SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0, x)1242 1243/* SD25G_TARGET:CMU_GRP_1:CMU_31 */1244#define SD25G_LANE_CMU_31(t) __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 64, 0, 1, 4)1245 1246#define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0 GENMASK(7, 0)1247#define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET(x)\1248 FIELD_PREP(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0, x)1249#define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_GET(x)\1250 FIELD_GET(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0, x)1251 1252/* SD25G_TARGET:CMU_GRP_2:CMU_40 */1253#define SD25G_LANE_CMU_40(t) __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 0, 0, 1, 4)1254 1255#define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL BIT(0)1256#define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_SET(x)\1257 FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL, x)1258#define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_GET(x)\1259 FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL, x)1260 1261#define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD BIT(1)1262#define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD_SET(x)\1263 FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD, x)1264#define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD_GET(x)\1265 FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD, x)1266 1267#define SD25G_LANE_CMU_40_L0_CFG_PD_CLK BIT(2)1268#define SD25G_LANE_CMU_40_L0_CFG_PD_CLK_SET(x)\1269 FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_PD_CLK, x)1270#define SD25G_LANE_CMU_40_L0_CFG_PD_CLK_GET(x)\1271 FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_PD_CLK, x)1272 1273#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN BIT(3)1274#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(x)\1275 FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN, x)1276#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_GET(x)\1277 FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN, x)1278 1279#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN BIT(4)1280#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN_SET(x)\1281 FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN, x)1282#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN_GET(x)\1283 FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN, x)1284 1285#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST BIT(5)1286#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_SET(x)\1287 FIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST, x)1288#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_GET(x)\1289 FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST, x)1290 1291/* SD25G_TARGET:CMU_GRP_2:CMU_45 */1292#define SD25G_LANE_CMU_45(t) __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 20, 0, 1, 4)1293 1294#define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0 GENMASK(7, 0)1295#define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET(x)\1296 FIELD_PREP(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0, x)1297#define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_GET(x)\1298 FIELD_GET(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0, x)1299 1300/* SD25G_TARGET:CMU_GRP_2:CMU_46 */1301#define SD25G_LANE_CMU_46(t) __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 24, 0, 1, 4)1302 1303#define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8 GENMASK(7, 0)1304#define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET(x)\1305 FIELD_PREP(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8, x)1306#define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_GET(x)\1307 FIELD_GET(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8, x)1308 1309/* SD25G_TARGET:CMU_GRP_3:CMU_C0 */1310#define SD25G_LANE_CMU_C0(t) __REG(TARGET_SD25G_LANE, t, 8, 768, 0, 1, 252, 0, 0, 1, 4)1311 1312#define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0 GENMASK(3, 0)1313#define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_SET(x)\1314 FIELD_PREP(SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0, x)1315#define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_GET(x)\1316 FIELD_GET(SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0, x)1317 1318#define SD25G_LANE_CMU_C0_PLL_LOL_UDL BIT(4)1319#define SD25G_LANE_CMU_C0_PLL_LOL_UDL_SET(x)\1320 FIELD_PREP(SD25G_LANE_CMU_C0_PLL_LOL_UDL, x)1321#define SD25G_LANE_CMU_C0_PLL_LOL_UDL_GET(x)\1322 FIELD_GET(SD25G_LANE_CMU_C0_PLL_LOL_UDL, x)1323 1324/* SD25G_TARGET:CMU_GRP_4:CMU_FF */1325#define SD25G_LANE_CMU_FF(t) __REG(TARGET_SD25G_LANE, t, 8, 1020, 0, 1, 4, 0, 0, 1, 4)1326 1327#define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX GENMASK(7, 0)1328#define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(x)\1329 FIELD_PREP(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, x)1330#define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_GET(x)\1331 FIELD_GET(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, x)1332 1333/* SD25G_TARGET:LANE_GRP_0:LANE_00 */1334#define SD25G_LANE_LANE_00(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 0, 0, 1, 4)1335 1336#define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0 GENMASK(3, 0)1337#define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_SET(x)\1338 FIELD_PREP(SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0, x)1339#define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_GET(x)\1340 FIELD_GET(SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0, x)1341 1342#define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0 GENMASK(5, 4)1343#define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_SET(x)\1344 FIELD_PREP(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0, x)1345#define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_GET(x)\1346 FIELD_GET(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0, x)1347 1348/* SD25G_TARGET:LANE_GRP_0:LANE_01 */1349#define SD25G_LANE_LANE_01(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 4, 0, 1, 4)1350 1351#define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0)1352#define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\1353 FIELD_PREP(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0, x)1354#define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\1355 FIELD_GET(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0, x)1356 1357#define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0 GENMASK(5, 4)1358#define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_SET(x)\1359 FIELD_PREP(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0, x)1360#define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_GET(x)\1361 FIELD_GET(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0, x)1362 1363/* SD25G_TARGET:LANE_GRP_0:LANE_03 */1364#define SD25G_LANE_LANE_03(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 12, 0, 1, 4)1365 1366#define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0 GENMASK(4, 0)1367#define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(x)\1368 FIELD_PREP(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0, x)1369#define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_GET(x)\1370 FIELD_GET(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0, x)1371 1372/* SD25G_TARGET:LANE_GRP_0:LANE_04 */1373#define SD25G_LANE_LANE_04(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 16, 0, 1, 4)1374 1375#define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN BIT(0)1376#define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(x)\1377 FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN, x)1378#define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_GET(x)\1379 FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN, x)1380 1381#define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN BIT(1)1382#define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_SET(x)\1383 FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN, x)1384#define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_GET(x)\1385 FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN, x)1386 1387#define SD25G_LANE_LANE_04_LN_CFG_PD_CML BIT(2)1388#define SD25G_LANE_LANE_04_LN_CFG_PD_CML_SET(x)\1389 FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_CML, x)1390#define SD25G_LANE_LANE_04_LN_CFG_PD_CML_GET(x)\1391 FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_CML, x)1392 1393#define SD25G_LANE_LANE_04_LN_CFG_PD_CLK BIT(3)1394#define SD25G_LANE_LANE_04_LN_CFG_PD_CLK_SET(x)\1395 FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_CLK, x)1396#define SD25G_LANE_LANE_04_LN_CFG_PD_CLK_GET(x)\1397 FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_CLK, x)1398 1399#define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER BIT(4)1400#define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_SET(x)\1401 FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER, x)1402#define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_GET(x)\1403 FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER, x)1404 1405#define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN BIT(5)1406#define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_SET(x)\1407 FIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN, x)1408#define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_GET(x)\1409 FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN, x)1410 1411/* SD25G_TARGET:LANE_GRP_0:LANE_05 */1412#define SD25G_LANE_LANE_05(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 20, 0, 1, 4)1413 1414#define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0 GENMASK(3, 0)1415#define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_SET(x)\1416 FIELD_PREP(SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0, x)1417#define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_GET(x)\1418 FIELD_GET(SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0, x)1419 1420#define SD25G_LANE_LANE_05_LN_CFG_BW_1_0 GENMASK(5, 4)1421#define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_SET(x)\1422 FIELD_PREP(SD25G_LANE_LANE_05_LN_CFG_BW_1_0, x)1423#define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_GET(x)\1424 FIELD_GET(SD25G_LANE_LANE_05_LN_CFG_BW_1_0, x)1425 1426/* SD25G_TARGET:LANE_GRP_0:LANE_06 */1427#define SD25G_LANE_LANE_06(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 24, 0, 1, 4)1428 1429#define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN BIT(0)1430#define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_SET(x)\1431 FIELD_PREP(SD25G_LANE_LANE_06_LN_CFG_EN_MAIN, x)1432#define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_GET(x)\1433 FIELD_GET(SD25G_LANE_LANE_06_LN_CFG_EN_MAIN, x)1434 1435#define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0 GENMASK(7, 4)1436#define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_SET(x)\1437 FIELD_PREP(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0, x)1438#define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_GET(x)\1439 FIELD_GET(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0, x)1440 1441/* SD25G_TARGET:LANE_GRP_0:LANE_07 */1442#define SD25G_LANE_LANE_07(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 28, 0, 1, 4)1443 1444#define SD25G_LANE_LANE_07_LN_CFG_EN_ADV BIT(0)1445#define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(x)\1446 FIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_ADV, x)1447#define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_GET(x)\1448 FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_ADV, x)1449 1450#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2 BIT(1)1451#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2_SET(x)\1452 FIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_DLY2, x)1453#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2_GET(x)\1454 FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_DLY2, x)1455 1456#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY BIT(2)1457#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_SET(x)\1458 FIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_DLY, x)1459#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_GET(x)\1460 FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_DLY, x)1461 1462/* SD25G_TARGET:LANE_GRP_0:LANE_09 */1463#define SD25G_LANE_LANE_09(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 36, 0, 1, 4)1464 1465#define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0 GENMASK(3, 0)1466#define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_SET(x)\1467 FIELD_PREP(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0, x)1468#define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_GET(x)\1469 FIELD_GET(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0, x)1470 1471/* SD25G_TARGET:LANE_GRP_0:LANE_0A */1472#define SD25G_LANE_LANE_0A(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 40, 0, 1, 4)1473 1474#define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0 GENMASK(5, 0)1475#define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_SET(x)\1476 FIELD_PREP(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0, x)1477#define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_GET(x)\1478 FIELD_GET(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0, x)1479 1480/* SD25G_TARGET:LANE_GRP_0:LANE_0B */1481#define SD25G_LANE_LANE_0B(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 44, 0, 1, 4)1482 1483#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN BIT(0)1484#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_SET(x)\1485 FIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN, x)1486#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_GET(x)\1487 FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN, x)1488 1489#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST BIT(1)1490#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST_SET(x)\1491 FIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST, x)1492#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST_GET(x)\1493 FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST, x)1494 1495#define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0 GENMASK(5, 4)1496#define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_SET(x)\1497 FIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0, x)1498#define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_GET(x)\1499 FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0, x)1500 1501/* SD25G_TARGET:LANE_GRP_0:LANE_0C */1502#define SD25G_LANE_LANE_0C(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 48, 0, 1, 4)1503 1504#define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0)1505#define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\1506 FIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0, x)1507#define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\1508 FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0, x)1509 1510#define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN BIT(4)1511#define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN_SET(x)\1512 FIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN, x)1513#define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN_GET(x)\1514 FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN, x)1515 1516#define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD BIT(5)1517#define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_SET(x)\1518 FIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD, x)1519#define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_GET(x)\1520 FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD, x)1521 1522/* SD25G_TARGET:LANE_GRP_0:LANE_0D */1523#define SD25G_LANE_LANE_0D(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 52, 0, 1, 4)1524 1525#define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0 GENMASK(2, 0)1526#define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_SET(x)\1527 FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0, x)1528#define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_GET(x)\1529 FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0, x)1530 1531#define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8 BIT(4)1532#define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8_SET(x)\1533 FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8, x)1534#define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8_GET(x)\1535 FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8, x)1536 1537#define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN BIT(5)1538#define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN_SET(x)\1539 FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN, x)1540#define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN_GET(x)\1541 FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN, x)1542 1543#define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD BIT(6)1544#define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD_SET(x)\1545 FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD, x)1546#define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD_GET(x)\1547 FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD, x)1548 1549#define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN BIT(7)1550#define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_SET(x)\1551 FIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN, x)1552#define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_GET(x)\1553 FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN, x)1554 1555/* SD25G_TARGET:LANE_GRP_0:LANE_0E */1556#define SD25G_LANE_LANE_0E(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 56, 0, 1, 4)1557 1558#define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN BIT(0)1559#define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_SET(x)\1560 FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN, x)1561#define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_GET(x)\1562 FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN, x)1563 1564#define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD BIT(1)1565#define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD_SET(x)\1566 FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD, x)1567#define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD_GET(x)\1568 FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD, x)1569 1570#define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG BIT(2)1571#define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_SET(x)\1572 FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG, x)1573#define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_GET(x)\1574 FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG, x)1575 1576#define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0 GENMASK(6, 4)1577#define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_SET(x)\1578 FIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0, x)1579#define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_GET(x)\1580 FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0, x)1581 1582/* SD25G_TARGET:LANE_GRP_0:LANE_0F */1583#define SD25G_LANE_LANE_0F(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 60, 0, 1, 4)1584 1585#define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1 GENMASK(4, 0)1586#define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_SET(x)\1587 FIELD_PREP(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1, x)1588#define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_GET(x)\1589 FIELD_GET(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1, x)1590 1591/* SD25G_TARGET:LANE_GRP_0:LANE_18 */1592#define SD25G_LANE_LANE_18(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 96, 0, 1, 4)1593 1594#define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN BIT(0)1595#define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(x)\1596 FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN, x)1597#define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_GET(x)\1598 FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN, x)1599 1600#define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT BIT(1)1601#define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT_SET(x)\1602 FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT, x)1603#define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT_GET(x)\1604 FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT, x)1605 1606#define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN BIT(2)1607#define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN_SET(x)\1608 FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN, x)1609#define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN_GET(x)\1610 FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN, x)1611 1612#define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD BIT(3)1613#define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(x)\1614 FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD, x)1615#define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_GET(x)\1616 FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD, x)1617 1618#define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0 GENMASK(6, 4)1619#define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_SET(x)\1620 FIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0, x)1621#define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_GET(x)\1622 FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0, x)1623 1624/* SD25G_TARGET:LANE_GRP_0:LANE_19 */1625#define SD25G_LANE_LANE_19(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 100, 0, 1, 4)1626 1627#define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD BIT(0)1628#define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_SET(x)\1629 FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_DCDR_PD, x)1630#define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_GET(x)\1631 FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_DCDR_PD, x)1632 1633#define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD BIT(1)1634#define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_SET(x)\1635 FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD, x)1636#define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_GET(x)\1637 FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD, x)1638 1639#define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL BIT(2)1640#define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL_SET(x)\1641 FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL, x)1642#define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL_GET(x)\1643 FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL, x)1644 1645#define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN BIT(3)1646#define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_SET(x)\1647 FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN, x)1648#define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_GET(x)\1649 FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN, x)1650 1651#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU BIT(4)1652#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU_SET(x)\1653 FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU, x)1654#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU_GET(x)\1655 FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU, x)1656 1657#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP BIT(5)1658#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP_SET(x)\1659 FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP, x)1660#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP_GET(x)\1661 FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP, x)1662 1663#define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET BIT(6)1664#define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET_SET(x)\1665 FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET, x)1666#define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET_GET(x)\1667 FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET, x)1668 1669#define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE BIT(7)1670#define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_SET(x)\1671 FIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_PD_CTLE, x)1672#define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_GET(x)\1673 FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_PD_CTLE, x)1674 1675/* SD25G_TARGET:LANE_GRP_0:LANE_1A */1676#define SD25G_LANE_LANE_1A(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 104, 0, 1, 4)1677 1678#define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN BIT(0)1679#define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_SET(x)\1680 FIELD_PREP(SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN, x)1681#define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_GET(x)\1682 FIELD_GET(SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN, x)1683 1684#define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0 GENMASK(6, 4)1685#define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_SET(x)\1686 FIELD_PREP(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0, x)1687#define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_GET(x)\1688 FIELD_GET(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0, x)1689 1690/* SD25G_TARGET:LANE_GRP_0:LANE_1B */1691#define SD25G_LANE_LANE_1B(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 108, 0, 1, 4)1692 1693#define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0 GENMASK(7, 0)1694#define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(x)\1695 FIELD_PREP(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0, x)1696#define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_GET(x)\1697 FIELD_GET(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0, x)1698 1699/* SD25G_TARGET:LANE_GRP_0:LANE_1C */1700#define SD25G_LANE_LANE_1C(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 112, 0, 1, 4)1701 1702#define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN BIT(0)1703#define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(x)\1704 FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN, x)1705#define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_GET(x)\1706 FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN, x)1707 1708#define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD BIT(1)1709#define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_SET(x)\1710 FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_DFE_PD, x)1711#define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_GET(x)\1712 FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_DFE_PD, x)1713 1714#define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD BIT(2)1715#define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD_SET(x)\1716 FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD, x)1717#define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD_GET(x)\1718 FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD, x)1719 1720#define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0 GENMASK(7, 4)1721#define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_SET(x)\1722 FIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0, x)1723#define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_GET(x)\1724 FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0, x)1725 1726/* SD25G_TARGET:LANE_GRP_0:LANE_1D */1727#define SD25G_LANE_LANE_1D(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 116, 0, 1, 4)1728 1729#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR BIT(0)1730#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_SET(x)\1731 FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR, x)1732#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_GET(x)\1733 FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR, x)1734 1735#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD BIT(1)1736#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD_SET(x)\1737 FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD, x)1738#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD_GET(x)\1739 FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD, x)1740 1741#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN BIT(2)1742#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN_SET(x)\1743 FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN, x)1744#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN_GET(x)\1745 FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN, x)1746 1747#define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP BIT(3)1748#define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP_SET(x)\1749 FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP, x)1750#define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP_GET(x)\1751 FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP, x)1752 1753#define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T BIT(4)1754#define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T_SET(x)\1755 FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PHID_1T, x)1756#define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T_GET(x)\1757 FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PHID_1T, x)1758 1759#define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN BIT(5)1760#define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_SET(x)\1761 FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN, x)1762#define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_GET(x)\1763 FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN, x)1764 1765#define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR BIT(6)1766#define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR_SET(x)\1767 FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR, x)1768#define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR_GET(x)\1769 FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR, x)1770 1771#define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD BIT(7)1772#define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_SET(x)\1773 FIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD, x)1774#define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_GET(x)\1775 FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD, x)1776 1777/* SD25G_TARGET:LANE_GRP_0:LANE_1E */1778#define SD25G_LANE_LANE_1E(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 120, 0, 1, 4)1779 1780#define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0 GENMASK(1, 0)1781#define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_SET(x)\1782 FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0, x)1783#define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_GET(x)\1784 FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0, x)1785 1786#define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN BIT(4)1787#define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_SET(x)\1788 FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN, x)1789#define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_GET(x)\1790 FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN, x)1791 1792#define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN BIT(5)1793#define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_SET(x)\1794 FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN, x)1795#define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_GET(x)\1796 FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN, x)1797 1798#define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR BIT(6)1799#define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR_SET(x)\1800 FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR, x)1801#define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR_GET(x)\1802 FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR, x)1803 1804#define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD BIT(7)1805#define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_SET(x)\1806 FIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD, x)1807#define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_GET(x)\1808 FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD, x)1809 1810/* SD25G_TARGET:LANE_GRP_0:LANE_21 */1811#define SD25G_LANE_LANE_21(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 132, 0, 1, 4)1812 1813#define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0 GENMASK(4, 0)1814#define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_SET(x)\1815 FIELD_PREP(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0, x)1816#define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_GET(x)\1817 FIELD_GET(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0, x)1818 1819/* SD25G_TARGET:LANE_GRP_0:LANE_22 */1820#define SD25G_LANE_LANE_22(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 136, 0, 1, 4)1821 1822#define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0 GENMASK(3, 0)1823#define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_SET(x)\1824 FIELD_PREP(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0, x)1825#define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_GET(x)\1826 FIELD_GET(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0, x)1827 1828/* SD25G_TARGET:LANE_GRP_0:LANE_25 */1829#define SD25G_LANE_LANE_25(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 148, 0, 1, 4)1830 1831#define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0 GENMASK(6, 0)1832#define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_SET(x)\1833 FIELD_PREP(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0, x)1834#define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_GET(x)\1835 FIELD_GET(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0, x)1836 1837/* SD25G_TARGET:LANE_GRP_0:LANE_26 */1838#define SD25G_LANE_LANE_26(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 152, 0, 1, 4)1839 1840#define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0 GENMASK(6, 0)1841#define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_SET(x)\1842 FIELD_PREP(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0, x)1843#define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_GET(x)\1844 FIELD_GET(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0, x)1845 1846/* SD25G_TARGET:LANE_GRP_0:LANE_28 */1847#define SD25G_LANE_LANE_28(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 160, 0, 1, 4)1848 1849#define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN BIT(0)1850#define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_SET(x)\1851 FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN, x)1852#define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_GET(x)\1853 FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN, x)1854 1855#define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH BIT(1)1856#define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH_SET(x)\1857 FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH, x)1858#define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH_GET(x)\1859 FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH, x)1860 1861#define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL BIT(2)1862#define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL_SET(x)\1863 FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL, x)1864#define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL_GET(x)\1865 FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL, x)1866 1867#define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0 GENMASK(6, 4)1868#define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_SET(x)\1869 FIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0, x)1870#define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_GET(x)\1871 FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0, x)1872 1873/* SD25G_TARGET:LANE_GRP_0:LANE_2B */1874#define SD25G_LANE_LANE_2B(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 172, 0, 1, 4)1875 1876#define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0 GENMASK(3, 0)1877#define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(x)\1878 FIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0, x)1879#define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_GET(x)\1880 FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0, x)1881 1882#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR BIT(4)1883#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR_SET(x)\1884 FIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR, x)1885#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR_GET(x)\1886 FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR, x)1887 1888#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU BIT(5)1889#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_SET(x)\1890 FIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU, x)1891#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_GET(x)\1892 FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU, x)1893 1894/* SD25G_TARGET:LANE_GRP_0:LANE_2C */1895#define SD25G_LANE_LANE_2C(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 176, 0, 1, 4)1896 1897#define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0 GENMASK(2, 0)1898#define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_SET(x)\1899 FIELD_PREP(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0, x)1900#define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_GET(x)\1901 FIELD_GET(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0, x)1902 1903#define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER BIT(4)1904#define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_SET(x)\1905 FIELD_PREP(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER, x)1906#define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_GET(x)\1907 FIELD_GET(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER, x)1908 1909/* SD25G_TARGET:LANE_GRP_0:LANE_2D */1910#define SD25G_LANE_LANE_2D(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 180, 0, 1, 4)1911 1912#define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0 GENMASK(2, 0)1913#define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_SET(x)\1914 FIELD_PREP(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0, x)1915#define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_GET(x)\1916 FIELD_GET(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0, x)1917 1918#define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0 GENMASK(6, 4)1919#define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_SET(x)\1920 FIELD_PREP(SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0, x)1921#define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_GET(x)\1922 FIELD_GET(SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0, x)1923 1924/* SD25G_TARGET:LANE_GRP_0:LANE_2E */1925#define SD25G_LANE_LANE_2E(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 184, 0, 1, 4)1926 1927#define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN BIT(0)1928#define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_SET(x)\1929 FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN, x)1930#define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_GET(x)\1931 FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN, x)1932 1933#define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ BIT(1)1934#define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_SET(x)\1935 FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ, x)1936#define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_GET(x)\1937 FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ, x)1938 1939#define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ BIT(2)1940#define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_SET(x)\1941 FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ, x)1942#define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_GET(x)\1943 FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ, x)1944 1945#define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS BIT(3)1946#define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS_SET(x)\1947 FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS, x)1948#define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS_GET(x)\1949 FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS, x)1950 1951#define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC BIT(4)1952#define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC_SET(x)\1953 FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC, x)1954#define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC_GET(x)\1955 FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC, x)1956 1957#define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG BIT(5)1958#define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(x)\1959 FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG, x)1960#define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_GET(x)\1961 FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG, x)1962 1963#define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN BIT(6)1964#define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN_SET(x)\1965 FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN, x)1966#define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN_GET(x)\1967 FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN, x)1968 1969#define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN BIT(7)1970#define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_SET(x)\1971 FIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN, x)1972#define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_GET(x)\1973 FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN, x)1974 1975/* SD25G_TARGET:LANE_GRP_0:LANE_40 */1976#define SD25G_LANE_LANE_40(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 256, 0, 1, 4)1977 1978#define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE BIT(0)1979#define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_SET(x)\1980 FIELD_PREP(SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE, x)1981#define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_GET(x)\1982 FIELD_GET(SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE, x)1983 1984#define SD25G_LANE_LANE_40_LN_R_TX_POL_INV BIT(1)1985#define SD25G_LANE_LANE_40_LN_R_TX_POL_INV_SET(x)\1986 FIELD_PREP(SD25G_LANE_LANE_40_LN_R_TX_POL_INV, x)1987#define SD25G_LANE_LANE_40_LN_R_TX_POL_INV_GET(x)\1988 FIELD_GET(SD25G_LANE_LANE_40_LN_R_TX_POL_INV, x)1989 1990#define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE BIT(2)1991#define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE_SET(x)\1992 FIELD_PREP(SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE, x)1993#define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE_GET(x)\1994 FIELD_GET(SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE, x)1995 1996#define SD25G_LANE_LANE_40_LN_R_RX_POL_INV BIT(3)1997#define SD25G_LANE_LANE_40_LN_R_RX_POL_INV_SET(x)\1998 FIELD_PREP(SD25G_LANE_LANE_40_LN_R_RX_POL_INV, x)1999#define SD25G_LANE_LANE_40_LN_R_RX_POL_INV_GET(x)\2000 FIELD_GET(SD25G_LANE_LANE_40_LN_R_RX_POL_INV, x)2001 2002#define SD25G_LANE_LANE_40_LN_R_CDR_RSTN BIT(4)2003#define SD25G_LANE_LANE_40_LN_R_CDR_RSTN_SET(x)\2004 FIELD_PREP(SD25G_LANE_LANE_40_LN_R_CDR_RSTN, x)2005#define SD25G_LANE_LANE_40_LN_R_CDR_RSTN_GET(x)\2006 FIELD_GET(SD25G_LANE_LANE_40_LN_R_CDR_RSTN, x)2007 2008#define SD25G_LANE_LANE_40_LN_R_DFE_RSTN BIT(5)2009#define SD25G_LANE_LANE_40_LN_R_DFE_RSTN_SET(x)\2010 FIELD_PREP(SD25G_LANE_LANE_40_LN_R_DFE_RSTN, x)2011#define SD25G_LANE_LANE_40_LN_R_DFE_RSTN_GET(x)\2012 FIELD_GET(SD25G_LANE_LANE_40_LN_R_DFE_RSTN, x)2013 2014#define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN BIT(6)2015#define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_SET(x)\2016 FIELD_PREP(SD25G_LANE_LANE_40_LN_R_CTLE_RSTN, x)2017#define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_GET(x)\2018 FIELD_GET(SD25G_LANE_LANE_40_LN_R_CTLE_RSTN, x)2019 2020/* SD25G_TARGET:LANE_GRP_0:LANE_42 */2021#define SD25G_LANE_LANE_42(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 264, 0, 1, 4)2022 2023#define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0 GENMASK(7, 0)2024#define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_SET(x)\2025 FIELD_PREP(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0, x)2026#define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_GET(x)\2027 FIELD_GET(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0, x)2028 2029/* SD25G_TARGET:LANE_GRP_0:LANE_43 */2030#define SD25G_LANE_LANE_43(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 268, 0, 1, 4)2031 2032#define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8 GENMASK(7, 0)2033#define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_SET(x)\2034 FIELD_PREP(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8, x)2035#define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_GET(x)\2036 FIELD_GET(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8, x)2037 2038/* SD25G_TARGET:LANE_GRP_0:LANE_44 */2039#define SD25G_LANE_LANE_44(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 272, 0, 1, 4)2040 2041#define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0 GENMASK(7, 0)2042#define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_SET(x)\2043 FIELD_PREP(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0, x)2044#define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_GET(x)\2045 FIELD_GET(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0, x)2046 2047/* SD25G_TARGET:LANE_GRP_0:LANE_45 */2048#define SD25G_LANE_LANE_45(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 276, 0, 1, 4)2049 2050#define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8 GENMASK(7, 0)2051#define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_SET(x)\2052 FIELD_PREP(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8, x)2053#define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_GET(x)\2054 FIELD_GET(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8, x)2055 2056/* SD25G_TARGET:LANE_GRP_1:LANE_DE */2057#define SD25G_LANE_LANE_DE(t) __REG(TARGET_SD25G_LANE, t, 8, 1792, 0, 1, 128, 120, 0, 1, 4)2058 2059#define SD25G_LANE_LANE_DE_LN_LOL_UDL BIT(0)2060#define SD25G_LANE_LANE_DE_LN_LOL_UDL_SET(x)\2061 FIELD_PREP(SD25G_LANE_LANE_DE_LN_LOL_UDL, x)2062#define SD25G_LANE_LANE_DE_LN_LOL_UDL_GET(x)\2063 FIELD_GET(SD25G_LANE_LANE_DE_LN_LOL_UDL, x)2064 2065#define SD25G_LANE_LANE_DE_LN_LOL BIT(1)2066#define SD25G_LANE_LANE_DE_LN_LOL_SET(x)\2067 FIELD_PREP(SD25G_LANE_LANE_DE_LN_LOL, x)2068#define SD25G_LANE_LANE_DE_LN_LOL_GET(x)\2069 FIELD_GET(SD25G_LANE_LANE_DE_LN_LOL, x)2070 2071#define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED BIT(2)2072#define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED_SET(x)\2073 FIELD_PREP(SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED, x)2074#define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED_GET(x)\2075 FIELD_GET(SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED, x)2076 2077#define SD25G_LANE_LANE_DE_LN_PMA_RXEI BIT(3)2078#define SD25G_LANE_LANE_DE_LN_PMA_RXEI_SET(x)\2079 FIELD_PREP(SD25G_LANE_LANE_DE_LN_PMA_RXEI, x)2080#define SD25G_LANE_LANE_DE_LN_PMA_RXEI_GET(x)\2081 FIELD_GET(SD25G_LANE_LANE_DE_LN_PMA_RXEI, x)2082 2083/* SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */2084#define SD6G_LANE_LANE_DF(t) __REG(TARGET_SD6G_LANE, t, 13, 832, 0, 1, 84, 60, 0, 1, 4)2085 2086#define SD6G_LANE_LANE_DF_LOL_UDL BIT(0)2087#define SD6G_LANE_LANE_DF_LOL_UDL_SET(x)\2088 FIELD_PREP(SD6G_LANE_LANE_DF_LOL_UDL, x)2089#define SD6G_LANE_LANE_DF_LOL_UDL_GET(x)\2090 FIELD_GET(SD6G_LANE_LANE_DF_LOL_UDL, x)2091 2092#define SD6G_LANE_LANE_DF_LOL BIT(1)2093#define SD6G_LANE_LANE_DF_LOL_SET(x)\2094 FIELD_PREP(SD6G_LANE_LANE_DF_LOL, x)2095#define SD6G_LANE_LANE_DF_LOL_GET(x)\2096 FIELD_GET(SD6G_LANE_LANE_DF_LOL, x)2097 2098#define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED BIT(2)2099#define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_SET(x)\2100 FIELD_PREP(SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)2101#define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(x)\2102 FIELD_GET(SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)2103 2104#define SD6G_LANE_LANE_DF_SQUELCH BIT(3)2105#define SD6G_LANE_LANE_DF_SQUELCH_SET(x)\2106 FIELD_PREP(SD6G_LANE_LANE_DF_SQUELCH, x)2107#define SD6G_LANE_LANE_DF_SQUELCH_GET(x)\2108 FIELD_GET(SD6G_LANE_LANE_DF_SQUELCH, x)2109 2110/* SD10G_CMU_TARGET:CMU_GRP_0:CMU_00 */2111#define SD_CMU_CMU_00(t) __REG(TARGET_SD_CMU, t, 14, 0, 0, 1, 20, 0, 0, 1, 4)2112 2113#define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE BIT(0)2114#define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_SET(x)\2115 FIELD_PREP(SD_CMU_CMU_00_R_HWT_SIMULATION_MODE, x)2116#define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_GET(x)\2117 FIELD_GET(SD_CMU_CMU_00_R_HWT_SIMULATION_MODE, x)2118 2119#define SD_CMU_CMU_00_CFG_PLL_LOL_SET BIT(1)2120#define SD_CMU_CMU_00_CFG_PLL_LOL_SET_SET(x)\2121 FIELD_PREP(SD_CMU_CMU_00_CFG_PLL_LOL_SET, x)2122#define SD_CMU_CMU_00_CFG_PLL_LOL_SET_GET(x)\2123 FIELD_GET(SD_CMU_CMU_00_CFG_PLL_LOL_SET, x)2124 2125#define SD_CMU_CMU_00_CFG_PLL_LOS_SET BIT(2)2126#define SD_CMU_CMU_00_CFG_PLL_LOS_SET_SET(x)\2127 FIELD_PREP(SD_CMU_CMU_00_CFG_PLL_LOS_SET, x)2128#define SD_CMU_CMU_00_CFG_PLL_LOS_SET_GET(x)\2129 FIELD_GET(SD_CMU_CMU_00_CFG_PLL_LOS_SET, x)2130 2131#define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0 GENMASK(5, 4)2132#define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET(x)\2133 FIELD_PREP(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, x)2134#define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_GET(x)\2135 FIELD_GET(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, x)2136 2137/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_05 */2138#define SD_CMU_CMU_05(t) __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 0, 0, 1, 4)2139 2140#define SD_CMU_CMU_05_CFG_REFCK_TERM_EN BIT(0)2141#define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_SET(x)\2142 FIELD_PREP(SD_CMU_CMU_05_CFG_REFCK_TERM_EN, x)2143#define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_GET(x)\2144 FIELD_GET(SD_CMU_CMU_05_CFG_REFCK_TERM_EN, x)2145 2146#define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0 GENMASK(5, 4)2147#define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_SET(x)\2148 FIELD_PREP(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, x)2149#define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_GET(x)\2150 FIELD_GET(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, x)2151 2152/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_06 */2153#define SD_CMU_CMU_06(t) \2154 __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 4, 0, 1, 4)2155 2156#define SD_CMU_CMU_06_CFG_DISLOS BIT(0)2157#define SD_CMU_CMU_06_CFG_DISLOS_SET(x)\2158 FIELD_PREP(SD_CMU_CMU_06_CFG_DISLOS, x)2159#define SD_CMU_CMU_06_CFG_DISLOS_GET(x)\2160 FIELD_GET(SD_CMU_CMU_06_CFG_DISLOS, x)2161 2162#define SD_CMU_CMU_06_CFG_DISLOL BIT(1)2163#define SD_CMU_CMU_06_CFG_DISLOL_SET(x)\2164 FIELD_PREP(SD_CMU_CMU_06_CFG_DISLOL, x)2165#define SD_CMU_CMU_06_CFG_DISLOL_GET(x)\2166 FIELD_GET(SD_CMU_CMU_06_CFG_DISLOL, x)2167 2168#define SD_CMU_CMU_06_CFG_DCLOL BIT(2)2169#define SD_CMU_CMU_06_CFG_DCLOL_SET(x)\2170 FIELD_PREP(SD_CMU_CMU_06_CFG_DCLOL, x)2171#define SD_CMU_CMU_06_CFG_DCLOL_GET(x)\2172 FIELD_GET(SD_CMU_CMU_06_CFG_DCLOL, x)2173 2174#define SD_CMU_CMU_06_CFG_FORCE_RX_FILT BIT(3)2175#define SD_CMU_CMU_06_CFG_FORCE_RX_FILT_SET(x)\2176 FIELD_PREP(SD_CMU_CMU_06_CFG_FORCE_RX_FILT, x)2177#define SD_CMU_CMU_06_CFG_FORCE_RX_FILT_GET(x)\2178 FIELD_GET(SD_CMU_CMU_06_CFG_FORCE_RX_FILT, x)2179 2180#define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD BIT(4)2181#define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_SET(x)\2182 FIELD_PREP(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD, x)2183#define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_GET(x)\2184 FIELD_GET(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD, x)2185 2186#define SD_CMU_CMU_06_CFG_VCO_PD BIT(5)2187#define SD_CMU_CMU_06_CFG_VCO_PD_SET(x)\2188 FIELD_PREP(SD_CMU_CMU_06_CFG_VCO_PD, x)2189#define SD_CMU_CMU_06_CFG_VCO_PD_GET(x)\2190 FIELD_GET(SD_CMU_CMU_06_CFG_VCO_PD, x)2191 2192#define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN BIT(6)2193#define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN_SET(x)\2194 FIELD_PREP(SD_CMU_CMU_06_CFG_VCO_CAL_RESETN, x)2195#define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN_GET(x)\2196 FIELD_GET(SD_CMU_CMU_06_CFG_VCO_CAL_RESETN, x)2197 2198#define SD_CMU_CMU_06_CFG_VCO_CAL_BYP BIT(7)2199#define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_SET(x)\2200 FIELD_PREP(SD_CMU_CMU_06_CFG_VCO_CAL_BYP, x)2201#define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_GET(x)\2202 FIELD_GET(SD_CMU_CMU_06_CFG_VCO_CAL_BYP, x)2203 2204/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_08 */2205#define SD_CMU_CMU_08(t) \2206 __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 12, 0, 1, 4)2207 2208#define SD_CMU_CMU_08_CFG_VFILT2PAD BIT(0)2209#define SD_CMU_CMU_08_CFG_VFILT2PAD_SET(x)\2210 FIELD_PREP(SD_CMU_CMU_08_CFG_VFILT2PAD, x)2211#define SD_CMU_CMU_08_CFG_VFILT2PAD_GET(x)\2212 FIELD_GET(SD_CMU_CMU_08_CFG_VFILT2PAD, x)2213 2214#define SD_CMU_CMU_08_CFG_EN_DUMMY BIT(1)2215#define SD_CMU_CMU_08_CFG_EN_DUMMY_SET(x)\2216 FIELD_PREP(SD_CMU_CMU_08_CFG_EN_DUMMY, x)2217#define SD_CMU_CMU_08_CFG_EN_DUMMY_GET(x)\2218 FIELD_GET(SD_CMU_CMU_08_CFG_EN_DUMMY, x)2219 2220#define SD_CMU_CMU_08_CFG_CK_TREE_PD BIT(2)2221#define SD_CMU_CMU_08_CFG_CK_TREE_PD_SET(x)\2222 FIELD_PREP(SD_CMU_CMU_08_CFG_CK_TREE_PD, x)2223#define SD_CMU_CMU_08_CFG_CK_TREE_PD_GET(x)\2224 FIELD_GET(SD_CMU_CMU_08_CFG_CK_TREE_PD, x)2225 2226#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN BIT(3)2227#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_SET(x)\2228 FIELD_PREP(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN, x)2229#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_GET(x)\2230 FIELD_GET(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN, x)2231 2232#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN BIT(4)2233#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_SET(x)\2234 FIELD_PREP(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN, x)2235#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_GET(x)\2236 FIELD_GET(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN, x)2237 2238/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_09 */2239#define SD_CMU_CMU_09(t) __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 16, 0, 1, 4)2240 2241#define SD_CMU_CMU_09_CFG_EN_TX_CK_UP BIT(0)2242#define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_SET(x)\2243 FIELD_PREP(SD_CMU_CMU_09_CFG_EN_TX_CK_UP, x)2244#define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_GET(x)\2245 FIELD_GET(SD_CMU_CMU_09_CFG_EN_TX_CK_UP, x)2246 2247#define SD_CMU_CMU_09_CFG_EN_TX_CK_DN BIT(1)2248#define SD_CMU_CMU_09_CFG_EN_TX_CK_DN_SET(x)\2249 FIELD_PREP(SD_CMU_CMU_09_CFG_EN_TX_CK_DN, x)2250#define SD_CMU_CMU_09_CFG_EN_TX_CK_DN_GET(x)\2251 FIELD_GET(SD_CMU_CMU_09_CFG_EN_TX_CK_DN, x)2252 2253#define SD_CMU_CMU_09_CFG_SW_8G BIT(4)2254#define SD_CMU_CMU_09_CFG_SW_8G_SET(x)\2255 FIELD_PREP(SD_CMU_CMU_09_CFG_SW_8G, x)2256#define SD_CMU_CMU_09_CFG_SW_8G_GET(x)\2257 FIELD_GET(SD_CMU_CMU_09_CFG_SW_8G, x)2258 2259#define SD_CMU_CMU_09_CFG_SW_10G BIT(5)2260#define SD_CMU_CMU_09_CFG_SW_10G_SET(x)\2261 FIELD_PREP(SD_CMU_CMU_09_CFG_SW_10G, x)2262#define SD_CMU_CMU_09_CFG_SW_10G_GET(x)\2263 FIELD_GET(SD_CMU_CMU_09_CFG_SW_10G, x)2264 2265/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_0D */2266#define SD_CMU_CMU_0D(t) __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 32, 0, 1, 4)2267 2268#define SD_CMU_CMU_0D_CFG_PD_DIV64 BIT(0)2269#define SD_CMU_CMU_0D_CFG_PD_DIV64_SET(x)\2270 FIELD_PREP(SD_CMU_CMU_0D_CFG_PD_DIV64, x)2271#define SD_CMU_CMU_0D_CFG_PD_DIV64_GET(x)\2272 FIELD_GET(SD_CMU_CMU_0D_CFG_PD_DIV64, x)2273 2274#define SD_CMU_CMU_0D_CFG_PD_DIV66 BIT(1)2275#define SD_CMU_CMU_0D_CFG_PD_DIV66_SET(x)\2276 FIELD_PREP(SD_CMU_CMU_0D_CFG_PD_DIV66, x)2277#define SD_CMU_CMU_0D_CFG_PD_DIV66_GET(x)\2278 FIELD_GET(SD_CMU_CMU_0D_CFG_PD_DIV66, x)2279 2280#define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD BIT(2)2281#define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_SET(x)\2282 FIELD_PREP(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD, x)2283#define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_GET(x)\2284 FIELD_GET(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD, x)2285 2286#define SD_CMU_CMU_0D_CFG_JC_BYP BIT(3)2287#define SD_CMU_CMU_0D_CFG_JC_BYP_SET(x)\2288 FIELD_PREP(SD_CMU_CMU_0D_CFG_JC_BYP, x)2289#define SD_CMU_CMU_0D_CFG_JC_BYP_GET(x)\2290 FIELD_GET(SD_CMU_CMU_0D_CFG_JC_BYP, x)2291 2292#define SD_CMU_CMU_0D_CFG_REFCK_PD BIT(4)2293#define SD_CMU_CMU_0D_CFG_REFCK_PD_SET(x)\2294 FIELD_PREP(SD_CMU_CMU_0D_CFG_REFCK_PD, x)2295#define SD_CMU_CMU_0D_CFG_REFCK_PD_GET(x)\2296 FIELD_GET(SD_CMU_CMU_0D_CFG_REFCK_PD, x)2297 2298/* SD10G_CMU_TARGET:CMU_GRP_3:CMU_1B */2299#define SD_CMU_CMU_1B(t) __REG(TARGET_SD_CMU, t, 14, 104, 0, 1, 20, 4, 0, 1, 4)2300 2301#define SD_CMU_CMU_1B_CFG_RESERVE_7_0 GENMASK(7, 0)2302#define SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(x)\2303 FIELD_PREP(SD_CMU_CMU_1B_CFG_RESERVE_7_0, x)2304#define SD_CMU_CMU_1B_CFG_RESERVE_7_0_GET(x)\2305 FIELD_GET(SD_CMU_CMU_1B_CFG_RESERVE_7_0, x)2306 2307/* SD10G_CMU_TARGET:CMU_GRP_4:CMU_1F */2308#define SD_CMU_CMU_1F(t) __REG(TARGET_SD_CMU, t, 14, 124, 0, 1, 68, 0, 0, 1, 4)2309 2310#define SD_CMU_CMU_1F_CFG_BIAS_DN_EN BIT(0)2311#define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_SET(x)\2312 FIELD_PREP(SD_CMU_CMU_1F_CFG_BIAS_DN_EN, x)2313#define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_GET(x)\2314 FIELD_GET(SD_CMU_CMU_1F_CFG_BIAS_DN_EN, x)2315 2316#define SD_CMU_CMU_1F_CFG_BIAS_UP_EN BIT(1)2317#define SD_CMU_CMU_1F_CFG_BIAS_UP_EN_SET(x)\2318 FIELD_PREP(SD_CMU_CMU_1F_CFG_BIAS_UP_EN, x)2319#define SD_CMU_CMU_1F_CFG_BIAS_UP_EN_GET(x)\2320 FIELD_GET(SD_CMU_CMU_1F_CFG_BIAS_UP_EN, x)2321 2322#define SD_CMU_CMU_1F_CFG_IC2IP_N BIT(2)2323#define SD_CMU_CMU_1F_CFG_IC2IP_N_SET(x)\2324 FIELD_PREP(SD_CMU_CMU_1F_CFG_IC2IP_N, x)2325#define SD_CMU_CMU_1F_CFG_IC2IP_N_GET(x)\2326 FIELD_GET(SD_CMU_CMU_1F_CFG_IC2IP_N, x)2327 2328#define SD_CMU_CMU_1F_CFG_VTUNE_SEL BIT(3)2329#define SD_CMU_CMU_1F_CFG_VTUNE_SEL_SET(x)\2330 FIELD_PREP(SD_CMU_CMU_1F_CFG_VTUNE_SEL, x)2331#define SD_CMU_CMU_1F_CFG_VTUNE_SEL_GET(x)\2332 FIELD_GET(SD_CMU_CMU_1F_CFG_VTUNE_SEL, x)2333 2334/* SD10G_CMU_TARGET:CMU_GRP_5:CMU_30 */2335#define SD_CMU_CMU_30(t) __REG(TARGET_SD_CMU, t, 14, 192, 0, 1, 72, 0, 0, 1, 4)2336 2337#define SD_CMU_CMU_30_R_PLL_DLOL_EN BIT(0)2338#define SD_CMU_CMU_30_R_PLL_DLOL_EN_SET(x)\2339 FIELD_PREP(SD_CMU_CMU_30_R_PLL_DLOL_EN, x)2340#define SD_CMU_CMU_30_R_PLL_DLOL_EN_GET(x)\2341 FIELD_GET(SD_CMU_CMU_30_R_PLL_DLOL_EN, x)2342 2343/* SD10G_CMU_TARGET:CMU_GRP_6:CMU_44 */2344#define SD_CMU_CMU_44(t) __REG(TARGET_SD_CMU, t, 14, 264, 0, 1, 632, 8, 0, 1, 4)2345 2346#define SD_CMU_CMU_44_R_PLL_RSTN BIT(0)2347#define SD_CMU_CMU_44_R_PLL_RSTN_SET(x)\2348 FIELD_PREP(SD_CMU_CMU_44_R_PLL_RSTN, x)2349#define SD_CMU_CMU_44_R_PLL_RSTN_GET(x)\2350 FIELD_GET(SD_CMU_CMU_44_R_PLL_RSTN, x)2351 2352#define SD_CMU_CMU_44_R_CK_RESETB BIT(1)2353#define SD_CMU_CMU_44_R_CK_RESETB_SET(x)\2354 FIELD_PREP(SD_CMU_CMU_44_R_CK_RESETB, x)2355#define SD_CMU_CMU_44_R_CK_RESETB_GET(x)\2356 FIELD_GET(SD_CMU_CMU_44_R_CK_RESETB, x)2357 2358/* SD10G_CMU_TARGET:CMU_GRP_6:CMU_45 */2359#define SD_CMU_CMU_45(t) __REG(TARGET_SD_CMU, t, 14, 264, 0, 1, 632, 12, 0, 1, 4)2360 2361#define SD_CMU_CMU_45_R_EN_RATECHG_CTRL BIT(0)2362#define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(x)\2363 FIELD_PREP(SD_CMU_CMU_45_R_EN_RATECHG_CTRL, x)2364#define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_GET(x)\2365 FIELD_GET(SD_CMU_CMU_45_R_EN_RATECHG_CTRL, x)2366 2367#define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT BIT(1)2368#define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(x)\2369 FIELD_PREP(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT, x)2370#define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_GET(x)\2371 FIELD_GET(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT, x)2372 2373#define SD_CMU_CMU_45_RESERVED BIT(2)2374#define SD_CMU_CMU_45_RESERVED_SET(x)\2375 FIELD_PREP(SD_CMU_CMU_45_RESERVED, x)2376#define SD_CMU_CMU_45_RESERVED_GET(x)\2377 FIELD_GET(SD_CMU_CMU_45_RESERVED, x)2378 2379#define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT BIT(3)2380#define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_SET(x)\2381 FIELD_PREP(SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT, x)2382#define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_GET(x)\2383 FIELD_GET(SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT, x)2384 2385#define SD_CMU_CMU_45_RESERVED_2 BIT(4)2386#define SD_CMU_CMU_45_RESERVED_2_SET(x)\2387 FIELD_PREP(SD_CMU_CMU_45_RESERVED_2, x)2388#define SD_CMU_CMU_45_RESERVED_2_GET(x)\2389 FIELD_GET(SD_CMU_CMU_45_RESERVED_2, x)2390 2391#define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT BIT(5)2392#define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_SET(x)\2393 FIELD_PREP(SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT, x)2394#define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_GET(x)\2395 FIELD_GET(SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT, x)2396 2397#define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT BIT(6)2398#define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_SET(x)\2399 FIELD_PREP(SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT, x)2400#define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_GET(x)\2401 FIELD_GET(SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT, x)2402 2403#define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN BIT(7)2404#define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_SET(x)\2405 FIELD_PREP(SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN, x)2406#define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_GET(x)\2407 FIELD_GET(SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN, x)2408 2409/* SD10G_CMU_TARGET:CMU_GRP_6:CMU_47 */2410#define SD_CMU_CMU_47(t) __REG(TARGET_SD_CMU, t, 14, 264, 0, 1, 632, 20, 0, 1, 4)2411 2412#define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0 GENMASK(4, 0)2413#define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(x)\2414 FIELD_PREP(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, x)2415#define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_GET(x)\2416 FIELD_GET(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, x)2417 2418/* SD10G_CMU_TARGET:CMU_GRP_7:CMU_E0 */2419#define SD_CMU_CMU_E0(t) __REG(TARGET_SD_CMU, t, 14, 896, 0, 1, 8, 0, 0, 1, 4)2420 2421#define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0 GENMASK(3, 0)2422#define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_SET(x)\2423 FIELD_PREP(SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0, x)2424#define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_GET(x)\2425 FIELD_GET(SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0, x)2426 2427#define SD_CMU_CMU_E0_PLL_LOL_UDL BIT(4)2428#define SD_CMU_CMU_E0_PLL_LOL_UDL_SET(x)\2429 FIELD_PREP(SD_CMU_CMU_E0_PLL_LOL_UDL, x)2430#define SD_CMU_CMU_E0_PLL_LOL_UDL_GET(x)\2431 FIELD_GET(SD_CMU_CMU_E0_PLL_LOL_UDL, x)2432 2433/* SD_CMU_TARGET:SD_CMU_CFG:SD_CMU_CFG */2434#define SD_CMU_CFG_SD_CMU_CFG(t) __REG(TARGET_SD_CMU_CFG, t, 14, 0, 0, 1, 8, 0, 0, 1, 4)2435 2436#define SD_CMU_CFG_SD_CMU_CFG_CMU_RST BIT(0)2437#define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(x)\2438 FIELD_PREP(SD_CMU_CFG_SD_CMU_CFG_CMU_RST, x)2439#define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_GET(x)\2440 FIELD_GET(SD_CMU_CFG_SD_CMU_CFG_CMU_RST, x)2441 2442#define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST BIT(1)2443#define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(x)\2444 FIELD_PREP(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, x)2445#define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_GET(x)\2446 FIELD_GET(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, x)2447 2448/* SD_LANE_TARGET:SD_RESET:SD_SER_RST */2449#define SD_LANE_SD_SER_RST(t) __REG(TARGET_SD_LANE, t, 25, 0, 0, 1, 8, 0, 0, 1, 4)2450 2451#define SD_LANE_SD_SER_RST_SER_RST BIT(0)2452#define SD_LANE_SD_SER_RST_SER_RST_SET(x)\2453 FIELD_PREP(SD_LANE_SD_SER_RST_SER_RST, x)2454#define SD_LANE_SD_SER_RST_SER_RST_GET(x)\2455 FIELD_GET(SD_LANE_SD_SER_RST_SER_RST, x)2456 2457/* SD_LANE_TARGET:SD_RESET:SD_DES_RST */2458#define SD_LANE_SD_DES_RST(t) __REG(TARGET_SD_LANE, t, 25, 0, 0, 1, 8, 4, 0, 1, 4)2459 2460#define SD_LANE_SD_DES_RST_DES_RST BIT(0)2461#define SD_LANE_SD_DES_RST_DES_RST_SET(x)\2462 FIELD_PREP(SD_LANE_SD_DES_RST_DES_RST, x)2463#define SD_LANE_SD_DES_RST_DES_RST_GET(x)\2464 FIELD_GET(SD_LANE_SD_DES_RST_DES_RST, x)2465 2466/* SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */2467#define SD_LANE_SD_LANE_CFG(t) __REG(TARGET_SD_LANE, t, 25, 8, 0, 1, 8, 0, 0, 1, 4)2468 2469#define SD_LANE_SD_LANE_CFG_MACRO_RST BIT(0)2470#define SD_LANE_SD_LANE_CFG_MACRO_RST_SET(x)\2471 FIELD_PREP(SD_LANE_SD_LANE_CFG_MACRO_RST, x)2472#define SD_LANE_SD_LANE_CFG_MACRO_RST_GET(x)\2473 FIELD_GET(SD_LANE_SD_LANE_CFG_MACRO_RST, x)2474 2475#define SD_LANE_SD_LANE_CFG_EXT_CFG_RST BIT(1)2476#define SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(x)\2477 FIELD_PREP(SD_LANE_SD_LANE_CFG_EXT_CFG_RST, x)2478#define SD_LANE_SD_LANE_CFG_EXT_CFG_RST_GET(x)\2479 FIELD_GET(SD_LANE_SD_LANE_CFG_EXT_CFG_RST, x)2480 2481#define SD_LANE_SD_LANE_CFG_TX_REF_SEL GENMASK(5, 4)2482#define SD_LANE_SD_LANE_CFG_TX_REF_SEL_SET(x)\2483 FIELD_PREP(SD_LANE_SD_LANE_CFG_TX_REF_SEL, x)2484#define SD_LANE_SD_LANE_CFG_TX_REF_SEL_GET(x)\2485 FIELD_GET(SD_LANE_SD_LANE_CFG_TX_REF_SEL, x)2486 2487#define SD_LANE_SD_LANE_CFG_RX_REF_SEL GENMASK(7, 6)2488#define SD_LANE_SD_LANE_CFG_RX_REF_SEL_SET(x)\2489 FIELD_PREP(SD_LANE_SD_LANE_CFG_RX_REF_SEL, x)2490#define SD_LANE_SD_LANE_CFG_RX_REF_SEL_GET(x)\2491 FIELD_GET(SD_LANE_SD_LANE_CFG_RX_REF_SEL, x)2492 2493#define SD_LANE_SD_LANE_CFG_LANE_RST BIT(8)2494#define SD_LANE_SD_LANE_CFG_LANE_RST_SET(x)\2495 FIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_RST, x)2496#define SD_LANE_SD_LANE_CFG_LANE_RST_GET(x)\2497 FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_RST, x)2498 2499#define SD_LANE_SD_LANE_CFG_LANE_TX_RST BIT(9)2500#define SD_LANE_SD_LANE_CFG_LANE_TX_RST_SET(x)\2501 FIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_TX_RST, x)2502#define SD_LANE_SD_LANE_CFG_LANE_TX_RST_GET(x)\2503 FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_TX_RST, x)2504 2505#define SD_LANE_SD_LANE_CFG_LANE_RX_RST BIT(10)2506#define SD_LANE_SD_LANE_CFG_LANE_RX_RST_SET(x)\2507 FIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_RX_RST, x)2508#define SD_LANE_SD_LANE_CFG_LANE_RX_RST_GET(x)\2509 FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_RX_RST, x)2510 2511/* SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */2512#define SD_LANE_SD_LANE_STAT(t) __REG(TARGET_SD_LANE, t, 25, 8, 0, 1, 8, 4, 0, 1, 4)2513 2514#define SD_LANE_SD_LANE_STAT_PMA_RST_DONE BIT(0)2515#define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_SET(x)\2516 FIELD_PREP(SD_LANE_SD_LANE_STAT_PMA_RST_DONE, x)2517#define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_GET(x)\2518 FIELD_GET(SD_LANE_SD_LANE_STAT_PMA_RST_DONE, x)2519 2520#define SD_LANE_SD_LANE_STAT_DFE_RST_DONE BIT(1)2521#define SD_LANE_SD_LANE_STAT_DFE_RST_DONE_SET(x)\2522 FIELD_PREP(SD_LANE_SD_LANE_STAT_DFE_RST_DONE, x)2523#define SD_LANE_SD_LANE_STAT_DFE_RST_DONE_GET(x)\2524 FIELD_GET(SD_LANE_SD_LANE_STAT_DFE_RST_DONE, x)2525 2526#define SD_LANE_SD_LANE_STAT_DBG_OBS GENMASK(31, 16)2527#define SD_LANE_SD_LANE_STAT_DBG_OBS_SET(x)\2528 FIELD_PREP(SD_LANE_SD_LANE_STAT_DBG_OBS, x)2529#define SD_LANE_SD_LANE_STAT_DBG_OBS_GET(x)\2530 FIELD_GET(SD_LANE_SD_LANE_STAT_DBG_OBS, x)2531 2532/* SD_LANE_TARGET:SD_PWR_CFG:QUIET_MODE_6G */2533#define SD_LANE_QUIET_MODE_6G(t) \2534 __REG(TARGET_SD_LANE, t, 25, 24, 0, 1, 8, 4, 0, 1, 4)2535 2536#define SD_LANE_QUIET_MODE_6G_QUIET_MODE GENMASK(24, 0)2537#define SD_LANE_QUIET_MODE_6G_QUIET_MODE_SET(x)\2538 FIELD_PREP(SD_LANE_QUIET_MODE_6G_QUIET_MODE, x)2539#define SD_LANE_QUIET_MODE_6G_QUIET_MODE_GET(x)\2540 FIELD_GET(SD_LANE_QUIET_MODE_6G_QUIET_MODE, x)2541 2542/* SD_LANE_TARGET:CFG_STAT_FX100:MISC */2543#define SD_LANE_MISC(t) __REG(TARGET_SD_LANE, t, 25, 56, 0, 1, 56, 0, 0, 1, 4)2544 2545#define SD_LANE_MISC_SD_125_RST_DIS BIT(0)2546#define SD_LANE_MISC_SD_125_RST_DIS_SET(x)\2547 FIELD_PREP(SD_LANE_MISC_SD_125_RST_DIS, x)2548#define SD_LANE_MISC_SD_125_RST_DIS_GET(x)\2549 FIELD_GET(SD_LANE_MISC_SD_125_RST_DIS, x)2550 2551#define SD_LANE_MISC_RX_ENA BIT(1)2552#define SD_LANE_MISC_RX_ENA_SET(x)\2553 FIELD_PREP(SD_LANE_MISC_RX_ENA, x)2554#define SD_LANE_MISC_RX_ENA_GET(x)\2555 FIELD_GET(SD_LANE_MISC_RX_ENA, x)2556 2557#define SD_LANE_MISC_MUX_ENA BIT(2)2558#define SD_LANE_MISC_MUX_ENA_SET(x)\2559 FIELD_PREP(SD_LANE_MISC_MUX_ENA, x)2560#define SD_LANE_MISC_MUX_ENA_GET(x)\2561 FIELD_GET(SD_LANE_MISC_MUX_ENA, x)2562 2563#define SD_LANE_MISC_CORE_CLK_FREQ GENMASK(5, 4)2564#define SD_LANE_MISC_CORE_CLK_FREQ_SET(x)\2565 FIELD_PREP(SD_LANE_MISC_CORE_CLK_FREQ, x)2566#define SD_LANE_MISC_CORE_CLK_FREQ_GET(x)\2567 FIELD_GET(SD_LANE_MISC_CORE_CLK_FREQ, x)2568 2569/* SD_LANE_TARGET:CFG_STAT_FX100:M_STAT_MISC */2570#define SD_LANE_M_STAT_MISC(t) __REG(TARGET_SD_LANE, t, 25, 56, 0, 1, 56, 36, 0, 1, 4)2571 2572#define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM GENMASK(21, 0)2573#define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_SET(x)\2574 FIELD_PREP(SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM, x)2575#define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_GET(x)\2576 FIELD_GET(SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM, x)2577 2578#define SD_LANE_M_STAT_MISC_M_LOCK_CNT GENMASK(31, 24)2579#define SD_LANE_M_STAT_MISC_M_LOCK_CNT_SET(x)\2580 FIELD_PREP(SD_LANE_M_STAT_MISC_M_LOCK_CNT, x)2581#define SD_LANE_M_STAT_MISC_M_LOCK_CNT_GET(x)\2582 FIELD_GET(SD_LANE_M_STAT_MISC_M_LOCK_CNT, x)2583 2584/* SD25G_CFG_TARGET:SD_RESET:SD_SER_RST */2585#define SD_LANE_25G_SD_SER_RST(t) __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 0, 0, 1, 4)2586 2587#define SD_LANE_25G_SD_SER_RST_SER_RST BIT(0)2588#define SD_LANE_25G_SD_SER_RST_SER_RST_SET(x)\2589 FIELD_PREP(SD_LANE_25G_SD_SER_RST_SER_RST, x)2590#define SD_LANE_25G_SD_SER_RST_SER_RST_GET(x)\2591 FIELD_GET(SD_LANE_25G_SD_SER_RST_SER_RST, x)2592 2593/* SD25G_CFG_TARGET:SD_RESET:SD_DES_RST */2594#define SD_LANE_25G_SD_DES_RST(t) __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 4, 0, 1, 4)2595 2596#define SD_LANE_25G_SD_DES_RST_DES_RST BIT(0)2597#define SD_LANE_25G_SD_DES_RST_DES_RST_SET(x)\2598 FIELD_PREP(SD_LANE_25G_SD_DES_RST_DES_RST, x)2599#define SD_LANE_25G_SD_DES_RST_DES_RST_GET(x)\2600 FIELD_GET(SD_LANE_25G_SD_DES_RST_DES_RST, x)2601 2602/* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */2603#define SD_LANE_25G_SD_LANE_CFG(t) __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 0, 0, 1, 4)2604 2605#define SD_LANE_25G_SD_LANE_CFG_MACRO_RST BIT(0)2606#define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(x)\2607 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_MACRO_RST, x)2608#define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_GET(x)\2609 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_MACRO_RST, x)2610 2611#define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST BIT(1)2612#define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(x)\2613 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST, x)2614#define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_GET(x)\2615 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST, x)2616 2617#define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE BIT(4)2618#define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE_SET(x)\2619 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE, x)2620#define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE_GET(x)\2621 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE, x)2622 2623#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE GENMASK(7, 5)2624#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE_SET(x)\2625 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE, x)2626#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE_GET(x)\2627 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE, x)2628 2629#define SD_LANE_25G_SD_LANE_CFG_LANE_RST BIT(8)2630#define SD_LANE_25G_SD_LANE_CFG_LANE_RST_SET(x)\2631 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_LANE_RST, x)2632#define SD_LANE_25G_SD_LANE_CFG_LANE_RST_GET(x)\2633 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_LANE_RST, x)2634 2635#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV BIT(9)2636#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV_SET(x)\2637 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV, x)2638#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV_GET(x)\2639 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV, x)2640 2641#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN BIT(10)2642#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN_SET(x)\2643 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN, x)2644#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN_GET(x)\2645 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN, x)2646 2647#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY BIT(11)2648#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY_SET(x)\2649 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY, x)2650#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY_GET(x)\2651 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY, x)2652 2653#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV GENMASK(15, 12)2654#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV_SET(x)\2655 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV, x)2656#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV_GET(x)\2657 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV, x)2658 2659#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN BIT(16)2660#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN_SET(x)\2661 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN, x)2662#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN_GET(x)\2663 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN, x)2664 2665#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY GENMASK(21, 17)2666#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY_SET(x)\2667 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY, x)2668#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY_GET(x)\2669 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY, x)2670 2671#define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN BIT(22)2672#define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN_SET(x)\2673 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN, x)2674#define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN_GET(x)\2675 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN, x)2676 2677#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN BIT(23)2678#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN_SET(x)\2679 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN, x)2680#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN_GET(x)\2681 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN, x)2682 2683#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING BIT(24)2684#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING_SET(x)\2685 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING, x)2686#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING_GET(x)\2687 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING, x)2688 2689#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI BIT(25)2690#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI_SET(x)\2691 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI, x)2692#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI_GET(x)\2693 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI, x)2694 2695#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN GENMASK(28, 26)2696#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_SET(x)\2697 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN, x)2698#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_GET(x)\2699 FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN, x)2700 2701/* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG2 */2702#define SD_LANE_25G_SD_LANE_CFG2(t) __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 4, 0, 1, 4)2703 2704#define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL GENMASK(2, 0)2705#define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_SET(x)\2706 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL, x)2707#define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_GET(x)\2708 FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL, x)2709 2710#define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL GENMASK(5, 3)2711#define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL_SET(x)\2712 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL, x)2713#define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL_GET(x)\2714 FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL, x)2715 2716#define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL GENMASK(8, 6)2717#define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL_SET(x)\2718 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL, x)2719#define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL_GET(x)\2720 FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL, x)2721 2722#define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED GENMASK(10, 9)2723#define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED_SET(x)\2724 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED, x)2725#define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED_GET(x)\2726 FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED, x)2727 2728#define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV GENMASK(13, 11)2729#define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV_SET(x)\2730 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV, x)2731#define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV_GET(x)\2732 FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV, x)2733 2734#define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV GENMASK(16, 14)2735#define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV_SET(x)\2736 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV, x)2737#define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV_GET(x)\2738 FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV, x)2739 2740#define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL GENMASK(19, 17)2741#define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL_SET(x)\2742 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL, x)2743#define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL_GET(x)\2744 FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL, x)2745 2746#define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV GENMASK(23, 20)2747#define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV_SET(x)\2748 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV, x)2749#define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV_GET(x)\2750 FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV, x)2751 2752#define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL GENMASK(25, 24)2753#define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL_SET(x)\2754 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL, x)2755#define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL_GET(x)\2756 FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL, x)2757 2758#define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL GENMASK(28, 26)2759#define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL_SET(x)\2760 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL, x)2761#define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL_GET(x)\2762 FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL, x)2763 2764#define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL GENMASK(31, 29)2765#define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_SET(x)\2766 FIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL, x)2767#define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_GET(x)\2768 FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL, x)2769 2770/* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */2771#define SD_LANE_25G_SD_LANE_STAT(t) __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 8, 0, 1, 4)2772 2773#define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE BIT(0)2774#define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_SET(x)\2775 FIELD_PREP(SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE, x)2776#define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_GET(x)\2777 FIELD_GET(SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE, x)2778 2779#define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE BIT(1)2780#define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE_SET(x)\2781 FIELD_PREP(SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE, x)2782#define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE_GET(x)\2783 FIELD_GET(SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE, x)2784 2785#define SD_LANE_25G_SD_LANE_STAT_DBG_OBS GENMASK(31, 16)2786#define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_SET(x)\2787 FIELD_PREP(SD_LANE_25G_SD_LANE_STAT_DBG_OBS, x)2788#define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_GET(x)\2789 FIELD_GET(SD_LANE_25G_SD_LANE_STAT_DBG_OBS, x)2790 2791/* SD25G_CFG_TARGET:SD_PWR_CFG:QUIET_MODE_6G */2792#define SD_LANE_25G_QUIET_MODE_6G(t) \2793 __REG(TARGET_SD_LANE_25G, t, 8, 28, 0, 1, 8, 4, 0, 1, 4)2794 2795#define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE GENMASK(24, 0)2796#define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_SET(x)\2797 FIELD_PREP(SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE, x)2798#define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_GET(x)\2799 FIELD_GET(SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE, x)2800 2801#endif /* _SPARX5_SERDES_REGS_H_ */2802