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1# SPDX-License-Identifier: GPL-2.0-only2#3# Phy drivers for Qualcomm and Atheros platforms4#5config PHY_ATH79_USB6 tristate "Atheros AR71XX/9XXX USB PHY driver"7 depends on OF && (ATH79 || COMPILE_TEST)8 default y if USB_EHCI_HCD_PLATFORM || USB_OHCI_HCD_PLATFORM9 select RESET_CONTROLLER10 select GENERIC_PHY11 help12 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.13 14config PHY_QCOM_APQ8064_SATA15 tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"16 depends on ARCH_QCOM17 depends on HAS_IOMEM18 depends on OF19 select GENERIC_PHY20 21config PHY_QCOM_EDP22 tristate "Qualcomm eDP PHY driver"23 depends on ARCH_QCOM || COMPILE_TEST24 depends on OF25 depends on COMMON_CLK26 select GENERIC_PHY27 help28 Enable this driver to support the Qualcomm eDP PHY found in various29 Qualcomm chipsets.30 31config PHY_QCOM_IPQ4019_USB32 tristate "Qualcomm IPQ4019 USB PHY driver"33 depends on OF && (ARCH_QCOM || COMPILE_TEST)34 select GENERIC_PHY35 help36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.37 38config PHY_QCOM_IPQ806X_SATA39 tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"40 depends on ARCH_QCOM41 depends on HAS_IOMEM42 depends on OF43 select GENERIC_PHY44 45config PHY_QCOM_PCIE246 tristate "Qualcomm PCIe Gen2 PHY Driver"47 depends on OF && COMMON_CLK && (ARCH_QCOM || COMPILE_TEST)48 select GENERIC_PHY49 help50 Enable this to support the Qualcomm PCIe PHY, used with the Synopsys51 based PCIe controller.52 53menuconfig PHY_QCOM_QMP54 tristate "Qualcomm QMP PHY Drivers"55 depends on OF && COMMON_CLK && (ARCH_QCOM || COMPILE_TEST)56 57if PHY_QCOM_QMP58 59config PHY_QCOM_QMP_COMBO60 tristate "Qualcomm QMP Combo PHY Driver"61 default PHY_QCOM_QMP62 depends on TYPEC || TYPEC=n63 depends on DRM || DRM=n64 select GENERIC_PHY65 select MFD_SYSCON66 select DRM_AUX_BRIDGE if DRM_BRIDGE67 help68 Enable this to support the QMP Combo PHY transceiver that is used69 with USB3 and DisplayPort controllers on Qualcomm chips.70 71config PHY_QCOM_QMP_PCIE72 tristate "Qualcomm QMP PCIe PHY Driver"73 depends on PCI || COMPILE_TEST74 select GENERIC_PHY75 default PHY_QCOM_QMP76 help77 Enable this to support the QMP PCIe PHY transceiver that is used78 with PCIe controllers on Qualcomm chips.79 80config PHY_QCOM_QMP_PCIE_899681 tristate "Qualcomm QMP PCIe 8996 PHY Driver"82 depends on PCI || COMPILE_TEST83 select GENERIC_PHY84 default PHY_QCOM_QMP85 help86 Enable this to support the QMP PCIe PHY transceiver that is used87 with PCIe controllers on Qualcomm msm8996 chips.88 89config PHY_QCOM_QMP_UFS90 tristate "Qualcomm QMP UFS PHY Driver"91 select GENERIC_PHY92 default PHY_QCOM_QMP93 help94 Enable this to support the QMP UFS PHY transceiver that is used95 with UFS controllers on Qualcomm chips.96 97config PHY_QCOM_QMP_USB98 tristate "Qualcomm QMP USB PHY Driver"99 select GENERIC_PHY100 default PHY_QCOM_QMP101 help102 Enable this to support the QMP USB PHY transceiver that is used103 with USB3 controllers on Qualcomm chips.104 105config PHY_QCOM_QMP_USB_LEGACY106 tristate "Qualcomm QMP legacy USB PHY Driver"107 select GENERIC_PHY108 default n109 help110 Enable this legacy driver to support the QMP USB+DisplayPort Combo111 PHY transceivers working only in USB3 mode on Qualcomm chips. This112 driver exists only for compatibility with older device trees,113 existing users have been migrated to PHY_QCOM_QMP_COMBO driver.114 115endif # PHY_QCOM_QMP116 117config PHY_QCOM_QUSB2118 tristate "Qualcomm QUSB2 PHY Driver"119 depends on OF && (ARCH_QCOM || COMPILE_TEST)120 depends on NVMEM || !NVMEM121 select GENERIC_PHY122 help123 Enable this to support the HighSpeed QUSB2 PHY transceiver for USB124 controllers on Qualcomm chips. This driver supports the high-speed125 PHY which is usually paired with either the ChipIdea or Synopsys DWC3126 USB IPs on MSM SOCs.127 128config PHY_QCOM_SNPS_EUSB2129 tristate "Qualcomm SNPS eUSB2 PHY Driver"130 depends on OF && (ARCH_QCOM || COMPILE_TEST)131 select GENERIC_PHY132 help133 Enable support for the USB high-speed SNPS eUSB2 phy on Qualcomm134 chipsets. The PHY is paired with a Synopsys DWC3 USB controller135 on Qualcomm SOCs.136 137config PHY_QCOM_EUSB2_REPEATER138 tristate "Qualcomm SNPS eUSB2 Repeater Driver"139 depends on OF && (ARCH_QCOM || COMPILE_TEST)140 select GENERIC_PHY141 help142 Enable support for the USB high-speed SNPS eUSB2 repeater on Qualcomm143 PMICs. The repeater is paired with a Synopsys eUSB2 Phy144 on Qualcomm SOCs.145 146config PHY_QCOM_M31_USB147 tristate "Qualcomm M31 HS PHY driver support"148 depends on USB && (ARCH_QCOM || COMPILE_TEST)149 select GENERIC_PHY150 help151 Enable this to support M31 HS PHY transceivers on Qualcomm chips152 with DWC3 USB core. It handles PHY initialization, clock153 management required after resetting the hardware and power154 management. This driver is required even for peripheral only or155 host only mode configurations.156 157config PHY_QCOM_USB_HS158 tristate "Qualcomm USB HS PHY module"159 depends on USB_ULPI_BUS160 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in161 select GENERIC_PHY162 help163 Support for the USB high-speed ULPI compliant phy on Qualcomm164 chipsets.165 166config PHY_QCOM_USB_SNPS_FEMTO_V2167 tristate "Qualcomm SNPS FEMTO USB HS PHY V2 module"168 depends on OF && (ARCH_QCOM || COMPILE_TEST)169 select GENERIC_PHY170 help171 Enable support for the USB high-speed SNPS Femto phy on Qualcomm172 chipsets. This PHY has differences in the register map compared173 to the V1 variants. The PHY is paired with a Synopsys DWC3 USB174 controller on Qualcomm SOCs.175 176config PHY_QCOM_USB_HSIC177 tristate "Qualcomm USB HSIC ULPI PHY module"178 depends on USB_ULPI_BUS179 select GENERIC_PHY180 help181 Support for the USB HSIC ULPI compliant PHY on QCOM chipsets.182 183config PHY_QCOM_USB_HS_28NM184 tristate "Qualcomm 28nm High-Speed PHY"185 depends on OF && (ARCH_QCOM || COMPILE_TEST)186 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in187 select GENERIC_PHY188 help189 Enable this to support the Qualcomm Synopsys DesignWare Core 28nm190 High-Speed PHY driver. This driver supports the Hi-Speed PHY which191 is usually paired with either the ChipIdea or Synopsys DWC3 USB192 IPs on MSM SOCs.193 194config PHY_QCOM_USB_SS195 tristate "Qualcomm USB Super-Speed PHY driver"196 depends on OF && (ARCH_QCOM || COMPILE_TEST)197 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in198 select GENERIC_PHY199 help200 Enable this to support the Super-Speed USB transceiver on various201 Qualcomm chipsets.202 203config PHY_QCOM_IPQ806X_USB204 tristate "Qualcomm IPQ806x DWC3 USB PHY driver"205 depends on HAS_IOMEM206 depends on OF && (ARCH_QCOM || COMPILE_TEST)207 select GENERIC_PHY208 help209 This option enables support for the Synopsis PHYs present inside the210 Qualcomm USB3.0 DWC3 controller on ipq806x SoC. This driver supports211 both HS and SS PHY controllers.212 213config PHY_QCOM_SGMII_ETH214 tristate "Qualcomm DWMAC SGMII SerDes/PHY driver"215 depends on OF && (ARCH_QCOM || COMPILE_TEST)216 depends on HAS_IOMEM217 select GENERIC_PHY218 help219 Enable this to support the internal SerDes/SGMII PHY on various220 Qualcomm chipsets.221