brintos / linux-shallow public Read only

1// SPDX-License-Identifier: GPL-2.02/*3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.4 */5 6#include <linux/clk.h>7#include <linux/clk-provider.h>8#include <linux/delay.h>9#include <linux/err.h>10#include <linux/io.h>11#include <linux/iopoll.h>12#include <linux/kernel.h>13#include <linux/mfd/syscon.h>14#include <linux/module.h>15#include <linux/of.h>16#include <linux/of_address.h>17#include <linux/phy/pcie.h>18#include <linux/phy/phy.h>19#include <linux/platform_device.h>20#include <linux/regmap.h>21#include <linux/regulator/consumer.h>22#include <linux/reset.h>23#include <linux/slab.h>24 25#include <dt-bindings/phy/phy-qcom-qmp.h>26 27#include "phy-qcom-qmp-common.h"28 29#include "phy-qcom-qmp.h"30#include "phy-qcom-qmp-pcs-misc-v3.h"31#include "phy-qcom-qmp-pcs-pcie-v4.h"32#include "phy-qcom-qmp-pcs-pcie-v4_20.h"33#include "phy-qcom-qmp-pcs-pcie-v5.h"34#include "phy-qcom-qmp-pcs-pcie-v5_20.h"35#include "phy-qcom-qmp-pcs-pcie-v6.h"36#include "phy-qcom-qmp-pcs-pcie-v6_20.h"37#include "phy-qcom-qmp-pcie-qhp.h"38 39#define PHY_INIT_COMPLETE_TIMEOUT		1000040 41/* set of registers with offsets different per-PHY */42enum qphy_reg_layout {43	/* PCS registers */44	QPHY_SW_RESET,45	QPHY_START_CTRL,46	QPHY_PCS_STATUS,47	QPHY_PCS_POWER_DOWN_CONTROL,48	/* Keep last to ensure regs_layout arrays are properly initialized */49	QPHY_LAYOUT_SIZE50};51 52static const unsigned int pciephy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {53	[QPHY_SW_RESET]			= QPHY_V2_PCS_SW_RESET,54	[QPHY_START_CTRL]		= QPHY_V2_PCS_START_CONTROL,55	[QPHY_PCS_STATUS]		= QPHY_V2_PCS_PCI_PCS_STATUS,56	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V2_PCS_POWER_DOWN_CONTROL,57};58 59static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {60	[QPHY_SW_RESET]			= QPHY_V3_PCS_SW_RESET,61	[QPHY_START_CTRL]		= QPHY_V3_PCS_START_CONTROL,62	[QPHY_PCS_STATUS]		= QPHY_V3_PCS_PCS_STATUS,63	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V3_PCS_POWER_DOWN_CONTROL,64};65 66static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {67	[QPHY_SW_RESET]			= 0x00,68	[QPHY_START_CTRL]		= 0x08,69	[QPHY_PCS_STATUS]		= 0x2ac,70	[QPHY_PCS_POWER_DOWN_CONTROL]	= 0x04,71};72 73static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {74	[QPHY_SW_RESET]			= QPHY_V4_PCS_SW_RESET,75	[QPHY_START_CTRL]		= QPHY_V4_PCS_START_CONTROL,76	[QPHY_PCS_STATUS]		= QPHY_V4_PCS_PCS_STATUS1,77	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V4_PCS_POWER_DOWN_CONTROL,78};79 80static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {81	[QPHY_SW_RESET]			= QPHY_V5_PCS_SW_RESET,82	[QPHY_START_CTRL]		= QPHY_V5_PCS_START_CONTROL,83	[QPHY_PCS_STATUS]		= QPHY_V5_PCS_PCS_STATUS1,84	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V5_PCS_POWER_DOWN_CONTROL,85};86 87static const unsigned int pciephy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {88	[QPHY_SW_RESET]			= QPHY_V6_PCS_SW_RESET,89	[QPHY_START_CTRL]		= QPHY_V6_PCS_START_CONTROL,90	[QPHY_PCS_STATUS]		= QPHY_V6_PCS_PCS_STATUS1,91	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V6_PCS_POWER_DOWN_CONTROL,92};93 94static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {95	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),96	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),97	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),98	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),99	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),100	QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),101	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),102	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),103	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),104	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),105	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),106	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),107	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),108	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),109	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),110	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),111	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),112	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),113	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),114	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),115	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),116	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),117	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),118	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),119	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),120	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),121	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),122	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),123	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),124	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),125	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),126	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),127	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),128	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),129	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),130	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),131	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),132	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),133	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),134	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),135	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),136	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),137};138 139static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {140	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),141	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),142	QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),143	QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),144};145 146static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {147	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),148	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),149	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),150	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),151	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),152	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),153	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),154	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),155	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),156	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),157	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),158	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),159	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),160	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),161};162 163static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {164	QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),165	QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),166	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),167	QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),168	QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),169	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),170	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),171	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),172	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),173	QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),174};175 176static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {177	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),178	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),179	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),180	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),181	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),182	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),183	QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),184	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),185	QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),186	QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),187	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),188	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),189	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),190	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),191	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),192	QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),193	QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),194	QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),195	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),196	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),197	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),198	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),199	QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),200	QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),201	QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),202	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),203	QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),204	QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),205	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),206	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),207	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),208	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),209	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),210	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),211	QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),212	QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),213	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),214	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),215	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),216	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),217	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),218	QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),219	QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),220	QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),221	QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),222	QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),223};224 225static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {226	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02),227	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06),228	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),229};230 231static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {232	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),233	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),234	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),235	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),236	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61),237	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),238	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e),239	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),240	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),241	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),242	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),243	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),244	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),245	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),246	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),247	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01),248	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),249	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),250	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),251	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01),252	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),253	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),254	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),255	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),256	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),257	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),258	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),259	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),260	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),261	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),262};263 264static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {265	QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01),266	QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),267	QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),268	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),269	QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),270	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),271	QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),272};273 274static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = {275	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),276	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),277	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),278	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),279	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),280	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),281	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11),282	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),283	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),284};285 286static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {287	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),288	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),289	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),290	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),291	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),292	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),293	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),294	QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),295	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),296	QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),297	QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),298	QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),299	QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),300	QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),301	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),302	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),303	QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),304	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),305	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),306	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),307	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),308	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),309	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),310	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),311	QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),312	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),313	QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),314	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),315	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),316	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),317	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),318	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),319	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),320	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),321	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),322	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),323	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),324	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),325	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),326	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),327};328 329static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {330	QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),331	QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),332	QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),333	QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),334	QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36),335	QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),336};337 338static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {339	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),340	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),341	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),342	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),343	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),344	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),345	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),346};347 348static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {349	QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4),350	QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0),351	QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),352	QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),353	QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),354	QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),355	QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),356	QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),357	QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99),358	QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15),359	QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe),360};361 362static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = {363	QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),364	QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),365	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),366	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),367	QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),368	QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),369	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),370	QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),371	QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),372	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),373	QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),374	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),375	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),376	QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),377	QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),378	QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82),379	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03),380	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355),381	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555),382	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a),383	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a),384	QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb),385	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),386	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),387	QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0),388	QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40),389	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),390	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),391	QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),392	QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20),393	QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa),394	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),395	QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),396	QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),397	QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),398	QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa),399	QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1),400	QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68),401	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2),402	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa),403	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab),404	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),405	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34),406	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414),407	QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b),408	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),409	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),410	QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0),411	QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40),412	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),413	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),414	QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),415	QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0),416	QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),417	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),418	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),419	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),420};421 422static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = {423	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02),424	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),425	QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10),426	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06),427};428 429static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = {430	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),431	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),432	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),433	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe),434	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4),435	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),436	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),437	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),438	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),439	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),440	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),441	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),442	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),443	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),444	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),445	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),446	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01),447	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),448	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),449	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),450	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),451	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),452	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2),453	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),454	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),455	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),456	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),457	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),458	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),459	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),460};461 462static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = {463	QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83),464	QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9),465	QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42),466	QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40),467	QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01),468	QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0),469	QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1),470	QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),471	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),472	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),473	QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),474};475 476static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = {477	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0),478	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),479	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),480	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),481	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),482	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11),483	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb),484	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),485	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),486	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),487	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a),488	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6),489	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),490};491 492static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_serdes_tbl[] = {493	QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),494	QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),495	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),496	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),497	QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),498	QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),499	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),500	QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),501	QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),502	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),503	QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),504	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),505	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),506	QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),507	QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),508	QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),509	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),510	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),511	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),512	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),513	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),514	QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),515	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),516	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),517	QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00),518	QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),519	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),520	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),521	QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),522	QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20),523	QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a),524	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),525	QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),526	QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),527	QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),528	QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a),529	QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),530	QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),531	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),532	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),533	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),534	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),535	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),536	QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),537	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),538	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),539	QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00),540	QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),541	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),542	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),543	QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),544	QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),545	QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),546	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01),547	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),548	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),549	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00),550	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00),551	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),552	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),553	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),554	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),555	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),556	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),557	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),558	QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89),559	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10),560};561 562static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_serdes_tbl[] = {563	QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),564	QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),565	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),566	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),567	QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),568	QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),569	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),570	QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),571	QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),572	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),573	QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),574	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),575	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),576	QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),577	QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),578	QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),579	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),580	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),581	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),582	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),583	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),584	QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),585	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),586	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),587	QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x00),588	QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),589	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),590	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),591	QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),592	QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),593	QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0x0a),594	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),595	QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),596	QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),597	QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),598	QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0x0a),599	QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),600	QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),601	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),602	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),603	QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),604	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),605	QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),606	QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),607	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),608	QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),609	QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x00),610	QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),611	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),612	QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),613	QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),614	QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),615	QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),616	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_EN_CENTER, 0x01),617	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),618	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),619	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER1, 0x00),620	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_ADJ_PER2, 0x00),621	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),622	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),623	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),624	QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),625	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),626	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),627	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),628	QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x89),629	QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x10),630};631 632static const struct qmp_phy_init_tbl ipq9574_pcie_rx_tbl[] = {633	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),634	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),635	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),636	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61),637	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),638	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e),639	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),640	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),641	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),642	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),643	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),644	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x73),645	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x80),646	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),647	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),648	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),649	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),650	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),651	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x00),652	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),653	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),654	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),655	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),656	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),657	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x02),658	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),659	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),660	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),661	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),662	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),663};664 665static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_tbl[] = {666	QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),667	QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),668	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),669	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),670	QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),671	QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),672};673 674static const struct qmp_phy_init_tbl ipq9574_gen3x1_pcie_pcs_misc_tbl[] = {675	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),676	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),677	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),678	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),679	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),680	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),681	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x14),682	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x10),683	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0b),684	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),685	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),686	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),687	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),688	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),689	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),690	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a),691	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x06),692	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03),693	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),694};695 696static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_tbl[] = {697	QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),698	QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),699	QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),700	QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),701	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),702	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),703};704 705static const struct qmp_phy_init_tbl ipq9574_gen3x2_pcie_pcs_misc_tbl[] = {706	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),707	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),708	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),709	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),710	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),711	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),712	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x14),713	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG1, 0x10),714	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0b),715	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_PRE, 0x00),716	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_PRESET_P10_POST, 0x58),717	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),718	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG1, 0x00),719	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),720	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_CONFIG4, 0x19),721	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),722	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x49),723	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x2a),724	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x02),725	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_MODE2_CONFIG6, 0x03),726	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),727};728 729static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {730	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),731	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),732	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),733	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),734	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),735	QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),736	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),737	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),738	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),739	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),740	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),741	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),742	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),743	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),744	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),745	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),746	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),747	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),748	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),749	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),750	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),751	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),752	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),753	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),754	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),755	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),756	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),757	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),758	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),759	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),760	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),761	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),762	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),763	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),764	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),765	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),766	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),767	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),768	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),769	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),770	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),771	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),772};773 774static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {775	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),776	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),777	QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),778	QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),779};780 781static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {782	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),783	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),784	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),785	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),786	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),787	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),788	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),789	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),790	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),791	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),792	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),793	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),794	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),795	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),796	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),797	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),798};799 800static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {801	QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),802 803	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),804	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),805	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),806	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),807	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),808 809	QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),810	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),811	QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),812	QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),813	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),814	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),815	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),816 817	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),818	QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),819	QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),820 821	QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),822};823 824static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {825	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),826	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),827	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),828	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),829	QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),830};831 832static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {833	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),834	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),835	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),836	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),837	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),838	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),839	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),840	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),841	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),842	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),843	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),844	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),845	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),846	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),847	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),848	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),849	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),850	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),851	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),852	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),853	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),854	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),855	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),856	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),857	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),858	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),859	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),860	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),861	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),862	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),863	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),864	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),865	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),866	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),867	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),868	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),869	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),870	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),871	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),872	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),873	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),874	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),875	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),876	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),877	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),878};879 880static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {881	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),882	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),883	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),884	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),885	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),886	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),887	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),888	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),889	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),890	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),891	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),892	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),893	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),894	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),895	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),896	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),897	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),898	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),899	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),900	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),901	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),902	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),903	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),904	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),905	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),906	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),907	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),908	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),909	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),910	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),911	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),912	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),913	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),914	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),915	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),916	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),917	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),918	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),919	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),920	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),921	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),922	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),923	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),924	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),925	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),926	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),927	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),928	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),929	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),930	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),931	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),932	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),933	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),934	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),935	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),936	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),937};938 939static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {940	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),941	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),942	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),943	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),944	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),945	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),946	QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),947};948 949static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {950	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),951	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),952	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),953	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),954	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),955	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),956	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),957	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),958	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),959	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),960	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),961	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),962	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),963	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),964	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),965	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),966	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),967	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),968	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),969	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),970	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),971	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),972	QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),973	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),974	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),975	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),976	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),977	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),978	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),979	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),980	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),981	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),982	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),983	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),984	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),985	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),986	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),987	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),988	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),989	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),990	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),991	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),992};993 994static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {995	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),996	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),997};998 999static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {1000	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),1001	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),1002	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),1003	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),1004	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),1005	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),1006	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),1007	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),1008	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),1009	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),1010	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),1011	QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),1012	QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),1013	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),1014	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),1015	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),1016	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),1017	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),1018	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),1019	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),1020	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),1021	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),1022	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),1023	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),1024	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),1025	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),1026	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),1027	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),1028	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),1029	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),1030	QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),1031	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),1032	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),1033	QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),1034	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),1035	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),1036};1037 1038static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {1039	QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),1040	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),1041	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),1042	QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),1043	QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),1044};1045 1046static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {1047	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),1048	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),1049	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),1050	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),1051	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),1052	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),1053	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),1054};1055 1056static const struct qmp_phy_init_tbl sc8280xp_qmp_pcie_serdes_tbl[] = {1057	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00),1058	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),1059	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),1060	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),1061	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),1062	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),1063	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),1064	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),1065	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),1066	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),1067	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),1068	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),1069	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),1070	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),1071	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),1072	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),1073	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),1074	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),1075	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),1076	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),1077	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),1078	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),1079	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),1080	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),1081	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),1082	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),1083	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),1084	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),1085	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),1086	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),1087	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),1088	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),1089	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),1090	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),1091	QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),1092	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),1093	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb9),1094	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),1095	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x94),1096	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),1097	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),1098};1099 1100static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl[] = {1101	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),1102};1103 1104static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl[] = {1105	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),1106};1107 1108static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl[] = {1109	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),1110};1111 1112static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_tx_tbl[] = {1113	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),1114	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),1115	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),1116	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),1117	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),1118};1119 1120static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rx_tbl[] = {1121	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),1122	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),1123	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),1124	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),1125	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),1126	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),1127	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),1128	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),1129	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),1130	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),1131	QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),1132	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),1133	QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),1134	QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),1135	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),1136	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),1137	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),1138	QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),1139};1140 1141static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_tbl[] = {1142	QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),1143	QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),1144	QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),1145};1146 1147static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl[] = {1148	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),1149	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),1150	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),1151	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),1152};1153 1154static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_tx_tbl[] = {1155	QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1),1156	QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2),1157	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5),1158	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),1159	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11),1160	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),1161};1162 1163static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rx_tbl[] = {1164	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),1165	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),1166	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),1167	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34),1168	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),1169	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),1170	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),1171	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),1172	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),1173	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),1174	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),1175	QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),1176	QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),1177	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),1178	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),1179	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),1180	QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),1181};1182 1183static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_tbl[] = {1184	QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),1185	QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x88),1186	QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),1187	QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x0f),1188};1189 1190static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl[] = {1191	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),1192	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),1193	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),1194	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),1195};1196 1197static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_serdes_tbl[] = {1198	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26),1199	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),1200	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),1201	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),1202	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),1203	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),1204	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),1205	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),1206	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),1207	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),1208	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),1209	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),1210	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12),1211	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),1212	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),1213	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),1214	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),1215	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),1216	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),1217	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),1218	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),1219	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),1220	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),1221	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),1222	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),1223	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),1224	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),1225	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),1226	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),1227	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),1228	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40),1229	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14),1230	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),1231	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),1232	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),1233	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),1234	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46),1235	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),1236	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),1237	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),1238	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),1239	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06),1240	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88),1241	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),1242	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f),1243};1244 1245static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl[] = {1246	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x1c),1247};1248 1249static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl[] = {1250	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),1251	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x88),1252	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02),1253	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d),1254	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0xd4),1255	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),1256	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),1257	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a),1258	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x32),1259	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6),1260	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64),1261	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),1262	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),1263	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),1264	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),1265	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),1266	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),1267	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),1268	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),1269	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),1270	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b),1271};1272 1273static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_tx_tbl[] = {1274	QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),1275	QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03),1276	QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01),1277	QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x10),1278	QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51),1279	QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34),1280};1281 1282static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_rx_tbl[] = {1283	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c),1284	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04),1285	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),1286	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),1287	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),1288	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80),1289	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x00),1290	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_BKUP_CTRL1, 0x15),1291	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_1, 0x01),1292	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_2, 0x01),1293	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x45),1294	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a, 1),1295	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0b, 2),1296	QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00),1297	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),1298	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),1299	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),1300	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),1301	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x3a, 1),1302	QMP_PHY_INIT_CFG_LANE(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38, 2),1303	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39),1304	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14),1305	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3),1306	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58),1307	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),1308	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26),1309	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),1310	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),1311	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xe4),1312	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xa4),1313	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60),1314	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),1315	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x4b),1316	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),1317	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),1318	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10),1319};1320 1321static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_tbl[] = {1322	QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e),1323	QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc),1324	QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00),1325	QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22),1326	QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04),1327	QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02),1328};1329 1330static const struct qmp_phy_init_tbl x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl[] = {1331	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),1332	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00),1333	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16),1334	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02),1335	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e),1336	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03),1337	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28),1338	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27),1339	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27),1340	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0),1341	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d),1342	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x18),1343	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0x7a),1344	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0x8a),1345};1346 1347static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {1348	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),1349	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),1350	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),1351	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),1352	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),1353	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),1354	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),1355	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),1356	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),1357	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),1358	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),1359	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),1360	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),1361	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),1362	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),1363	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),1364	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),1365	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),1366	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),1367	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),1368	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),1369	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),1370	QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),1371	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),1372	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),1373	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),1374	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),1375	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),1376	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),1377	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),1378	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),1379	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),1380	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),1381	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),1382	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),1383	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),1384	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),1385	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),1386	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),1387	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),1388	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),1389};1390 1391static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {1392	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),1393};1394 1395static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {1396	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),1397	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),1398	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),1399};1400 1401static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {1402	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),1403	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),1404	QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),1405	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),1406	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),1407	QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),1408	QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),1409	QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),1410	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),1411	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),1412	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),1413	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),1414	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),1415	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),1416	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),1417	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),1418	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),1419	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),1420	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),1421	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),1422	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),1423	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),1424	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),1425	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),1426	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),1427	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),1428	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),1429	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),1430	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),1431	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),1432};1433 1434static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {1435	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),1436	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),1437	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),1438	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),1439	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),1440	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),1441};1442 1443static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {1444	QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),1445	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),1446	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),1447};1448 1449static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {1450	QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),1451	QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),1452};1453 1454static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {1455	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),1456	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),1457	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),1458	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),1459	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),1460	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),1461	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),1462};1463 1464static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {1465	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),1466	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),1467};1468 1469static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {1470	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),1471};1472 1473static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {1474	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),1475	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),1476	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),1477	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),1478};1479 1480static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {1481	QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),1482	QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),1483};1484 1485static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {1486	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),1487	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),1488};1489 1490static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {1491	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),1492	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),1493	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),1494	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),1495	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),1496	QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),1497	QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),1498	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),1499	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),1500	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),1501	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03),1502	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),1503	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),1504	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),1505};1506 1507static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_serdes_tbl[] = {1508	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),1509	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),1510	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),1511	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xce),1512	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x0b),1513	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x97),1514	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x0c),1515	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),1516	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE0, 0x0a),1517	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE1, 0x10),1518	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),1519	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),1520	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),1521	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),1522	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),1523	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),1524	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),1525	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x04),1526	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0d),1527	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x0a),1528	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1a),1529	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0xc3),1530	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0xd0),1531	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x05),1532	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55),1533	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55),1534	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05),1535	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),1536	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),1537	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),1538	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xd8),1539	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x20),1540};1541 1542static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = {1543	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),1544	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),1545	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),1546	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),1547	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),1548	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),1549	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),1550	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),1551	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),1552	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),1553	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),1554	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),1555	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),1556	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),1557	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),1558	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),1559	QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),1560	QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),1561	QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),1562	QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),1563	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),1564	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),1565	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),1566	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),1567	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),1568};1569 1570static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {1571	QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),1572	QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),1573	QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),1574	QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),1575	QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),1576};1577 1578static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {1579	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),1580	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),1581	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),1582	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),1583	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),1584	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),1585	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),1586	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),1587	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),1588	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),1589	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),1590	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),1591	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),1592	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),1593	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),1594	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),1595	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),1596	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),1597	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),1598	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),1599	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),1600	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),1601	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),1602	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),1603	QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),1604};1605 1606static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {1607	QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),1608	QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),1609	QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),1610	QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),1611};1612 1613static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {1614	QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),1615	QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),1616	QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),1617	QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),1618	QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),1619};1620 1621static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_pcs_misc_tbl[] = {1622	QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),1623	QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),1624};1625 1626static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] = {1627	QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),1628	QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),1629};1630 1631static const struct qmp_phy_init_tbl sdx65_qmp_pcie_serdes_tbl[] = {1632	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02),1633	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),1634	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07),1635	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),1636	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27),1637	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a),1638	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17),1639	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19),1640	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00),1641	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03),1642	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00),1643	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),1644	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),1645	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),1646	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04),1647	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff),1648	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09),1649	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19),1650	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28),1651	QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),1652	QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01),1653	QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),1654	QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01),1655	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),1656	QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),1657	QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),1658	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),1659	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),1660	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),1661	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),1662	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),1663	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),1664	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE_CONTD, 0x00),1665	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),1666};1667 1668static const struct qmp_phy_init_tbl sdx65_qmp_pcie_tx_tbl[] = {1669	QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),1670	QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),1671	QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x00),1672	QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_VMODE_CTRL1, 0x00),1673	QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_PI_QEC_CTRL, 0x00),1674	QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),1675	QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),1676	QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RCV_DETECT_LVL_2, 0x12),1677};1678 1679static const struct qmp_phy_init_tbl sdx65_qmp_pcie_rx_tbl[] = {1680	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),1681	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_1, 0x06),1682	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_2, 0x06),1683	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH1, 0x3e),1684	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH2, 0x1e),1685	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),1686	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),1687	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH1, 0x02),1688	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH2, 0x1d),1689	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x44),1690	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL2, 0x00),1691	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),1692	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),1693	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x74),1694	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),1695	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_ENABLES, 0x1c),1696	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_CNTRL, 0x03),1697	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_DEGLITCH_CNTRL, 0x14),1698	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x04),1699	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),1700	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),1701	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),1702	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x64),1703	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),1704	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),1705	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),1706	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DCC_CTRL1, 0x0c),1707	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),1708	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),1709	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),1710	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),1711	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),1712	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),1713	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),1714	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),1715	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),1716	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),1717	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),1718	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),1719	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),1720	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),1721	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),1722	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),1723	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE2, 0x00),1724	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),1725	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),1726	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),1727	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),1728	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xac),1729	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),1730	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),1731	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x07),1732	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),1733	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),1734	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc5),1735	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xee),1736	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),1737	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),1738	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),1739	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),1740	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),1741	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_EN_TIMER, 0x28),1742	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),1743};1744 1745static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_tbl[] = {1746	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),1747	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0xaa),1748	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG2, 0x0d),1749	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),1750	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),1751};1752 1753static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_misc_tbl[] = {1754	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),1755	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),1756	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08),1757	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2, 0x0d),1758	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),1759	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),1760	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),1761	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),1762};1763 1764static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = {1765	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),1766	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),1767	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),1768	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),1769	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),1770	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),1771	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),1772	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),1773	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),1774	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),1775	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),1776	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),1777	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),1778	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),1779	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),1780	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),1781	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),1782	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),1783	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),1784	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),1785	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),1786	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),1787	QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),1788	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),1789	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),1790	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),1791	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),1792	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),1793	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),1794	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),1795	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),1796	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),1797	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),1798	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),1799	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),1800	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),1801	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),1802	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),1803	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),1804	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),1805	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),1806};1807 1808static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_serdes_tbl[] = {1809	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),1810};1811 1812static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {1813	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),1814	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),1815	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),1816	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),1817	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),1818};1819 1820static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_rx_tbl[] = {1821	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),1822	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),1823	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),1824	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),1825	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),1826	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),1827	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),1828	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),1829	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),1830	QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),1831	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),1832	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),1833	QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),1834	QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),1835};1836 1837static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_rx_tbl[] = {1838	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),1839	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),1840	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),1841	QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),1842	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),1843	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),1844	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),1845	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),1846};1847 1848static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_pcs_tbl[] = {1849	QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),1850	QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),1851	QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),1852};1853 1854static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {1855	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),1856	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),1857	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),1858	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),1859};1860 1861static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_tx_tbl[] = {1862	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),1863	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),1864	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),1865	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),1866	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),1867};1868 1869static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_rx_tbl[] = {1870	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),1871	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),1872	QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),1873	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),1874};1875 1876static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = {1877	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),1878	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34),1879	QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),1880};1881 1882static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_tx_tbl[] = {1883	QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1),1884	QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2),1885	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5),1886	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),1887	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),1888	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),1889};1890 1891static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_pcs_tbl[] = {1892	QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x0f),1893};1894 1895static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {1896	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),1897	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),1898	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),1899	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),1900	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),1901	QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),1902	QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),1903	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),1904	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),1905	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),1906	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),1907	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),1908	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),1909};1910 1911static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_serdes_tbl[] = {1912	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),1913	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),1914	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),1915	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),1916	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),1917	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),1918	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),1919	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),1920	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),1921	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),1922	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),1923	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),1924	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),1925	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),1926	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),1927	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),1928	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),1929	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),1930	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),1931	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),1932	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),1933	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),1934	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),1935	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),1936	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),1937	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),1938	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),1939	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),1940};1941 1942static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {1943	QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),1944	QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),1945	QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),1946	QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),1947};1948 1949static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {1950	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),1951	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),1952	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),1953	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),1954	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),1955	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),1956	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),1957	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),1958	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),1959	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),1960	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),1961	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),1962	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),1963	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),1964	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),1965	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),1966	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),1967	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),1968	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),1969	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),1970	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),1971	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),1972	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),1973	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),1974 1975	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),1976 1977	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),1978 1979	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),1980	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),1981	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),1982	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),1983	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),1984	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),1985	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),1986	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),1987 1988	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),1989	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),1990	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),1991	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),1992	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),1993	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),1994	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),1995	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),1996	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),1997};1998 1999static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {2000	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),2001	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),2002	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),2003	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x99),2004};2005 2006static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {2007	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),2008	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),2009	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),2010	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),2011};2012 2013static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl[] = {2014	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),2015	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),2016	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_PRESET_P10_POST, 0x00),2017};2018 2019static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_serdes_tbl[] = {2020	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02),2021	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07),2022	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27),2023	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a),2024	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17),2025	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19),2026	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00),2027	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03),2028	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00),2029	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),2030	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04),2031	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff),2032	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09),2033	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19),2034	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28),2035	QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),2036	QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01),2037	QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),2038	QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01),2039	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),2040};2041 2042static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = {2043	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08),2044};2045 2046static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_serdes_tbl[] = {2047	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),2048	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),2049	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),2050	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),2051	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),2052	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x93),2053	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01),2054	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),2055	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),2056	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07),2057	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),2058	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),2059	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),2060	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),2061	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),2062	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),2063	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),2064	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),2065	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42),2066	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),2067	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),2068	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),2069	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),2070	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),2071	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x34),2072	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),2073	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),2074	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),2075	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),2076	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55),2077	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01),2078	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),2079	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),2080	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),2081	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),2082	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),2083	QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f),2084	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),2085};2086 2087static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_tx_tbl[] = {2088	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x15),2089	QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),2090	QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x02),2091	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x06),2092	QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x18),2093};2094 2095static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_rx_tbl[] = {2096	QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),2097	QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x11),2098	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf),2099	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf),2100	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7),2101	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea),2102	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f),2103	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),2104	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),2105	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a),2106	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89),2107	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),2108	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94),2109	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b),2110	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a),2111	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89),2112	QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0x00),2113	QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09),2114	QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05),2115	QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),2116	QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),2117	QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),2118	QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x1c),2119	QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),2120	QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),2121};2122 2123static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_tbl[] = {2124	QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x05),2125	QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x77),2126	QMP_PHY_INIT_CFG(QPHY_V6_PCS_RATE_SLEW_CNTRL1, 0x0b),2127	QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG2, 0x0f),2128	QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x8c),2129};2130 2131static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_misc_tbl[] = {2132	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1, 0x1e),2133	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME, 0x27),2134	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),2135	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),2136	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),2137	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),2138};2139 2140static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_serdes_tbl[] = {2141	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26),2142	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),2143	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),2144	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),2145	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),2146	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),2147	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),2148	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),2149	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),2150	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),2151	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),2152	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),2153	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12),2154	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),2155	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),2156	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),2157	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),2158	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),2159	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),2160	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),2161	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),2162	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),2163	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),2164	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),2165	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),2166	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),2167	QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),2168	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),2169	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),2170	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),2171	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40),2172	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14),2173	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),2174	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),2175	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),2176	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),2177	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46),2178	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),2179	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),2180	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),2181	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),2182	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06),2183	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88),2184	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),2185	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f),2186};2187 2188static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = {2189	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),2190	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00),2191	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x02),2192	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x0d),2193	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12),2194	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),2195	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),2196	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a),2197	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38),2198	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6),2199	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64),2200	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),2201	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),2202	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),2203	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),2204	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),2205	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),2206	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),2207	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),2208	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),2209	QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE, 0x5b),2210};2211 2212static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = {2213	QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),2214	QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03),2215	QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01),2216	QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x00),2217	QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51),2218	QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34),2219};2220 2221static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = {2222	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0c),2223	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),2224	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_GAIN_RATE_2, 0x04),2225	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),2226	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),2227	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80),2228	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c),2229	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05),2230	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_TX_ADPT_CTRL, 0x10),2231	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a),2232	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),2233	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),2234	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),2235	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),2236	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),2237	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),2238	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14),2239	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3),2240	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58),2241	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),2242	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26),2243	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),2244	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),2245	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xdb),2246	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xdb),2247	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0xa0),2248	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),2249	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78),2250	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),2251	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),2252	QMP_PHY_INIT_CFG(QSERDES_V6_20_VGA_CAL_CNTRL1, 0x00),2253};2254 2255static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = {2256	QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB, 0x17),2257	QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e),2258	QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_RX_SIGDET_LVL, 0xcc),2259	QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00),2260	QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22),2261	QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04),2262	QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02),2263};2264 2265static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_misc_tbl[] = {2266	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),2267	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00),2268	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16),2269	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_RXEQEVAL_TIME, 0x27),2270	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_RXEQEVAL_TIME, 0x27),2271	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02),2272	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e),2273	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03),2274	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28),2275	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0),2276	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d),2277	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f),2278	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2),2279	QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2),2280};2281 2282static const struct qmp_phy_init_tbl sm8650_qmp_gen4x2_pcie_rx_tbl[] = {2283	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a),2284	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),2285	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),2286	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),2287	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x82),2288	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05),2289	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a),2290	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),2291	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),2292	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),2293	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),2294	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),2295	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0xd3),2296	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xd3),2297	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x00),2298	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),2299	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x06),2300	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),2301	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),2302	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0x23),2303	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0x9b),2304	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0x60),2305	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),2306	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x43),2307	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),2308	QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),2309};2310 2311static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl[] = {2312	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),2313	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),2314	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),2315	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),2316	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),2317	QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),2318	QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),2319	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),2320	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),2321	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),2322	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),2323	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),2324	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),2325	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),2326};2327 2328static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl[] = {2329	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00),2330	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),2331	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),2332	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),2333	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),2334	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),2335	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),2336	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),2337	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),2338	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),2339	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),2340	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),2341	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),2342	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),2343	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),2344	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),2345	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),2346	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),2347	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),2348	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),2349	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),2350	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),2351	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),2352	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),2353	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),2354	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),2355	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),2356	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),2357};2358 2359static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rx_alt_tbl[] = {2360	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),2361	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),2362	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9a),2363	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0),2364	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x92),2365	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0),2366	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42),2367	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x99),2368	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),2369	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9a),2370	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xfb),2371	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0x92),2372	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xec),2373	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43),2374	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd),2375	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),2376	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3),2377	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf8),2378	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xec),2379	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd6),2380	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83),2381	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf5),2382	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x5e),2383	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),2384	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),2385	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),2386	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00),2387	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),2388	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),2389	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),2390	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),2391	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),2392	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),2393	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),2394	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),2395	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),2396	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),2397	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),2398	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08),2399	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04),2400	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04),2401	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08),2402	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),2403	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c),2404	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),2405	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),2406	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05),2407	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),2408	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),2409};2410 2411static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_tx_tbl[] = {2412	QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),2413	QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x07),2414	QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),2415	QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),2416	QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x0f),2417};2418 2419static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_pcs_misc_tbl[] = {2420	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),2421	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),2422	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),2423	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),2424};2425 2426static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl[] = {2427	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),2428	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),2429	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),2430};2431 2432static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl[] = {2433	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),2434	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),2435	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),2436	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),2437	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),2438	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66),2439};2440 2441static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rx_alt_tbl[] = {2442	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),2443	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),2444	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00),2445	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),2446	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),2447	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05),2448	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),2449	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),2450	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c),2451	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),2452	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),2453	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),2454	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),2455	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),2456	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),2457	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),2458	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),2459	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),2460	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),2461	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),2462	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x99),2463	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0),2464	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x92),2465	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0),2466	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42),2467	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00),2468	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20),2469	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9a),2470	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xb6),2471	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0x92),2472	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xf0),2473	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43),2474	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd),2475	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),2476	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3),2477	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf6),2478	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xee),2479	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd2),2480	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83),2481	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf9),2482	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x3d),2483	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),2484	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),2485	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),2486	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08),2487	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04),2488	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),2489	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04),2490	QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08),2491};2492 2493static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl[] = {2494	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),2495	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),2496	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),2497	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66),2498};2499 2500static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl[] = {2501	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),2502	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),2503	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),2504	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),2505	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),2506	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),2507	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),2508	QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),2509	QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),2510	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),2511	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),2512	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),2513	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),2514	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),2515	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),2516	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),2517};2518 2519 2520static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl[] = {2521	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00),2522	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),2523	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),2524	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),2525	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),2526	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),2527	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),2528	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),2529	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),2530	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),2531	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),2532	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),2533	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),2534	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),2535	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),2536	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),2537	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),2538	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),2539	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),2540	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),2541	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),2542	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),2543	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),2544	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),2545	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),2546	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),2547};2548 2549static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl[] = {2550	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02),2551	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07),2552	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27),2553	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a),2554	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17),2555	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19),2556	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00),2557	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03),2558	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00),2559	QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),2560	QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01),2561	QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),2562	QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01),2563	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),2564	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),2565	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04),2566	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff),2567	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09),2568	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19),2569	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28),2570};2571 2572static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl[] = {2573	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_MX_CTRL7, 0x00),2574	QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_INSIG_SW_CTRL7, 0x00),2575};2576 2577struct qmp_pcie_offsets {2578	u16 serdes;2579	u16 pcs;2580	u16 pcs_misc;2581	u16 tx;2582	u16 rx;2583	u16 tx2;2584	u16 rx2;2585	u16 ln_shrd;2586};2587 2588struct qmp_phy_cfg_tbls {2589	const struct qmp_phy_init_tbl *serdes;2590	int serdes_num;2591	const struct qmp_phy_init_tbl *tx;2592	int tx_num;2593	const struct qmp_phy_init_tbl *rx;2594	int rx_num;2595	const struct qmp_phy_init_tbl *pcs;2596	int pcs_num;2597	const struct qmp_phy_init_tbl *pcs_misc;2598	int pcs_misc_num;2599	const struct qmp_phy_init_tbl *ln_shrd;2600	int ln_shrd_num;2601};2602 2603/* struct qmp_phy_cfg - per-PHY initialization config */2604struct qmp_phy_cfg {2605	int lanes;2606 2607	const struct qmp_pcie_offsets *offsets;2608 2609	/* Main init sequence for PHY blocks - serdes, tx, rx, pcs */2610	const struct qmp_phy_cfg_tbls tbls;2611	/*2612	 * Additional init sequences for PHY blocks, providing additional2613	 * register programming. They are used for providing separate sequences2614	 * for the Root Complex and End Point use cases.2615	 *2616	 * If EP mode is not supported, both tables can be left unset.2617	 */2618	const struct qmp_phy_cfg_tbls *tbls_rc;2619	const struct qmp_phy_cfg_tbls *tbls_ep;2620 2621	const struct qmp_phy_init_tbl *serdes_4ln_tbl;2622	int serdes_4ln_num;2623 2624	/* resets to be requested */2625	const char * const *reset_list;2626	int num_resets;2627	/* regulators to be requested */2628	const char * const *vreg_list;2629	int num_vregs;2630 2631	/* array of registers with different offsets */2632	const unsigned int *regs;2633 2634	unsigned int pwrdn_ctrl;2635	/* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */2636	unsigned int phy_status;2637 2638	bool skip_start_delay;2639 2640	bool has_nocsr_reset;2641 2642	/* QMP PHY pipe clock interface rate */2643	unsigned long pipe_clock_rate;2644 2645	/* QMP PHY AUX clock interface rate */2646	unsigned long aux_clock_rate;2647};2648 2649struct qmp_pcie {2650	struct device *dev;2651 2652	const struct qmp_phy_cfg *cfg;2653	bool tcsr_4ln_config;2654 2655	void __iomem *serdes;2656	void __iomem *pcs;2657	void __iomem *pcs_misc;2658	void __iomem *tx;2659	void __iomem *rx;2660	void __iomem *tx2;2661	void __iomem *rx2;2662	void __iomem *ln_shrd;2663 2664	void __iomem *port_b;2665 2666	struct clk_bulk_data *clks;2667	struct clk_bulk_data pipe_clks[2];2668	int num_pipe_clks;2669 2670	struct reset_control_bulk_data *resets;2671	struct reset_control *nocsr_reset;2672	struct regulator_bulk_data *vregs;2673 2674	struct phy *phy;2675	int mode;2676 2677	struct clk_fixed_rate pipe_clk_fixed;2678	struct clk_fixed_rate aux_clk_fixed;2679};2680 2681static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)2682{2683	u32 reg;2684 2685	reg = readl(base + offset);2686	reg |= val;2687	writel(reg, base + offset);2688 2689	/* ensure that above write is through */2690	readl(base + offset);2691}2692 2693static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)2694{2695	u32 reg;2696 2697	reg = readl(base + offset);2698	reg &= ~val;2699	writel(reg, base + offset);2700 2701	/* ensure that above write is through */2702	readl(base + offset);2703}2704 2705/* list of clocks required by phy */2706static const char * const qmp_pciephy_clk_l[] = {2707	"aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux",2708};2709 2710/* list of regulators */2711static const char * const qmp_phy_vreg_l[] = {2712	"vdda-phy", "vdda-pll",2713};2714 2715static const char * const sm8550_qmp_phy_vreg_l[] = {2716	"vdda-phy", "vdda-pll", "vdda-qref",2717};2718 2719/* list of resets */2720static const char * const ipq8074_pciephy_reset_l[] = {2721	"phy", "common",2722};2723 2724static const char * const sdm845_pciephy_reset_l[] = {2725	"phy",2726};2727 2728static const struct qmp_pcie_offsets qmp_pcie_offsets_qhp = {2729	.serdes		= 0,2730	.pcs		= 0x1800,2731	.tx		= 0x0800,2732	/* no .rx for QHP */2733};2734 2735static const struct qmp_pcie_offsets qmp_pcie_offsets_v2 = {2736	.serdes		= 0,2737	.pcs		= 0x0800,2738	.tx		= 0x0200,2739	.rx		= 0x0400,2740};2741 2742static const struct qmp_pcie_offsets qmp_pcie_offsets_v3 = {2743	.serdes		= 0,2744	.pcs		= 0x0800,2745	.pcs_misc	= 0x0600,2746	.tx		= 0x0200,2747	.rx		= 0x0400,2748};2749 2750static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = {2751	.serdes		= 0,2752	.pcs		= 0x0800,2753	.pcs_misc	= 0x0c00,2754	.tx		= 0x0200,2755	.rx		= 0x0400,2756};2757 2758static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = {2759	.serdes		= 0,2760	.pcs		= 0x0a00,2761	.pcs_misc	= 0x0e00,2762	.tx		= 0x0200,2763	.rx		= 0x0400,2764	.tx2		= 0x0600,2765	.rx2		= 0x0800,2766};2767 2768static const struct qmp_pcie_offsets qmp_pcie_offsets_v4_20 = {2769	.serdes		= 0x1000,2770	.pcs		= 0x1200,2771	.pcs_misc	= 0x1600,2772	.tx		= 0x0000,2773	.rx		= 0x0200,2774	.tx2		= 0x0800,2775	.rx2		= 0x0a00,2776};2777 2778static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = {2779	.serdes		= 0,2780	.pcs		= 0x0200,2781	.pcs_misc	= 0x0600,2782	.tx		= 0x0e00,2783	.rx		= 0x1000,2784	.tx2		= 0x1600,2785	.rx2		= 0x1800,2786};2787 2788static const struct qmp_pcie_offsets qmp_pcie_offsets_ipq9574 = {2789	.serdes         = 0,2790	.pcs            = 0x1000,2791	.pcs_misc       = 0x1400,2792	.tx             = 0x0200,2793	.rx             = 0x0400,2794	.tx2            = 0x0600,2795	.rx2            = 0x0800,2796};2797 2798static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_20 = {2799	.serdes		= 0x1000,2800	.pcs		= 0x1200,2801	.pcs_misc	= 0x1400,2802	.tx		= 0x0000,2803	.rx		= 0x0200,2804	.tx2		= 0x0800,2805	.rx2		= 0x0a00,2806};2807 2808static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_30 = {2809	.serdes		= 0x2000,2810	.pcs		= 0x2200,2811	.pcs_misc	= 0x2400,2812	.tx		= 0x0,2813	.rx		= 0x0200,2814	.tx2		= 0x3800,2815	.rx2		= 0x3a00,2816};2817 2818static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = {2819	.serdes		= 0x1000,2820	.pcs		= 0x1200,2821	.pcs_misc	= 0x1400,2822	.tx		= 0x0000,2823	.rx		= 0x0200,2824	.tx2		= 0x0800,2825	.rx2		= 0x0a00,2826	.ln_shrd	= 0x0e00,2827};2828 2829static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {2830	.lanes			= 1,2831 2832	.offsets		= &qmp_pcie_offsets_v2,2833 2834	.tbls = {2835		.serdes		= ipq8074_pcie_serdes_tbl,2836		.serdes_num	= ARRAY_SIZE(ipq8074_pcie_serdes_tbl),2837		.tx		= ipq8074_pcie_tx_tbl,2838		.tx_num		= ARRAY_SIZE(ipq8074_pcie_tx_tbl),2839		.rx		= ipq8074_pcie_rx_tbl,2840		.rx_num		= ARRAY_SIZE(ipq8074_pcie_rx_tbl),2841		.pcs		= ipq8074_pcie_pcs_tbl,2842		.pcs_num	= ARRAY_SIZE(ipq8074_pcie_pcs_tbl),2843	},2844	.reset_list		= ipq8074_pciephy_reset_l,2845	.num_resets		= ARRAY_SIZE(ipq8074_pciephy_reset_l),2846	.vreg_list		= NULL,2847	.num_vregs		= 0,2848	.regs			= pciephy_v2_regs_layout,2849 2850	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,2851	.phy_status		= PHYSTATUS,2852};2853 2854static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {2855	.lanes			= 1,2856 2857	.offsets		= &qmp_pcie_offsets_v4x1,2858 2859	.tbls = {2860		.serdes		= ipq8074_pcie_gen3_serdes_tbl,2861		.serdes_num	= ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl),2862		.tx		= ipq8074_pcie_gen3_tx_tbl,2863		.tx_num		= ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),2864		.rx		= ipq8074_pcie_gen3_rx_tbl,2865		.rx_num		= ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl),2866		.pcs		= ipq8074_pcie_gen3_pcs_tbl,2867		.pcs_num	= ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl),2868		.pcs_misc	= ipq8074_pcie_gen3_pcs_misc_tbl,2869		.pcs_misc_num	= ARRAY_SIZE(ipq8074_pcie_gen3_pcs_misc_tbl),2870	},2871	.reset_list		= ipq8074_pciephy_reset_l,2872	.num_resets		= ARRAY_SIZE(ipq8074_pciephy_reset_l),2873	.vreg_list		= NULL,2874	.num_vregs		= 0,2875	.regs			= pciephy_v4_regs_layout,2876 2877	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,2878	.phy_status		= PHYSTATUS,2879 2880	.pipe_clock_rate	= 250000000,2881};2882 2883static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {2884	.lanes			= 1,2885 2886	.offsets		= &qmp_pcie_offsets_v4x1,2887 2888	.tbls = {2889		.serdes		= ipq6018_pcie_serdes_tbl,2890		.serdes_num	= ARRAY_SIZE(ipq6018_pcie_serdes_tbl),2891		.tx		= ipq6018_pcie_tx_tbl,2892		.tx_num		= ARRAY_SIZE(ipq6018_pcie_tx_tbl),2893		.rx		= ipq6018_pcie_rx_tbl,2894		.rx_num		= ARRAY_SIZE(ipq6018_pcie_rx_tbl),2895		.pcs		= ipq6018_pcie_pcs_tbl,2896		.pcs_num	= ARRAY_SIZE(ipq6018_pcie_pcs_tbl),2897		.pcs_misc	= ipq6018_pcie_pcs_misc_tbl,2898		.pcs_misc_num	= ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl),2899	},2900	.reset_list		= ipq8074_pciephy_reset_l,2901	.num_resets		= ARRAY_SIZE(ipq8074_pciephy_reset_l),2902	.vreg_list		= NULL,2903	.num_vregs		= 0,2904	.regs			= pciephy_v4_regs_layout,2905 2906	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,2907	.phy_status		= PHYSTATUS,2908};2909 2910static const struct qmp_phy_cfg ipq9574_gen3x1_pciephy_cfg = {2911	.lanes			= 1,2912 2913	.offsets		= &qmp_pcie_offsets_v4x1,2914 2915	.tbls = {2916		.serdes		= ipq9574_gen3x1_pcie_serdes_tbl,2917		.serdes_num	= ARRAY_SIZE(ipq9574_gen3x1_pcie_serdes_tbl),2918		.tx		= ipq8074_pcie_gen3_tx_tbl,2919		.tx_num		= ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),2920		.rx		= ipq9574_pcie_rx_tbl,2921		.rx_num		= ARRAY_SIZE(ipq9574_pcie_rx_tbl),2922		.pcs		= ipq9574_gen3x1_pcie_pcs_tbl,2923		.pcs_num	= ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_tbl),2924		.pcs_misc	= ipq9574_gen3x1_pcie_pcs_misc_tbl,2925		.pcs_misc_num	= ARRAY_SIZE(ipq9574_gen3x1_pcie_pcs_misc_tbl),2926	},2927	.reset_list		= ipq8074_pciephy_reset_l,2928	.num_resets		= ARRAY_SIZE(ipq8074_pciephy_reset_l),2929	.vreg_list		= NULL,2930	.num_vregs		= 0,2931	.regs			= pciephy_v4_regs_layout,2932 2933	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,2934	.phy_status		= PHYSTATUS,2935	.pipe_clock_rate	= 250000000,2936};2937 2938static const struct qmp_phy_cfg ipq9574_gen3x2_pciephy_cfg = {2939	.lanes			= 2,2940 2941	.offsets		= &qmp_pcie_offsets_ipq9574,2942 2943	.tbls = {2944		.serdes		= ipq9574_gen3x2_pcie_serdes_tbl,2945		.serdes_num	= ARRAY_SIZE(ipq9574_gen3x2_pcie_serdes_tbl),2946		.tx		= ipq8074_pcie_gen3_tx_tbl,2947		.tx_num		= ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),2948		.rx		= ipq9574_pcie_rx_tbl,2949		.rx_num		= ARRAY_SIZE(ipq9574_pcie_rx_tbl),2950		.pcs		= ipq9574_gen3x2_pcie_pcs_tbl,2951		.pcs_num	= ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_tbl),2952		.pcs_misc	= ipq9574_gen3x2_pcie_pcs_misc_tbl,2953		.pcs_misc_num	= ARRAY_SIZE(ipq9574_gen3x2_pcie_pcs_misc_tbl),2954	},2955	.reset_list		= ipq8074_pciephy_reset_l,2956	.num_resets		= ARRAY_SIZE(ipq8074_pciephy_reset_l),2957	.vreg_list		= NULL,2958	.num_vregs		= 0,2959	.regs			= pciephy_v5_regs_layout,2960 2961	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,2962	.phy_status		= PHYSTATUS,2963	.pipe_clock_rate	= 250000000,2964};2965 2966static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {2967	.lanes			= 1,2968 2969	.offsets		= &qmp_pcie_offsets_v3,2970 2971	.tbls = {2972		.serdes		= sdm845_qmp_pcie_serdes_tbl,2973		.serdes_num	= ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),2974		.tx		= sdm845_qmp_pcie_tx_tbl,2975		.tx_num		= ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),2976		.rx		= sdm845_qmp_pcie_rx_tbl,2977		.rx_num		= ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),2978		.pcs		= sdm845_qmp_pcie_pcs_tbl,2979		.pcs_num	= ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),2980		.pcs_misc	= sdm845_qmp_pcie_pcs_misc_tbl,2981		.pcs_misc_num	= ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),2982	},2983	.reset_list		= sdm845_pciephy_reset_l,2984	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),2985	.vreg_list		= qmp_phy_vreg_l,2986	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),2987	.regs			= pciephy_v3_regs_layout,2988 2989	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,2990	.phy_status		= PHYSTATUS,2991};2992 2993static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {2994	.lanes			= 1,2995 2996	.offsets		= &qmp_pcie_offsets_qhp,2997 2998	.tbls = {2999		.serdes		= sdm845_qhp_pcie_serdes_tbl,3000		.serdes_num	= ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),3001		.tx		= sdm845_qhp_pcie_tx_tbl,3002		.tx_num		= ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),3003		.pcs		= sdm845_qhp_pcie_pcs_tbl,3004		.pcs_num	= ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),3005	},3006	.reset_list		= sdm845_pciephy_reset_l,3007	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),3008	.vreg_list		= qmp_phy_vreg_l,3009	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),3010	.regs			= sdm845_qhp_pciephy_regs_layout,3011 3012	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,3013	.phy_status		= PHYSTATUS,3014};3015 3016static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {3017	.lanes			= 1,3018 3019	.offsets		= &qmp_pcie_offsets_v4x1,3020 3021	.tbls = {3022		.serdes		= sm8250_qmp_pcie_serdes_tbl,3023		.serdes_num	= ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),3024		.tx		= sm8250_qmp_pcie_tx_tbl,3025		.tx_num		= ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),3026		.rx		= sm8250_qmp_pcie_rx_tbl,3027		.rx_num		= ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),3028		.pcs		= sm8250_qmp_pcie_pcs_tbl,3029		.pcs_num	= ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),3030		.pcs_misc	= sm8250_qmp_pcie_pcs_misc_tbl,3031		.pcs_misc_num	= ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),3032	},3033	.tbls_rc = &(const struct qmp_phy_cfg_tbls) {3034		.serdes		= sm8250_qmp_gen3x1_pcie_serdes_tbl,3035		.serdes_num	= ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),3036		.rx		= sm8250_qmp_gen3x1_pcie_rx_tbl,3037		.rx_num		= ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),3038		.pcs		= sm8250_qmp_gen3x1_pcie_pcs_tbl,3039		.pcs_num	= ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),3040		.pcs_misc	= sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,3041		.pcs_misc_num	= ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),3042	},3043	.reset_list		= sdm845_pciephy_reset_l,3044	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),3045	.vreg_list		= qmp_phy_vreg_l,3046	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),3047	.regs			= pciephy_v4_regs_layout,3048 3049	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,3050	.phy_status		= PHYSTATUS,3051};3052 3053static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {3054	.lanes			= 2,3055 3056	.offsets		= &qmp_pcie_offsets_v4x2,3057 3058	.tbls = {3059		.serdes		= sm8250_qmp_pcie_serdes_tbl,3060		.serdes_num	= ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),3061		.tx		= sm8250_qmp_pcie_tx_tbl,3062		.tx_num		= ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),3063		.rx		= sm8250_qmp_pcie_rx_tbl,3064		.rx_num		= ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),3065		.pcs		= sm8250_qmp_pcie_pcs_tbl,3066		.pcs_num	= ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),3067		.pcs_misc	= sm8250_qmp_pcie_pcs_misc_tbl,3068		.pcs_misc_num	= ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),3069	},3070	.tbls_rc = &(const struct qmp_phy_cfg_tbls) {3071		.tx		= sm8250_qmp_gen3x2_pcie_tx_tbl,3072		.tx_num		= ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),3073		.rx		= sm8250_qmp_gen3x2_pcie_rx_tbl,3074		.rx_num		= ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),3075		.pcs		= sm8250_qmp_gen3x2_pcie_pcs_tbl,3076		.pcs_num	= ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),3077		.pcs_misc	= sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,3078		.pcs_misc_num	= ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),3079	},3080	.reset_list		= sdm845_pciephy_reset_l,3081	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),3082	.vreg_list		= qmp_phy_vreg_l,3083	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),3084	.regs			= pciephy_v4_regs_layout,3085 3086	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,3087	.phy_status		= PHYSTATUS,3088};3089 3090static const struct qmp_phy_cfg msm8998_pciephy_cfg = {3091	.lanes			= 1,3092 3093	.offsets		= &qmp_pcie_offsets_v3,3094 3095	.tbls = {3096		.serdes		= msm8998_pcie_serdes_tbl,3097		.serdes_num	= ARRAY_SIZE(msm8998_pcie_serdes_tbl),3098		.tx		= msm8998_pcie_tx_tbl,3099		.tx_num		= ARRAY_SIZE(msm8998_pcie_tx_tbl),3100		.rx		= msm8998_pcie_rx_tbl,3101		.rx_num		= ARRAY_SIZE(msm8998_pcie_rx_tbl),3102		.pcs		= msm8998_pcie_pcs_tbl,3103		.pcs_num	= ARRAY_SIZE(msm8998_pcie_pcs_tbl),3104	},3105	.reset_list		= ipq8074_pciephy_reset_l,3106	.num_resets		= ARRAY_SIZE(ipq8074_pciephy_reset_l),3107	.vreg_list		= qmp_phy_vreg_l,3108	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),3109	.regs			= pciephy_v3_regs_layout,3110 3111	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,3112	.phy_status		= PHYSTATUS,3113 3114	.skip_start_delay	= true,3115};3116 3117static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {3118	.lanes			= 2,3119 3120	.offsets		= &qmp_pcie_offsets_v4x2,3121 3122	.tbls = {3123		.serdes		= sc8180x_qmp_pcie_serdes_tbl,3124		.serdes_num	= ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),3125		.tx		= sc8180x_qmp_pcie_tx_tbl,3126		.tx_num		= ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),3127		.rx		= sc8180x_qmp_pcie_rx_tbl,3128		.rx_num		= ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),3129		.pcs		= sc8180x_qmp_pcie_pcs_tbl,3130		.pcs_num	= ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),3131		.pcs_misc	= sc8180x_qmp_pcie_pcs_misc_tbl,3132		.pcs_misc_num	= ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),3133	},3134	.reset_list		= sdm845_pciephy_reset_l,3135	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),3136	.vreg_list		= qmp_phy_vreg_l,3137	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),3138	.regs			= pciephy_v4_regs_layout,3139 3140	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,3141	.phy_status		= PHYSTATUS,3142};3143 3144static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = {3145	.lanes			= 1,3146 3147	.offsets		= &qmp_pcie_offsets_v5,3148 3149	.tbls = {3150		.serdes		= sc8280xp_qmp_pcie_serdes_tbl,3151		.serdes_num	= ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),3152		.tx		= sc8280xp_qmp_gen3x1_pcie_tx_tbl,3153		.tx_num		= ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_tx_tbl),3154		.rx		= sc8280xp_qmp_gen3x1_pcie_rx_tbl,3155		.rx_num		= ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rx_tbl),3156		.pcs		= sc8280xp_qmp_gen3x1_pcie_pcs_tbl,3157		.pcs_num	= ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_tbl),3158		.pcs_misc	= sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl,3159		.pcs_misc_num	= ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl),3160	},3161 3162	.tbls_rc = &(const struct qmp_phy_cfg_tbls) {3163		.serdes		= sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl,3164		.serdes_num	= ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl),3165	},3166 3167	.reset_list		= sdm845_pciephy_reset_l,3168	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),3169	.vreg_list		= qmp_phy_vreg_l,3170	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),3171	.regs			= pciephy_v5_regs_layout,3172 3173	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,3174	.phy_status		= PHYSTATUS,3175};3176 3177static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = {3178	.lanes			= 2,3179 3180	.offsets		= &qmp_pcie_offsets_v5,3181 3182	.tbls = {3183		.serdes		= sc8280xp_qmp_pcie_serdes_tbl,3184		.serdes_num	= ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),3185		.tx		= sc8280xp_qmp_gen3x2_pcie_tx_tbl,3186		.tx_num		= ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl),3187		.rx		= sc8280xp_qmp_gen3x2_pcie_rx_tbl,3188		.rx_num		= ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl),3189		.pcs		= sc8280xp_qmp_gen3x2_pcie_pcs_tbl,3190		.pcs_num	= ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl),3191		.pcs_misc	= sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,3192		.pcs_misc_num	= ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),3193	},3194 3195	.tbls_rc = &(const struct qmp_phy_cfg_tbls) {3196		.serdes		= sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl,3197		.serdes_num	= ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl),3198	},3199 3200	.reset_list		= sdm845_pciephy_reset_l,3201	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),3202	.vreg_list		= qmp_phy_vreg_l,3203	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),3204	.regs			= pciephy_v5_regs_layout,3205 3206	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,3207	.phy_status		= PHYSTATUS,3208};3209 3210static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = {3211	.lanes			= 4,3212 3213	.offsets		= &qmp_pcie_offsets_v5,3214 3215	.tbls = {3216		.serdes		= sc8280xp_qmp_pcie_serdes_tbl,3217		.serdes_num	= ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),3218		.tx		= sc8280xp_qmp_gen3x2_pcie_tx_tbl,3219		.tx_num		= ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl),3220		.rx		= sc8280xp_qmp_gen3x2_pcie_rx_tbl,3221		.rx_num		= ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl),3222		.pcs		= sc8280xp_qmp_gen3x2_pcie_pcs_tbl,3223		.pcs_num	= ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl),3224		.pcs_misc	= sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,3225		.pcs_misc_num	= ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),3226	},3227 3228	.tbls_rc = &(const struct qmp_phy_cfg_tbls) {3229		.serdes		= sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl,3230		.serdes_num	= ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl),3231	},3232 3233	.serdes_4ln_tbl		= sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl,3234	.serdes_4ln_num		= ARRAY_SIZE(sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl),3235 3236	.reset_list		= sdm845_pciephy_reset_l,3237	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),3238	.vreg_list		= qmp_phy_vreg_l,3239	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),3240	.regs			= pciephy_v5_regs_layout,3241 3242	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,3243	.phy_status		= PHYSTATUS,3244};3245 3246static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {3247	.lanes			= 2,3248 3249	.offsets		= &qmp_pcie_offsets_v4_20,3250 3251	.tbls = {3252		.serdes		= sdx55_qmp_pcie_serdes_tbl,3253		.serdes_num	= ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),3254		.tx		= sdx55_qmp_pcie_tx_tbl,3255		.tx_num		= ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),3256		.rx		= sdx55_qmp_pcie_rx_tbl,3257		.rx_num		= ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),3258		.pcs		= sdx55_qmp_pcie_pcs_tbl,3259		.pcs_num	= ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),3260		.pcs_misc	= sdx55_qmp_pcie_pcs_misc_tbl,3261		.pcs_misc_num	= ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),3262	},3263 3264	.tbls_rc = &(const struct qmp_phy_cfg_tbls) {3265		.serdes		= sdx55_qmp_pcie_rc_serdes_tbl,3266		.serdes_num	= ARRAY_SIZE(sdx55_qmp_pcie_rc_serdes_tbl),3267		.pcs_misc	= sdx55_qmp_pcie_rc_pcs_misc_tbl,3268		.pcs_misc_num	= ARRAY_SIZE(sdx55_qmp_pcie_rc_pcs_misc_tbl),3269	},3270 3271	.tbls_ep = &(const struct qmp_phy_cfg_tbls) {3272		.serdes		= sdx55_qmp_pcie_ep_serdes_tbl,3273		.serdes_num	= ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl),3274		.pcs_misc	= sdx55_qmp_pcie_ep_pcs_misc_tbl,3275		.pcs_misc_num	= ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_misc_tbl),3276	},3277 3278	.reset_list		= sdm845_pciephy_reset_l,3279	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),3280	.vreg_list		= qmp_phy_vreg_l,3281	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),3282	.regs			= pciephy_v4_regs_layout,3283 3284	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,3285	.phy_status		= PHYSTATUS_4_20,3286};3287 3288static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = {3289	.lanes			= 1,3290 3291	.offsets		= &qmp_pcie_offsets_v5,3292 3293	.tbls = {3294		.serdes		= sm8450_qmp_gen3_pcie_serdes_tbl,3295		.serdes_num	= ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),3296		.tx		= sm8350_qmp_gen3x1_pcie_tx_tbl,3297		.tx_num		= ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl),3298		.rx		= sm8450_qmp_gen3_pcie_rx_tbl,3299		.rx_num		= ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),3300		.pcs		= sm8450_qmp_gen3_pcie_pcs_tbl,3301		.pcs_num	= ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),3302		.pcs_misc	= sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,3303		.pcs_misc_num	= ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),3304	},3305 3306	.tbls_rc = &(const struct qmp_phy_cfg_tbls) {3307		.serdes		= sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,3308		.serdes_num	= ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),3309		.rx		= sm8350_qmp_gen3x1_pcie_rc_rx_tbl,3310		.rx_num		= ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl),3311	},3312 3313	.reset_list		= sdm845_pciephy_reset_l,3314	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),3315	.vreg_list		= qmp_phy_vreg_l,3316	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),3317	.regs			= pciephy_v5_regs_layout,3318 3319	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,3320	.phy_status		= PHYSTATUS,3321};3322 3323static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = {3324	.lanes			= 2,3325 3326	.offsets		= &qmp_pcie_offsets_v5,3327 3328	.tbls = {3329		.serdes		= sm8450_qmp_gen3_pcie_serdes_tbl,3330		.serdes_num	= ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),3331		.tx		= sm8350_qmp_gen3x2_pcie_tx_tbl,3332		.tx_num		= ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_tx_tbl),3333		.rx		= sm8450_qmp_gen3_pcie_rx_tbl,3334		.rx_num		= ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),3335		.pcs		= sm8450_qmp_gen3_pcie_pcs_tbl,3336		.pcs_num	= ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),3337		.pcs_misc	= sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,3338		.pcs_misc_num	= ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),3339	},3340 3341	.tbls_rc = &(const struct qmp_phy_cfg_tbls) {3342		.rx		= sm8350_qmp_gen3x2_pcie_rc_rx_tbl,3343		.rx_num		= ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl),3344		.pcs		= sm8350_qmp_gen3x2_pcie_rc_pcs_tbl,3345		.pcs_num	= ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl),3346	},3347 3348	.reset_list		= sdm845_pciephy_reset_l,3349	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),3350	.vreg_list		= qmp_phy_vreg_l,3351	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),3352	.regs			= pciephy_v5_regs_layout,3353 3354	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,3355	.phy_status		= PHYSTATUS,3356};3357 3358static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg = {3359	.lanes                  = 2,3360 3361	.offsets		= &qmp_pcie_offsets_v6_20,3362 3363	.tbls = {3364			.serdes         = sdx65_qmp_pcie_serdes_tbl,3365			.serdes_num     = ARRAY_SIZE(sdx65_qmp_pcie_serdes_tbl),3366			.tx             = sdx65_qmp_pcie_tx_tbl,3367			.tx_num         = ARRAY_SIZE(sdx65_qmp_pcie_tx_tbl),3368			.rx             = sdx65_qmp_pcie_rx_tbl,3369			.rx_num         = ARRAY_SIZE(sdx65_qmp_pcie_rx_tbl),3370			.pcs            = sdx65_qmp_pcie_pcs_tbl,3371			.pcs_num        = ARRAY_SIZE(sdx65_qmp_pcie_pcs_tbl),3372			.pcs_misc       = sdx65_qmp_pcie_pcs_misc_tbl,3373			.pcs_misc_num   = ARRAY_SIZE(sdx65_qmp_pcie_pcs_misc_tbl),3374		},3375	.reset_list             = sdm845_pciephy_reset_l,3376	.num_resets             = ARRAY_SIZE(sdm845_pciephy_reset_l),3377	.vreg_list              = qmp_phy_vreg_l,3378	.num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),3379	.regs                   = pciephy_v6_regs_layout,3380 3381	.pwrdn_ctrl             = SW_PWRDN,3382	.phy_status             = PHYSTATUS_4_20,3383};3384 3385static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {3386	.lanes			= 1,3387 3388	.offsets		= &qmp_pcie_offsets_v5,3389 3390	.tbls = {3391		.serdes		= sm8450_qmp_gen3_pcie_serdes_tbl,3392		.serdes_num	= ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),3393		.tx		= sm8450_qmp_gen3x1_pcie_tx_tbl,3394		.tx_num		= ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),3395		.rx		= sm8450_qmp_gen3_pcie_rx_tbl,3396		.rx_num		= ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),3397		.pcs		= sm8450_qmp_gen3_pcie_pcs_tbl,3398		.pcs_num	= ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),3399		.pcs_misc	= sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,3400		.pcs_misc_num	= ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),3401	},3402 3403	.tbls_rc = &(const struct qmp_phy_cfg_tbls) {3404		.serdes		= sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,3405		.serdes_num	= ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),3406		.rx		= sm8450_qmp_gen3x1_pcie_rc_rx_tbl,3407		.rx_num		= ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_rx_tbl),3408	},3409 3410	.reset_list		= sdm845_pciephy_reset_l,3411	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),3412	.vreg_list		= qmp_phy_vreg_l,3413	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),3414	.regs			= pciephy_v5_regs_layout,3415 3416	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,3417	.phy_status		= PHYSTATUS,3418};3419 3420static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {3421	.lanes			= 2,3422 3423	.offsets		= &qmp_pcie_offsets_v5_20,3424 3425	.tbls = {3426		.serdes		= sm8450_qmp_gen4x2_pcie_serdes_tbl,3427		.serdes_num	= ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),3428		.tx		= sm8450_qmp_gen4x2_pcie_tx_tbl,3429		.tx_num		= ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),3430		.rx		= sm8450_qmp_gen4x2_pcie_rx_tbl,3431		.rx_num		= ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),3432		.pcs		= sm8450_qmp_gen4x2_pcie_pcs_tbl,3433		.pcs_num	= ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),3434		.pcs_misc	= sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,3435		.pcs_misc_num	= ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),3436	},3437 3438	.tbls_rc = &(const struct qmp_phy_cfg_tbls) {3439		.serdes		= sm8450_qmp_gen4x2_pcie_rc_serdes_tbl,3440		.serdes_num	= ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_serdes_tbl),3441		.pcs_misc	= sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl,3442		.pcs_misc_num	= ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl),3443	},3444 3445	.tbls_ep = &(const struct qmp_phy_cfg_tbls) {3446		.serdes		= sm8450_qmp_gen4x2_pcie_ep_serdes_tbl,3447		.serdes_num	= ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_serdes_tbl),3448		.pcs_misc	= sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl,3449		.pcs_misc_num	= ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl),3450	},3451 3452	.reset_list		= sdm845_pciephy_reset_l,3453	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),3454	.vreg_list		= qmp_phy_vreg_l,3455	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),3456	.regs			= pciephy_v5_regs_layout,3457 3458	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,3459	.phy_status		= PHYSTATUS_4_20,3460 3461	/* 20MHz PHY AUX Clock */3462	.aux_clock_rate		= 20000000,3463};3464 3465static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg = {3466	.lanes = 2,3467 3468	.offsets		= &qmp_pcie_offsets_v5,3469 3470	.tbls = {3471		.serdes		= sm8550_qmp_gen3x2_pcie_serdes_tbl,3472		.serdes_num	= ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl),3473		.tx		= sm8550_qmp_gen3x2_pcie_tx_tbl,3474		.tx_num		= ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl),3475		.rx		= sm8550_qmp_gen3x2_pcie_rx_tbl,3476		.rx_num		= ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl),3477		.pcs		= sm8550_qmp_gen3x2_pcie_pcs_tbl,3478		.pcs_num	= ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl),3479		.pcs_misc	= sm8550_qmp_gen3x2_pcie_pcs_misc_tbl,3480		.pcs_misc_num	= ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl),3481	},3482	.reset_list		= sdm845_pciephy_reset_l,3483	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),3484	.vreg_list		= qmp_phy_vreg_l,3485	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),3486	.regs			= pciephy_v5_regs_layout,3487 3488	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,3489	.phy_status		= PHYSTATUS,3490};3491 3492static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = {3493	.lanes = 2,3494 3495	.offsets		= &qmp_pcie_offsets_v6_20,3496 3497	.tbls = {3498		.serdes			= sm8550_qmp_gen4x2_pcie_serdes_tbl,3499		.serdes_num		= ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl),3500		.tx			= sm8550_qmp_gen4x2_pcie_tx_tbl,3501		.tx_num			= ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl),3502		.rx			= sm8550_qmp_gen4x2_pcie_rx_tbl,3503		.rx_num			= ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_rx_tbl),3504		.pcs			= sm8550_qmp_gen4x2_pcie_pcs_tbl,3505		.pcs_num		= ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl),3506		.pcs_misc		= sm8550_qmp_gen4x2_pcie_pcs_misc_tbl,3507		.pcs_misc_num		= ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl),3508		.ln_shrd		= sm8550_qmp_gen4x2_pcie_ln_shrd_tbl,3509		.ln_shrd_num		= ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl),3510	},3511	.reset_list		= sdm845_pciephy_reset_l,3512	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),3513	.vreg_list		= sm8550_qmp_phy_vreg_l,3514	.num_vregs		= ARRAY_SIZE(sm8550_qmp_phy_vreg_l),3515	.regs			= pciephy_v6_regs_layout,3516 3517	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,3518	.phy_status		= PHYSTATUS_4_20,3519	.has_nocsr_reset	= true,3520 3521	/* 20MHz PHY AUX Clock */3522	.aux_clock_rate		= 20000000,3523};3524 3525static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pciephy_cfg = {3526	.lanes = 2,3527 3528	.offsets		= &qmp_pcie_offsets_v6_20,3529 3530	.tbls = {3531		.serdes			= sm8550_qmp_gen4x2_pcie_serdes_tbl,3532		.serdes_num		= ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl),3533		.tx			= sm8550_qmp_gen4x2_pcie_tx_tbl,3534		.tx_num			= ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl),3535		.rx			= sm8650_qmp_gen4x2_pcie_rx_tbl,3536		.rx_num			= ARRAY_SIZE(sm8650_qmp_gen4x2_pcie_rx_tbl),3537		.pcs			= sm8550_qmp_gen4x2_pcie_pcs_tbl,3538		.pcs_num		= ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl),3539		.pcs_misc		= sm8550_qmp_gen4x2_pcie_pcs_misc_tbl,3540		.pcs_misc_num		= ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl),3541		.ln_shrd		= sm8550_qmp_gen4x2_pcie_ln_shrd_tbl,3542		.ln_shrd_num		= ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl),3543	},3544	.reset_list		= sdm845_pciephy_reset_l,3545	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),3546	.vreg_list		= sm8550_qmp_phy_vreg_l,3547	.num_vregs		= ARRAY_SIZE(sm8550_qmp_phy_vreg_l),3548	.regs			= pciephy_v6_regs_layout,3549 3550	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,3551	.phy_status		= PHYSTATUS_4_20,3552	.has_nocsr_reset	= true,3553 3554	/* 20MHz PHY AUX Clock */3555	.aux_clock_rate		= 20000000,3556};3557 3558static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = {3559	.lanes			= 2,3560	.offsets		= &qmp_pcie_offsets_v5_20,3561 3562	.tbls = {3563		.serdes		= sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl,3564		.serdes_num		= ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl),3565		.tx		= sa8775p_qmp_gen4_pcie_tx_tbl,3566		.tx_num		= ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl),3567		.rx		= sa8775p_qmp_gen4x2_pcie_rx_alt_tbl,3568		.rx_num		= ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rx_alt_tbl),3569		.pcs		= sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl,3570		.pcs_num		= ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl),3571		.pcs_misc		= sa8775p_qmp_gen4_pcie_pcs_misc_tbl,3572		.pcs_misc_num	= ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),3573	},3574 3575	.tbls_rc = &(const struct qmp_phy_cfg_tbls) {3576		.serdes		= sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl,3577		.serdes_num	= ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl),3578		.pcs_misc	= sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl,3579		.pcs_misc_num	= ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),3580	},3581 3582	.tbls_ep = &(const struct qmp_phy_cfg_tbls) {3583		.serdes		= sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl,3584		.serdes_num	= ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl),3585		.pcs_misc	= sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl,3586		.pcs_misc_num	= ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl),3587		.pcs		= sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl,3588		.pcs_num	= ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_pcs_alt_tbl),3589	},3590 3591	.reset_list		= sdm845_pciephy_reset_l,3592	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),3593	.vreg_list		= qmp_phy_vreg_l,3594	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),3595	.regs			= pciephy_v5_regs_layout,3596 3597	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,3598	.phy_status		= PHYSTATUS_4_20,3599};3600 3601static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pciephy_cfg = {3602	.lanes = 4,3603	.offsets		= &qmp_pcie_offsets_v5_30,3604 3605	.tbls = {3606		.serdes		= sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl,3607		.serdes_num		= ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl),3608		.tx		= sa8775p_qmp_gen4_pcie_tx_tbl,3609		.tx_num		= ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl),3610		.rx			= sa8775p_qmp_gen4x4_pcie_rx_alt_tbl,3611		.rx_num		= ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rx_alt_tbl),3612		.pcs		= sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl,3613		.pcs_num		= ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl),3614		.pcs_misc		= sa8775p_qmp_gen4_pcie_pcs_misc_tbl,3615		.pcs_misc_num	= ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),3616	},3617 3618	.tbls_rc = &(const struct qmp_phy_cfg_tbls) {3619		.serdes		= sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl,3620		.serdes_num	= ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl),3621		.pcs_misc	= sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl,3622		.pcs_misc_num	= ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),3623	},3624 3625	.tbls_ep = &(const struct qmp_phy_cfg_tbls) {3626		.serdes		= sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl,3627		.serdes_num	= ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_ep_serdes_alt_tbl),3628		.pcs_misc	= sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl,3629		.pcs_misc_num	= ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl),3630	},3631 3632	.reset_list		= sdm845_pciephy_reset_l,3633	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),3634	.vreg_list		= qmp_phy_vreg_l,3635	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),3636	.regs			= pciephy_v5_regs_layout,3637 3638	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,3639	.phy_status		= PHYSTATUS_4_20,3640};3641 3642static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = {3643	.lanes = 2,3644 3645	.offsets		= &qmp_pcie_offsets_v6_20,3646 3647	.tbls = {3648		.serdes			= x1e80100_qmp_gen4x2_pcie_serdes_tbl,3649		.serdes_num		= ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_serdes_tbl),3650		.tx			= x1e80100_qmp_gen4x2_pcie_tx_tbl,3651		.tx_num			= ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_tx_tbl),3652		.rx			= x1e80100_qmp_gen4x2_pcie_rx_tbl,3653		.rx_num			= ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_rx_tbl),3654		.pcs			= x1e80100_qmp_gen4x2_pcie_pcs_tbl,3655		.pcs_num		= ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_tbl),3656		.pcs_misc		= x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl,3657		.pcs_misc_num		= ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl),3658		.ln_shrd		= x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl,3659		.ln_shrd_num		= ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl),3660	},3661 3662	.reset_list		= sdm845_pciephy_reset_l,3663	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),3664	.vreg_list		= qmp_phy_vreg_l,3665	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),3666	.regs			= pciephy_v6_regs_layout,3667 3668	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,3669	.phy_status		= PHYSTATUS_4_20,3670	.has_nocsr_reset	= true,3671};3672 3673static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = {3674	.lanes = 4,3675 3676	.offsets		= &qmp_pcie_offsets_v6_20,3677 3678	.tbls = {3679		.serdes			= x1e80100_qmp_gen4x2_pcie_serdes_tbl,3680		.serdes_num		= ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_serdes_tbl),3681		.tx			= x1e80100_qmp_gen4x2_pcie_tx_tbl,3682		.tx_num			= ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_tx_tbl),3683		.rx			= x1e80100_qmp_gen4x2_pcie_rx_tbl,3684		.rx_num			= ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_rx_tbl),3685		.pcs			= x1e80100_qmp_gen4x2_pcie_pcs_tbl,3686		.pcs_num		= ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_tbl),3687		.pcs_misc		= x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl,3688		.pcs_misc_num		= ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_pcs_misc_tbl),3689		.ln_shrd		= x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl,3690		.ln_shrd_num		= ARRAY_SIZE(x1e80100_qmp_gen4x2_pcie_ln_shrd_tbl),3691	},3692 3693	.serdes_4ln_tbl		= x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl,3694	.serdes_4ln_num		= ARRAY_SIZE(x1e80100_qmp_gen4x4_pcie_serdes_4ln_tbl),3695 3696	.reset_list		= sdm845_pciephy_reset_l,3697	.num_resets		= ARRAY_SIZE(sdm845_pciephy_reset_l),3698	.vreg_list		= qmp_phy_vreg_l,3699	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),3700	.regs			= pciephy_v6_regs_layout,3701 3702	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,3703	.phy_status		= PHYSTATUS_4_20,3704	.has_nocsr_reset	= true,3705};3706 3707static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)3708{3709	const struct qmp_phy_cfg *cfg = qmp->cfg;3710	const struct qmp_pcie_offsets *offs = cfg->offsets;3711	void __iomem *serdes, *tx3, *rx3, *tx4, *rx4, *pcs, *pcs_misc, *ln_shrd;3712 3713	serdes = qmp->port_b + offs->serdes;3714	tx3 = qmp->port_b + offs->tx;3715	rx3 = qmp->port_b + offs->rx;3716	tx4 = qmp->port_b + offs->tx2;3717	rx4 = qmp->port_b + offs->rx2;3718	pcs = qmp->port_b + offs->pcs;3719	pcs_misc = qmp->port_b + offs->pcs_misc;3720	ln_shrd = qmp->port_b + offs->ln_shrd;3721 3722	qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num);3723	qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num);3724 3725	qmp_configure_lane(qmp->dev, tx3, tbls->tx, tbls->tx_num, 1);3726	qmp_configure_lane(qmp->dev, rx3, tbls->rx, tbls->rx_num, 1);3727 3728	qmp_configure_lane(qmp->dev, tx4, tbls->tx, tbls->tx_num, 2);3729	qmp_configure_lane(qmp->dev, rx4, tbls->rx, tbls->rx_num, 2);3730 3731	qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num);3732	qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num);3733 3734	qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num);3735}3736 3737static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)3738{3739	const struct qmp_phy_cfg *cfg = qmp->cfg;3740	void __iomem *serdes = qmp->serdes;3741	void __iomem *tx = qmp->tx;3742	void __iomem *rx = qmp->rx;3743	void __iomem *tx2 = qmp->tx2;3744	void __iomem *rx2 = qmp->rx2;3745	void __iomem *pcs = qmp->pcs;3746	void __iomem *pcs_misc = qmp->pcs_misc;3747	void __iomem *ln_shrd = qmp->ln_shrd;3748 3749	if (!tbls)3750		return;3751 3752	qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num);3753 3754	qmp_configure_lane(qmp->dev, tx, tbls->tx, tbls->tx_num, 1);3755	qmp_configure_lane(qmp->dev, rx, tbls->rx, tbls->rx_num, 1);3756 3757	if (cfg->lanes >= 2) {3758		qmp_configure_lane(qmp->dev, tx2, tbls->tx, tbls->tx_num, 2);3759		qmp_configure_lane(qmp->dev, rx2, tbls->rx, tbls->rx_num, 2);3760	}3761 3762	qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num);3763	qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num);3764 3765	if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) {3766		qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl,3767			      cfg->serdes_4ln_num);3768		qmp_pcie_init_port_b(qmp, tbls);3769	}3770 3771	qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num);3772}3773 3774static int qmp_pcie_init(struct phy *phy)3775{3776	struct qmp_pcie *qmp = phy_get_drvdata(phy);3777	const struct qmp_phy_cfg *cfg = qmp->cfg;3778	int ret;3779 3780	ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);3781	if (ret) {3782		dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);3783		return ret;3784	}3785 3786	ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);3787	if (ret) {3788		dev_err(qmp->dev, "reset assert failed\n");3789		goto err_disable_regulators;3790	}3791 3792	ret = reset_control_assert(qmp->nocsr_reset);3793	if (ret) {3794		dev_err(qmp->dev, "no-csr reset assert failed\n");3795		goto err_assert_reset;3796	}3797 3798	usleep_range(200, 300);3799 3800	ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);3801	if (ret) {3802		dev_err(qmp->dev, "reset deassert failed\n");3803		goto err_assert_reset;3804	}3805 3806	ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);3807	if (ret)3808		goto err_assert_reset;3809 3810	return 0;3811 3812err_assert_reset:3813	reset_control_bulk_assert(cfg->num_resets, qmp->resets);3814err_disable_regulators:3815	regulator_bulk_disable(cfg->num_vregs, qmp->vregs);3816 3817	return ret;3818}3819 3820static int qmp_pcie_exit(struct phy *phy)3821{3822	struct qmp_pcie *qmp = phy_get_drvdata(phy);3823	const struct qmp_phy_cfg *cfg = qmp->cfg;3824 3825	reset_control_bulk_assert(cfg->num_resets, qmp->resets);3826 3827	clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);3828 3829	regulator_bulk_disable(cfg->num_vregs, qmp->vregs);3830 3831	return 0;3832}3833 3834static int qmp_pcie_power_on(struct phy *phy)3835{3836	struct qmp_pcie *qmp = phy_get_drvdata(phy);3837	const struct qmp_phy_cfg *cfg = qmp->cfg;3838	const struct qmp_phy_cfg_tbls *mode_tbls;3839	void __iomem *pcs = qmp->pcs;3840	void __iomem *status;3841	unsigned int mask, val;3842	int ret;3843 3844	qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],3845			cfg->pwrdn_ctrl);3846 3847	if (qmp->mode == PHY_MODE_PCIE_RC)3848		mode_tbls = cfg->tbls_rc;3849	else3850		mode_tbls = cfg->tbls_ep;3851 3852	qmp_pcie_init_registers(qmp, &cfg->tbls);3853	qmp_pcie_init_registers(qmp, mode_tbls);3854 3855	ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks);3856	if (ret)3857		return ret;3858 3859	ret = reset_control_deassert(qmp->nocsr_reset);3860	if (ret) {3861		dev_err(qmp->dev, "no-csr reset deassert failed\n");3862		goto err_disable_pipe_clk;3863	}3864 3865	/* Pull PHY out of reset state */3866	qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);3867 3868	/* start SerDes and Phy-Coding-Sublayer */3869	qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);3870 3871	if (!cfg->skip_start_delay)3872		usleep_range(1000, 1200);3873 3874	status = pcs + cfg->regs[QPHY_PCS_STATUS];3875	mask = cfg->phy_status;3876	ret = readl_poll_timeout(status, val, !(val & mask), 200,3877				 PHY_INIT_COMPLETE_TIMEOUT);3878	if (ret) {3879		dev_err(qmp->dev, "phy initialization timed-out\n");3880		goto err_disable_pipe_clk;3881	}3882 3883	return 0;3884 3885err_disable_pipe_clk:3886	clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);3887 3888	return ret;3889}3890 3891static int qmp_pcie_power_off(struct phy *phy)3892{3893	struct qmp_pcie *qmp = phy_get_drvdata(phy);3894	const struct qmp_phy_cfg *cfg = qmp->cfg;3895 3896	clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);3897 3898	/* PHY reset */3899	qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);3900 3901	/* stop SerDes and Phy-Coding-Sublayer */3902	qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],3903			SERDES_START | PCS_START);3904 3905	/* Put PHY into POWER DOWN state: active low */3906	qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],3907			cfg->pwrdn_ctrl);3908 3909	return 0;3910}3911 3912static int qmp_pcie_enable(struct phy *phy)3913{3914	int ret;3915 3916	ret = qmp_pcie_init(phy);3917	if (ret)3918		return ret;3919 3920	ret = qmp_pcie_power_on(phy);3921	if (ret)3922		qmp_pcie_exit(phy);3923 3924	return ret;3925}3926 3927static int qmp_pcie_disable(struct phy *phy)3928{3929	int ret;3930 3931	ret = qmp_pcie_power_off(phy);3932	if (ret)3933		return ret;3934 3935	return qmp_pcie_exit(phy);3936}3937 3938static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode)3939{3940	struct qmp_pcie *qmp = phy_get_drvdata(phy);3941 3942	switch (submode) {3943	case PHY_MODE_PCIE_RC:3944	case PHY_MODE_PCIE_EP:3945		qmp->mode = submode;3946		break;3947	default:3948		dev_err(&phy->dev, "Unsupported submode %d\n", submode);3949		return -EINVAL;3950	}3951 3952	return 0;3953}3954 3955static const struct phy_ops qmp_pcie_phy_ops = {3956	.power_on	= qmp_pcie_enable,3957	.power_off	= qmp_pcie_disable,3958	.set_mode	= qmp_pcie_set_mode,3959	.owner		= THIS_MODULE,3960};3961 3962static int qmp_pcie_vreg_init(struct qmp_pcie *qmp)3963{3964	const struct qmp_phy_cfg *cfg = qmp->cfg;3965	struct device *dev = qmp->dev;3966	int num = cfg->num_vregs;3967	int i;3968 3969	qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);3970	if (!qmp->vregs)3971		return -ENOMEM;3972 3973	for (i = 0; i < num; i++)3974		qmp->vregs[i].supply = cfg->vreg_list[i];3975 3976	return devm_regulator_bulk_get(dev, num, qmp->vregs);3977}3978 3979static int qmp_pcie_reset_init(struct qmp_pcie *qmp)3980{3981	const struct qmp_phy_cfg *cfg = qmp->cfg;3982	struct device *dev = qmp->dev;3983	int i;3984	int ret;3985 3986	qmp->resets = devm_kcalloc(dev, cfg->num_resets,3987				   sizeof(*qmp->resets), GFP_KERNEL);3988	if (!qmp->resets)3989		return -ENOMEM;3990 3991	for (i = 0; i < cfg->num_resets; i++)3992		qmp->resets[i].id = cfg->reset_list[i];3993 3994	ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);3995	if (ret)3996		return dev_err_probe(dev, ret, "failed to get resets\n");3997 3998	if (cfg->has_nocsr_reset) {3999		qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr");4000		if (IS_ERR(qmp->nocsr_reset))4001			return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset),4002						"failed to get no-csr reset\n");4003	}4004 4005	return 0;4006}4007 4008static int qmp_pcie_clk_init(struct qmp_pcie *qmp)4009{4010	struct device *dev = qmp->dev;4011	int num = ARRAY_SIZE(qmp_pciephy_clk_l);4012	int i;4013 4014	qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);4015	if (!qmp->clks)4016		return -ENOMEM;4017 4018	for (i = 0; i < num; i++)4019		qmp->clks[i].id = qmp_pciephy_clk_l[i];4020 4021	return devm_clk_bulk_get_optional(dev, num, qmp->clks);4022}4023 4024static void phy_clk_release_provider(void *res)4025{4026	of_clk_del_provider(res);4027}4028 4029/*4030 * Register a fixed rate pipe clock.4031 *4032 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate4033 * controls it. The <s>_pipe_clk coming out of the GCC is requested4034 * by the PHY driver for its operations.4035 * We register the <s>_pipe_clksrc here. The gcc driver takes care4036 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.4037 * Below picture shows this relationship.4038 *4039 *         +---------------+4040 *         |   PHY block   |<<---------------------------------------+4041 *         |               |                                         |4042 *         |   +-------+   |                   +-----+               |4043 *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+4044 *    clk  |   +-------+   |                   +-----+4045 *         +---------------+4046 */4047static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np)4048{4049	struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;4050	struct clk_init_data init = { };4051	int ret;4052 4053	ret = of_property_read_string_index(np, "clock-output-names", 0, &init.name);4054	if (ret) {4055		dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);4056		return ret;4057	}4058 4059	init.ops = &clk_fixed_rate_ops;4060 4061	/*4062	 * Controllers using QMP PHY-s use 125MHz pipe clock interface4063	 * unless other frequency is specified in the PHY config.4064	 */4065	if (qmp->cfg->pipe_clock_rate)4066		fixed->fixed_rate = qmp->cfg->pipe_clock_rate;4067	else4068		fixed->fixed_rate = 125000000;4069 4070	fixed->hw.init = &init;4071 4072	return devm_clk_hw_register(qmp->dev, &fixed->hw);4073}4074 4075/*4076 * Register a fixed rate PHY aux clock.4077 *4078 * The <s>_phy_aux_clksrc generated by PHY goes to the GCC that gate4079 * controls it. The <s>_phy_aux_clk coming out of the GCC is requested4080 * by the PHY driver for its operations.4081 * We register the <s>_phy_aux_clksrc here. The gcc driver takes care4082 * of assigning this <s>_phy_aux_clksrc as parent to <s>_phy_aux_clk.4083 * Below picture shows this relationship.4084 *4085 *         +---------------+4086 *         |   PHY block   |<<---------------------------------------------+4087 *         |               |                                               |4088 *         |   +-------+   |                      +-----+                  |4089 *   I/P---^-->|  PLL  |---^--->phy_aux_clksrc--->| GCC |--->phy_aux_clk---+4090 *    clk  |   +-------+   |                      +-----+4091 *         +---------------+4092 */4093static int phy_aux_clk_register(struct qmp_pcie *qmp, struct device_node *np)4094{4095	struct clk_fixed_rate *fixed = &qmp->aux_clk_fixed;4096	struct clk_init_data init = { };4097	char name[64];4098 4099	snprintf(name, sizeof(name), "%s::phy_aux_clk", dev_name(qmp->dev));4100 4101	init.name = name;4102	init.ops = &clk_fixed_rate_ops;4103 4104	fixed->fixed_rate = qmp->cfg->aux_clock_rate;4105	fixed->hw.init = &init;4106 4107	return devm_clk_hw_register(qmp->dev, &fixed->hw);4108}4109 4110static struct clk_hw *qmp_pcie_clk_hw_get(struct of_phandle_args *clkspec, void *data)4111{4112	struct qmp_pcie *qmp = data;4113 4114	/* Support legacy bindings */4115	if (!clkspec->args_count)4116		return &qmp->pipe_clk_fixed.hw;4117 4118	switch (clkspec->args[0]) {4119	case QMP_PCIE_PIPE_CLK:4120		return &qmp->pipe_clk_fixed.hw;4121	case QMP_PCIE_PHY_AUX_CLK:4122		return &qmp->aux_clk_fixed.hw;4123	}4124 4125	return ERR_PTR(-EINVAL);4126}4127 4128static int qmp_pcie_register_clocks(struct qmp_pcie *qmp, struct device_node *np)4129{4130	int ret;4131 4132	ret = phy_pipe_clk_register(qmp, np);4133	if (ret)4134		return ret;4135 4136	if (qmp->cfg->aux_clock_rate) {4137		ret = phy_aux_clk_register(qmp, np);4138		if (ret)4139			return ret;4140 4141		ret = of_clk_add_hw_provider(np, qmp_pcie_clk_hw_get, qmp);4142		if (ret)4143			return ret;4144	} else {4145		ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &qmp->pipe_clk_fixed.hw);4146		if (ret)4147			return ret;4148	}4149 4150	/*4151	 * Roll a devm action because the clock provider is the child node, but4152	 * the child node is not actually a device.4153	 */4154	return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);4155}4156 4157static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np)4158{4159	struct platform_device *pdev = to_platform_device(qmp->dev);4160	const struct qmp_phy_cfg *cfg = qmp->cfg;4161	struct device *dev = qmp->dev;4162	struct clk *clk;4163 4164	qmp->serdes = devm_platform_ioremap_resource(pdev, 0);4165	if (IS_ERR(qmp->serdes))4166		return PTR_ERR(qmp->serdes);4167 4168	/*4169	 * Get memory resources for the PHY:4170	 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.4171	 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 54172	 * For single lane PHYs: pcs_misc (optional) -> 3.4173	 */4174	qmp->tx = devm_of_iomap(dev, np, 0, NULL);4175	if (IS_ERR(qmp->tx))4176		return PTR_ERR(qmp->tx);4177 4178	if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy"))4179		qmp->rx = qmp->tx;4180	else4181		qmp->rx = devm_of_iomap(dev, np, 1, NULL);4182	if (IS_ERR(qmp->rx))4183		return PTR_ERR(qmp->rx);4184 4185	qmp->pcs = devm_of_iomap(dev, np, 2, NULL);4186	if (IS_ERR(qmp->pcs))4187		return PTR_ERR(qmp->pcs);4188 4189	if (cfg->lanes >= 2) {4190		qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);4191		if (IS_ERR(qmp->tx2))4192			return PTR_ERR(qmp->tx2);4193 4194		qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);4195		if (IS_ERR(qmp->rx2))4196			return PTR_ERR(qmp->rx2);4197 4198		qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);4199	} else {4200		qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);4201	}4202 4203	if (IS_ERR(qmp->pcs_misc) &&4204	    of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy"))4205		qmp->pcs_misc = qmp->pcs + 0x400;4206 4207	if (IS_ERR(qmp->pcs_misc)) {4208		if (cfg->tbls.pcs_misc ||4209		    (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) ||4210		    (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) {4211			return PTR_ERR(qmp->pcs_misc);4212		}4213	}4214 4215	clk = devm_get_clk_from_child(dev, np, NULL);4216	if (IS_ERR(clk)) {4217		return dev_err_probe(dev, PTR_ERR(clk),4218				     "failed to get pipe clock\n");4219	}4220 4221	qmp->num_pipe_clks = 1;4222	qmp->pipe_clks[0].id = "pipe";4223	qmp->pipe_clks[0].clk = clk;4224 4225	return 0;4226}4227 4228static int qmp_pcie_get_4ln_config(struct qmp_pcie *qmp)4229{4230	struct regmap *tcsr;4231	unsigned int args[2];4232	int ret;4233 4234	tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node,4235						    "qcom,4ln-config-sel",4236						    ARRAY_SIZE(args), args);4237	if (IS_ERR(tcsr)) {4238		ret = PTR_ERR(tcsr);4239		if (ret == -ENOENT)4240			return 0;4241 4242		dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret);4243		return ret;4244	}4245 4246	ret = regmap_test_bits(tcsr, args[0], BIT(args[1]));4247	if (ret < 0) {4248		dev_err(qmp->dev, "failed to read tcsr: %d\n", ret);4249		return ret;4250	}4251 4252	qmp->tcsr_4ln_config = ret;4253 4254	dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config);4255 4256	return 0;4257}4258 4259static int qmp_pcie_parse_dt(struct qmp_pcie *qmp)4260{4261	struct platform_device *pdev = to_platform_device(qmp->dev);4262	const struct qmp_phy_cfg *cfg = qmp->cfg;4263	const struct qmp_pcie_offsets *offs = cfg->offsets;4264	struct device *dev = qmp->dev;4265	void __iomem *base;4266	int ret;4267 4268	if (!offs)4269		return -EINVAL;4270 4271	ret = qmp_pcie_get_4ln_config(qmp);4272	if (ret)4273		return ret;4274 4275	base = devm_platform_ioremap_resource(pdev, 0);4276	if (IS_ERR(base))4277		return PTR_ERR(base);4278 4279	qmp->serdes = base + offs->serdes;4280	qmp->pcs = base + offs->pcs;4281	qmp->pcs_misc = base + offs->pcs_misc;4282	qmp->tx = base + offs->tx;4283	qmp->rx = base + offs->rx;4284 4285	if (cfg->lanes >= 2) {4286		qmp->tx2 = base + offs->tx2;4287		qmp->rx2 = base + offs->rx2;4288	}4289 4290	if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) {4291		qmp->port_b = devm_platform_ioremap_resource(pdev, 1);4292		if (IS_ERR(qmp->port_b))4293			return PTR_ERR(qmp->port_b);4294	}4295 4296	if (cfg->tbls.ln_shrd)4297		qmp->ln_shrd = base + offs->ln_shrd;4298 4299	qmp->num_pipe_clks = 2;4300	qmp->pipe_clks[0].id = "pipe";4301	qmp->pipe_clks[1].id = "pipediv2";4302 4303	ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks);4304	if (ret)4305		return ret;4306 4307	ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1);4308	if (ret)4309		return ret;4310 4311	return 0;4312}4313 4314static int qmp_pcie_probe(struct platform_device *pdev)4315{4316	struct device *dev = &pdev->dev;4317	struct phy_provider *phy_provider;4318	struct device_node *np;4319	struct qmp_pcie *qmp;4320	int ret;4321 4322	qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);4323	if (!qmp)4324		return -ENOMEM;4325 4326	qmp->dev = dev;4327 4328	qmp->cfg = of_device_get_match_data(dev);4329	if (!qmp->cfg)4330		return -EINVAL;4331 4332	WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl);4333	WARN_ON_ONCE(!qmp->cfg->phy_status);4334 4335	ret = qmp_pcie_clk_init(qmp);4336	if (ret)4337		return ret;4338 4339	ret = qmp_pcie_reset_init(qmp);4340	if (ret)4341		return ret;4342 4343	ret = qmp_pcie_vreg_init(qmp);4344	if (ret)4345		return ret;4346 4347	/* Check for legacy binding with child node. */4348	np = of_get_next_available_child(dev->of_node, NULL);4349	if (np) {4350		ret = qmp_pcie_parse_dt_legacy(qmp, np);4351	} else {4352		np = of_node_get(dev->of_node);4353		ret = qmp_pcie_parse_dt(qmp);4354	}4355	if (ret)4356		goto err_node_put;4357 4358	ret = qmp_pcie_register_clocks(qmp, np);4359	if (ret)4360		goto err_node_put;4361 4362	qmp->mode = PHY_MODE_PCIE_RC;4363 4364	qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops);4365	if (IS_ERR(qmp->phy)) {4366		ret = PTR_ERR(qmp->phy);4367		dev_err(dev, "failed to create PHY: %d\n", ret);4368		goto err_node_put;4369	}4370 4371	phy_set_drvdata(qmp->phy, qmp);4372 4373	of_node_put(np);4374 4375	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);4376 4377	return PTR_ERR_OR_ZERO(phy_provider);4378 4379err_node_put:4380	of_node_put(np);4381	return ret;4382}4383 4384static const struct of_device_id qmp_pcie_of_match_table[] = {4385	{4386		.compatible = "qcom,ipq6018-qmp-pcie-phy",4387		.data = &ipq6018_pciephy_cfg,4388	}, {4389		.compatible = "qcom,ipq8074-qmp-gen3-pcie-phy",4390		.data = &ipq8074_pciephy_gen3_cfg,4391	}, {4392		.compatible = "qcom,ipq8074-qmp-pcie-phy",4393		.data = &ipq8074_pciephy_cfg,4394	}, {4395		.compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy",4396		.data = &ipq9574_gen3x1_pciephy_cfg,4397	}, {4398		.compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy",4399		.data = &ipq9574_gen3x2_pciephy_cfg,4400	}, {4401		.compatible = "qcom,msm8998-qmp-pcie-phy",4402		.data = &msm8998_pciephy_cfg,4403	}, {4404		.compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy",4405		.data = &sa8775p_qmp_gen4x2_pciephy_cfg,4406	}, {4407		.compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy",4408		.data = &sa8775p_qmp_gen4x4_pciephy_cfg,4409	}, {4410		.compatible = "qcom,sc8180x-qmp-pcie-phy",4411		.data = &sc8180x_pciephy_cfg,4412	}, {4413		.compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy",4414		.data = &sc8280xp_qmp_gen3x1_pciephy_cfg,4415	}, {4416		.compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy",4417		.data = &sc8280xp_qmp_gen3x2_pciephy_cfg,4418	}, {4419		.compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy",4420		.data = &sc8280xp_qmp_gen3x4_pciephy_cfg,4421	}, {4422		.compatible = "qcom,sdm845-qhp-pcie-phy",4423		.data = &sdm845_qhp_pciephy_cfg,4424	}, {4425		.compatible = "qcom,sdm845-qmp-pcie-phy",4426		.data = &sdm845_qmp_pciephy_cfg,4427	}, {4428		.compatible = "qcom,sdx55-qmp-pcie-phy",4429		.data = &sdx55_qmp_pciephy_cfg,4430	}, {4431		.compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy",4432		.data = &sdx65_qmp_pciephy_cfg,4433	}, {4434		.compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy",4435		.data = &sm8250_qmp_gen3x1_pciephy_cfg,4436	}, {4437		.compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy",4438		.data = &sm8250_qmp_gen3x2_pciephy_cfg,4439	}, {4440		.compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",4441		.data = &sm8250_qmp_gen3x1_pciephy_cfg,4442	}, {4443		.compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",4444		.data = &sm8250_qmp_gen3x2_pciephy_cfg,4445	}, {4446		.compatible = "qcom,sm8250-qmp-modem-pcie-phy",4447		.data = &sm8250_qmp_gen3x2_pciephy_cfg,4448	}, {4449		.compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy",4450		.data = &sm8350_qmp_gen3x1_pciephy_cfg,4451	}, {4452		.compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy",4453		.data = &sm8350_qmp_gen3x2_pciephy_cfg,4454	}, {4455		.compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",4456		.data = &sm8450_qmp_gen3x1_pciephy_cfg,4457	}, {4458		.compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",4459		.data = &sm8450_qmp_gen4x2_pciephy_cfg,4460	}, {4461		.compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy",4462		.data = &sm8550_qmp_gen3x2_pciephy_cfg,4463	}, {4464		.compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy",4465		.data = &sm8550_qmp_gen4x2_pciephy_cfg,4466	}, {4467		.compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy",4468		.data = &sm8550_qmp_gen3x2_pciephy_cfg,4469	}, {4470		.compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy",4471		.data = &sm8650_qmp_gen4x2_pciephy_cfg,4472	}, {4473		.compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy",4474		.data = &sm8550_qmp_gen3x2_pciephy_cfg,4475	}, {4476		.compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy",4477		.data = &x1e80100_qmp_gen4x2_pciephy_cfg,4478	}, {4479		.compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy",4480		.data = &x1e80100_qmp_gen4x4_pciephy_cfg,4481	},4482	{ },4483};4484MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table);4485 4486static struct platform_driver qmp_pcie_driver = {4487	.probe		= qmp_pcie_probe,4488	.driver = {4489		.name	= "qcom-qmp-pcie-phy",4490		.of_match_table = qmp_pcie_of_match_table,4491	},4492};4493 4494module_platform_driver(qmp_pcie_driver);4495 4496MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");4497MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver");4498MODULE_LICENSE("GPL v2");4499