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1/* Only for QMP V5 PHY - UFS PCS registers */2/* SPDX-License-Identifier: GPL-2.0 */3/*4 * Copyright (c) 2017, The Linux Foundation. All rights reserved.5 */6 7#ifndef QCOM_PHY_QMP_PCS_UFS_V5_H_8#define QCOM_PHY_QMP_PCS_UFS_V5_H_9 10/* Only for QMP V5 PHY - UFS PCS registers */11#define QPHY_V5_PCS_UFS_PHY_START 0x00012#define QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL 0x00413#define QPHY_V5_PCS_UFS_SW_RESET 0x00814#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c15#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x01016#define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c17#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x03018#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x03819#define QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL 0x06020#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x07421#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b422#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x12423#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x15024#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x15425#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x15826#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x16027#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x16828#define QPHY_V5_PCS_UFS_READY_STATUS 0x18029#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d830#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e031 32#endif33